Papers by Ronald Gyurcsik
IEEE Journal of Solid-State Circuits, 1989
Routing is a major obstacle in the design of analog VLSI circuits, and, in general, is much more ... more Routing is a major obstacle in the design of analog VLSI circuits, and, in general, is much more critical than that of digital circuits. The coupling of signals between sensitive nets by signals from digital and large-swing analog nets, effects of unwanted parasitic capacitances due to overlapping, and effects of voltage drops in nets must be accounted for when routing. This paper describes a generalized algorithm for two-layer detailed channel routing of mixed analog and digital signal nets. In this algorithm nets are classified based on the type of signal they cany. A table stores classification-dependent information including data to calculate minimum net-to-net spacing, sensitivity to parasitic capacitances, and the single-layer-only routing requirement. The routing channel is represented by a weighted directed graph. The graph represents relative positions of nets within the channel. The edge weights and directions in the graph are assigned to account for the analog routing concerns provided in the net classification table.
IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part C, 1997
This paper describes a new methodology for equipment fault detection. The key features of this me... more This paper describes a new methodology for equipment fault detection. The key features of this methodology are that it allows for the incorporation of spatial information and that it can be used to detect and diagnose equipment faults simultaneously. This methodology consists of constructing a virtual wafer surface from spatial data and using physically based spatial signature metrics to compare the virtual wafer surface to an established baseline process surface in order to detect equipment faults. Statistical distributional studies of the spatial signature metrics provide the justification of determining the significance of the spatial signature. Data collected from a rapid thermal chemical vapor deposition (RTCVD) process and from a plasma enhanced chemical vapor deposition (PECVD) process are used to illustrate the procedures. This method detected equipment faults for all 11 wafers that were subjected to induced equipment faults in the RTCVD process, and even diagnosed the type of equipment fault for 10 of these wafers. This method also detected 42 of 44 induced equipment faults in the PECVD process.
Proceedings of the IEEE 1988 Custom Integrated Circuits Conference, 1988
... NETS Jzan-Ching Jeen, Ronald S . Gyurcsik, and Wen-Tai Liu ... Ni. A more extensive example i... more ... NETS Jzan-Ching Jeen, Ronald S . Gyurcsik, and Wen-Tai Liu ... Ni. A more extensive example is given in Figure 4. Figure 4(a) shows the area-"ized routing excluding analog con-straints, and Figure 4(b) includes the constraints. ...
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1989
... However, there is no guarantee that these claims are for the worst-case test results and not ... more ... However, there is no guarantee that these claims are for the worst-case test results and not for the best-case re-sults. ACKNOWLEDGMENT ... His research interests include CAD tools for failureanalysis and testing. radiation effects on ~C'S. and fabrication process modeling. * ...
Journal of the American Statistical Association, 1998
An important diagnostic tool of semiconductor fabrication processes is within-wafer uniformity. G... more An important diagnostic tool of semiconductor fabrication processes is within-wafer uniformity. Given some required standard (for example, deposition of 1000 angstroms of polysilicon on a blanket of silicon dioxide), the goal is to determine optimum process conditions that will achieve this requirement uniformly across the wafer, despite possible spatial anomalies in the fabrication process. Processes are traditionally optimized with respect'to the process operating conditions, without regard to spatial dependence. Nevertheless, this spatial dependence can be very important, and is thus accounted for in our modeling of the mean, variance, and correlation of measurements taken on a wafer. Moreover, the uniformity (or lack thereoO of the wafer surface is investigated by the use of different metrics-based on simple averages of absolute error, or on a thin plate spline of the error surface. These metrics ar~then employed in the optimization of the process. The techniques are illustrated through application to a Rapid Thermal Chemical Vapor Deposition process.
Recent trends in the semiconductor industry indicate the need to explore alternatives to batch-wa... more Recent trends in the semiconductor industry indicate the need to explore alternatives to batch-wafer manufacturing. One proposed alternative is a micro-factory based on cluster tools. This paper presents an analysis of the effect of redundant chamhers and chamber revisitation process sequences on the throughput in an individual cluster tool. Theoretical models which quantify the time required to process a lot of wafers in a cluster tool are developed for these situations. The differences between scheduling algorithms which use the load-lock as a queue and those that do not are also explored. Finally, the models developed in the work are integrated into a model which bounds the minimum theoretical turn-around-time which can be achieved in a cluster based fab.
Guest Editors' Introduction L.R. Carley, R.S. Gyurcsik. Sframe: an Efficient System for Detai... more Guest Editors' Introduction L.R. Carley, R.S. Gyurcsik. Sframe: an Efficient System for Detailed DC Simulation of Bipolar Analog Integrated Circuits using Continuation Methods R. Melville, S. Moinian, P. Feldmann, L. Watson. A Higher Level Modeling Procedure for Analog Integrated Circuits H.A. Mantooth, P.E. Allen. Ariadne: a Constraint-Based Approach to Computer-Aided Synthesis and Modeling of Analog Integrated Circuits K. Swings, W. Sansen. Analog Integrated Filter Compilation R.K. Henderson, Li Ping, J.I. Sewel. CAD Tools for the Synthesis and Layout of SC Filters and Networks A. Muralt, P. Zbinden, G.S. Moschytz. OTA-C Biquad-Based Filter Silicon Compiler M.R. Kobe, E. Sanchez-Sinencio, J. Ramirez-Angulo. Design of Multibit Noise-Shaping Data Converters J.G. Kenney, L.R. Carley.
The performance, cost and reliability of semiconductor processing equipment is greatly affected b... more The performance, cost and reliability of semiconductor processing equipment is greatly affected by the number and type of sensors and actuators used within the equipment. Current semiconductor processing equipment can include over one thousand sensors and actuators of varying accuracy, cost and performance. The integration of theses sensors and actuators is further complicated by varying, non-standard electrical interfaces to them.
Modern statistical modeling techniques are applied to the characterization and optimization of ra... more Modern statistical modeling techniques are applied to the characterization and optimization of rapid thermal chemical vapor deposition. The problems of deposition during process ramps and thickness uniformity modeling wafer are addressed. A two-phase fractional factorial experimental design is used to generate models for the deposition rate, uniformity measures, and normalized time responses. A constrained algebraic optimization algorithm is used to
Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91, 1991
This paper describes an algorithm that uses dynamic programming to order IC tests so that faulty ... more This paper describes an algorithm that uses dynamic programming to order IC tests so that faulty circuits are detected early in the test sequence and the average test time is minimized. An accurate estimate of the probabilities of individual tests failing, and the joint probabilities of several tests failing is required. These probabilities can be estimated using statistical simulation techniques
Advanced Techniques for Integrated Circuit Processing, 1991
Manufacturing Process Control for Microelectronic Devices and Circuits, 1994
Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97, 1997
Two techniques are presented that are expected to greatly enhance wireless data collection from h... more Two techniques are presented that are expected to greatly enhance wireless data collection from high-bandwidth biosensors. By steering the aggregate magnetic field from a (near-) orthogonal set of AC-energized coils, selected sensor implants can be powered and communicated with. Communication with individual implants can also be enhanced through half-cycle amplitude modulation. This technique allows bit rates of up to twice
Proceedings of 1997 IEEE International Symposium on Circuits and Systems. Circuits and Systems in the Information Age ISCAS '97, 1997
This paper describes an analog continuous-time adaptive cable equalizer that can be implemented i... more This paper describes an analog continuous-time adaptive cable equalizer that can be implemented in a standard CMOS integrated circuit technology. The equalizer can be designed with as many poles and zeros as are necessary to compensate for cable distortion. However, only two control voltages, gain control and bandwidth control, are needed for adaptive control of the equalizer. By properly designing the relative locations of the poles and zeros, these control voltages will adjust to compensate for cable distortion and the large process and temperature tolerances on the integrated circuit. Since there are only two control voltages, the circuitry required to produce these control voltages is very simple. Also, if independent parameters of the received signal are used to develop these control voltages, such as the autocorrelation and the signal amplitude, no training is required to adapt the equalizer. Since the gain of the equalizer can be adjusted independently of the shape of the frequency response, no additional VGA is necessary
Proceedings of the 1988 ACM sixteenth annual conference on Computer science - CSC '88, 1988
This paper discusses a software system made possible by the current advances in distributed proce... more This paper discusses a software system made possible by the current advances in distributed processing, high-speed computer networks, and concurrent language implementation. The system discussed herein consists of several software layers. At the core of the system lies the UNIX#8482; operating system. This particular operating system provides an extensible set of communication domains which support communication within one UNIX system
Proceedings of the 28th conference on ACM/IEEE design automation conference - DAC '91, 1991
This paper describes a methodology for the automatic generation of the performance sensitivities ... more This paper describes a methodology for the automatic generation of the performance sensitivities for analog cells directly from their design specifications. The resulting sensitivities can be used in automating the layout of analog ICs. A program was built in C to verify the concept. The program allows the user to describe the performance functions in terms of voltages and currents
Rapid Thermal and Integrated Processing, 1992
Proceedings of IEEE International Symposium on Circuits and Systems - ISCAS '94, 1994
Synapse, neuron, and weight increment circuits for a high density, temperature-compensated analog... more Synapse, neuron, and weight increment circuits for a high density, temperature-compensated analog VLSI neural network are introduced. The synapse circuit, which consumes 4500 μm2 in a 2-μm technology, uses hybrid dynamic and non-volatile weight storage. Dynamic memory allows fast learning while non-volatile memory allows reliable long-term storage and low power dissipation. Measured test results for the synapse are presented. The
IEEE Transactions on Components, Packaging, and Manufacturing Technology: Part C, 1996
Within-wafer uniformity is traditionally measured by the signal-to-noise ratio (SNR), defined as ... more Within-wafer uniformity is traditionally measured by the signal-to-noise ratio (SNR), defined as the estimated standard-deviation of within-wafer measurements over the mean of those measurements. Unfortunately, in the presence of deterministic variations of the response over the wafer (such as the bull's eye effect of some processes), the SNR is sensitive to both the location and the number of the measurements taken. A robust metric for describing within-wafer uniformity is developed and compared with the SNR method. The new metric, termed the integration statistic (I) is shown to be robust to both the location and number of measurements taken on the wafer and has lower variance than the SNR metric. The implications of this robust behavior are that fewer measurements can be taken to achieve a given accuracy in the uniformity estimate and that uniformity estimates are consistent with respect to variations in the orientation of the uniformity pattern to the measurement pattern.
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Papers by Ronald Gyurcsik