Analog VLSI

The fact that wide bandgap semiconductors are capable of electronic functionality at much higher temperatures than silicon has partially fueled their development, particularly in the case of SiC. It appears unlikely that wide bandgap semiconductor devices will find much use in low-power transistor applications until the ambient temperature exceeds approximately 300°C, as commercially available silicon and silicon-on-insulator technologies are already satisfying requirements for digital and analog VLSI in this temperature range. However practical operation of silicon power devices at ambient temperatures above 200°C appears problematic, as self-heating at higher power levels results in high internal junction temperatures and leakages. Thus, most electronic subsystems that simultaneously require high-temperature and high-power operation will necessarily be realized using wide bandgap devices, once they become widely available. Technological challenges impeding the realization of beneficial wide bandgap high ambient temperature electronics, including material growth, contacts, and packaging, are briefly discussed.

New CMOS rail to rail second generation current conveyor circuits are proposed. First a class A current conveyor circuit which operates from a single supply of 1.5 V with a rail to rail voltage swing capability is given. The circuit is then modified to work as a class AB while maintaining the rail to rail swing capability. The class AB circuit works from supply voltages down to +1.1 V with standby current of 56 A. These new current conveyor realizations are insensitive to the threshold voltage variation caused by the body effect, which minimizes the layout area and makes both circuits a valuable addition to the analog VLSI libraries. PSpice simulation confirms the attractive properties of the proposed circuits.

We present analog VLSI neuromorphic architectures for a general class of learning tasks, which include supervised learning, reinforcement learning, and temporal difference learning. The presented architectures are parallel, cellular, sparse in global interconnects, distributed in representation, and robust to noise and mismatches in the implementation. They use a parallel stochastic perturbation technique to estimate the effect of weight changes on network outputs, rather than calculating derivatives based on a model of the network. This "model-free" technique avoids errors due to mismatches in the physical implementation of the network, and more generally allows to train networks of which the exact characteristics and structure are not known. With additional mechanisms of reinforcement learning, networks of fairly general structure are trained effectively from an arbitrarily supplied reward signal. No prior assumptions are required on the structure of the network nor on the specifics of the desired network response.

Electrical activity in the brain spans a wide range of spatial and temporal scales, requiring simultaneous recording of multiple modalities of neurophysiological signals in order to capture various aspects of brain state dynamics. Here, we present a 16-channel neural interface integrated circuit fabricated in a 0.5 μm 3M2P CMOS process for selective digital acquisition of biopotentials across the spectrum of neural signal modalities in the brain, ranging from single spike action potentials to local field potentials (LFP), electrocorticograms (ECoG), and electroencephalograms (EEG). Each channel is composed of a tunable bandwidth, fixed gain front-end amplifier and a programmable gain/resolution continuous-time incremental ΔΣ analog-to-digital converter (ADC). A two-stage topology for the front-end voltage amplifier with capacitive feedback offers independent tuning of the amplifier bandpass frequency corners, and attains a noise efficiency factor (NEF) of 2.9 at 8.2 kHz bandwidth for spike recording, and a NEF of 3.2 at 140 Hz bandwidth for EEG recording. The amplifier has a measured midband gain of 39.6 dB, frequency response from 0.2 Hz to 8.2 kHz, and an input-referred noise of 1.94 μV rms while drawing 12.2 μA of current from a 3.3 V supply. The lower and higher cutoff frequencies of the bandpass filter are adjustable from 0.2 to 94 Hz and 140 Hz to 8.2 kHz, respectively. At 10-bit resolution, the ADC has an SNDR of 56 dB while consuming 76 μW power. Time-modulation feedback in the ADC offers programmable digital gain (1-4096) for auto-ranging, further improving the dynamic range and linearity of the ADC. Experimental recordings with the system show spike signals in rat somatosensory cortex as well as alpha EEG activity in a human subject.

A new CMOS programmable balanced output transconductor (BOTA) is introduced. The BOTA is a useful block for continuous-time analog signal processing. A new CMOS realization based on MOS transistors operating in the saturation region is given. Application of the BOTA in realizing bandpass-lowpass-allpass-notch biquad mixed mode filter using four BOTAs and two grounded capacitors and in realizing current mode MOS-C oscillators using three or four BOTAs and two grounded capacitors are given. PSpice simulation results for the BOTA circuit and for its applications are also included. ᭧

MOS transistor mismatch is revisited in the context of subthreshold operation and VLSI systems. We report experimental measurements from large transistor arrays with device sizes typical for digital and analog VLSI systems (areas between 9 and 400μm2). These are fabricated at different production qualified facilities in 40-nm gate oxide,n-well andp-well, mask lithography processes. Within the small area of our test-strips (3 mm2), transistor mismatch can be classified into four categories: random variations, “edge,” “striation,” and “gradient” effects. The edge effect manifests itself as a dependence of the transistor current on its position with reference to the surrounding structures. Contrary to what was previously believed, edge effects extend beyond the outer most devices in the array. The striation effect exhibits itself as a position-dependent variation in transistor current following a sinusoidal oscillation in space of slowly varying frequency. The gradient effect is also a position-dependent spatial variation but of much lower frequency. When systematic effects are removed from the data, the random variations follow an inverse linear dependence on the square root of transistor area.

An analog system-on-chip for kernel-based pattern classification and sequence estimation is presented. State transition probabilities conditioned on input data are generated by an integrated support vector machine. Dot product based kernels and support vector coefficients are implemented in analog programmable floating gate translinear circuits, and probabilities are propagated and normalized using sub-threshold current-mode circuits. A 14-input, 24-state, and 720-support vector forward decoding kernel machine is integrated on a 3mm×3mm chip in 0.5µm CMOS technology. Experiments with the processor trained for speaker verification and phoneme sequence estimation demonstrate real-time recognition accuracy at par with floating-point software, at sub-microwatt power.

Previous work on analog VLSI implementation of multi-layer perceptrons with on-chip learning has mainly targeted the implementation of algorithms like backpropagation. Although back-propagation is ecient, its implementation in analog VLSI requires excessive computational hardware. In this paper we show that using gradient descent with direct approximation of the gradient instead of backpropagation is cheapest for parallel analog implementations. We also show that this technique (we call \weight perturbation") is suitable for multi-layer recurrent networks as well. A discrete level analog implementation showing the training of an XOR network as an example is also presented.

We present a mixed-mode analog/digital VLSI device comprising an array of leaky integrate-and-fire (I&F) neurons, adaptive synapses with spike-timing dependent plasticity, and an asynchronous event based communication infrastructure that allows the user to (re)configure networks of spiking neurons with arbitrary topologies. The asynchronous communication protocol used by the silicon neurons to transmit spikes (events) off-chip and the silicon synapses to receive spikes from the outside is based on the "address-event representation" (AER). We describe the analog circuits designed to implement the silicon neurons and synapses and present experimental data showing the neuron's response properties and the synapses characteristics, in response to AER input spike trains. Our results indicate that these circuits can be used in massively parallel VLSI networks of I&F neurons to simulate real-time complex spike-based learning algorithms.

Many time-critical neural network applications require fully parallel hardware implementations for maximal throughput. We first survey the rich array of technologies that are being pursued, then focus on the analog CMOS VLSI medium. Although analog VLSI holds great promise for implementing dense neural networks in a fully parallel manner, the medium is "messy" in that limited dynamic range, offset voltages, and noise sources all conspire to reduce precision. Many traditional neural models may be difficult to implement in analog technology. In this paper, we examine how neqral networks may be directly implemented in analog VLSI, giving examples of approaches that have been pursued to date. Two important application areas are highlighted Optimization, because neural hardware may offer a speed advantage of orders of magnitude over other methods, and supervised learning, because of the widespread use and generality of gradient-descent learning algorithms as applied to feedforward networks.

A high-speed analog VLSI image acquisition and preprocessing system has been designed and fabricated in a 0.35 m standard CMOS process. The chip features a massively parallel architecture enabling the computation of programmable low-level image processing in each pixel. Extraction of spatial gradients and convolutions such as Sobel or Laplacian filters are implemented on the circuit. For this purpose, each 35 m 35 m pixel includes a photodiode, an amplifier, two storage capacitors, and an analog arithmetic unit based on a four-quadrant multiplier architecture. The retina provides address-event coded output on three asynchronous buses: one output dedicated to the gradient and the other two to the pixel values.

The first two main rounds of neural computing focused on adaptation and selforganization in neural networks, and on use of analog VLSI for compartmental modeling of the neuron, respectively. This paper is a prospectus for a third round of neural computing: analyzing the architecture of the primate brain to extract neural information processing principles and translate them into biologically-inspired operating systems and computer architectures. The way in which the cerebellum interacts with other brain regions in learning how to better control and coordinate movements provides a case study to introduce key ideas for these three rounds of neural computation. It is argued that the third round will develop and exploit general insights into brain architectures, their function and dynamics, that will provide a principled combination of cooperative computation, learning and perceptual robotics (i.e., the integration of action, perception and computation). This new effort is motivated by recent advances in computational neuroscience research, studying examples of system evolution ranging from low-level vision to how the interactions between frontal and parietal cortices serve action recognition (the mirror system), and language. The paper also notes the vast difference between the slow biological evolution of diverse brains and the needs of computer technology for explicit tools for the design and testing of novel programs and architectures, and suggests the challenges of developing a reflection methodology for wrapping modules with descriptions that can be automatically updated as the module itself adapts through learning. The Appendix provides a road map for approaching the voluminous literature on brain theory and neural networks.

We describe and demonstrate a neuromorphic, analog VLSI chip (termed F-LANN) hosting 128 integrate-and-fire (IF) neurons with spike-frequency adaptation, and 16,384 plastic bistable synapses implementing a self-regulated form of Hebbian, spike-driven, stochastic plasticity. The chip is designed to offer a high degree of reconfigurability: each synapse may be individually configured at any time to be either excitatory or inhibitory and to receive either recurrent input from an on-chip neuron or AER-based input from an off-chip neuron. The initial state of each synapse can be set as potentiated or depressed, and the state of each synapse can be read and stored on a computer.

Abstmct-A wide-band, fast settling CMOS complementary folded ascode (CFC) transconductance amplifier for use in analog VLSI high frequency signal processing applications is introduced. The superior performance of the CFC architecture over that of the folder ascode (FC) or mirrored cascode (MC) approaches for VLSI ampliers is demonstrated. The symmetrically configured complementary input stage provides a wide common-mode input voltage range. The amplifier performs as an operational transconductance amplifier (OTA) and displays a first-order dominant pole when loaded by a shunt capacitor. The transconductance amplifier is small in area (0.016 mm'), and well suited for high frequency analog signal processing applications. Simulation and experimental results demonstrate a dc gain of approximately 50 dB, witth a 0.1% settling response of under 10 ns for loads varied from 0 to 2 pF.

In this paper we present an analog circuit that determines the direction of incoming sound using two microphones. The circuit is inspired by biology and uses two silicon cochlea to determine the azimuthal angle of the sound source with respect to the axis of the two microphones using the time difference between the two microphone signals. A new algorithm, adapted to an analog VLSI implementation, is presented together with simulation and measurement results.

In this paper we present an analog circuit that determines the direction of incoming sound using two microphones. The circuit is inspired by biology and uses two silicon cochlea to determine the azimuthal angle of the sound source with respect to the axis of the two microphones using the time difference between the two microphone signals. A new algorithm, adapted to an analog VLSI implementation, is presented together with simulation and measurement results.

This chapter describes an analog VLSI implementation of a multilayer perceptron neural network with on-chip back propagation learning. Local adaptation of the learning rate offers fast convergence. Experimental results from a chip fabricated in the ATMEL ES2 ECPDO7 O.7f.J.m CMOS process demonstrate learning of a 2-input exclusive-or task in 32 ms. J Bar: L..k=l k k,J J ,

We summarize the implementation of an analog VLSI chip hosting a network of 32 integrate-and-fire (IF) neurons with spike-frequency adaptation and 2,048 Hebbian plastic bistable spike-driven stochastic synapse s endowed with a self- regulating mechanism which stops unnecessary synaptic changes. The synaptic matrix can be flexibly configured and provides both recurrent and AER-based con- nectivity with external, AER compliant devices. We demonstrate the ability of the network to efficiently classify overlapping patterns, than ks to the self-regulating mechanism.

We describe an analog VLSI circuit implementing spike-driven synaptic plasticity, embedded in a network of integrate-and-fire neurons. This biologically inspired synapse is highly effective in learning to classify complex stimuli in semisupervised fashion. The circuits presented are designed in subthreshold CMOS consuming extremely low power. The pulsebased neural network communicates with the outside world using the Address Event Representation in an asynchronous fashion. We present measurements from a test chip, characterizing all the modules of the circuit and show how they match well with theoretical expectations. We finally demonstrate that the learning mechanism of the synapse is fully functional by stimulating it with Poisson distributed spike trains.

We study a range of neural dynamics under variations in biophysical parameters underlying extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The extended models are implemented in NeuroDyn, a four neuron, twelve synapse continuous-time analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. The dynamics exhibit a wide range of time scales extending beyond 100 ms neglected in typical silicon models of tonic spiking neurons. Circuit simulations and measurements show transition from tonic spiking to tonic bursting dynamics through variation of a single conductance parameter governing calcium recovery. We similarly demonstrate transition from graded to all-or-none neural excitability in the onset of spiking dynamics through the variation of channel kinetic parameters governing the speed of potassium activation. Other combinations of variations in conductance and channel kinetic parameters give rise to phasic spiking and spike frequency adaptation dynamics. The NeuroDyn chip consumes 1.29 mW and occupies 3 mm 3 mm in 0.5 m CMOS, supporting emerging developments in neuromorphic silicon-neuron interfaces.

We describe and demonstrate a neuromorphic, analog VLSI chip (termed F-LANN) hosting 128 integrate-andfire (IF) neurons with spike-frequency adaptation, and 16,384 plastic bistable synapses implementing a self-regulated form of Hebbian, spike-driven, stochastic plasticity. The chip is designed to offer a high degree of reconfigurability: each synapse may be individually configured at any time to be either excitatory or inhibitory and to receive either recurrent input from an on-chip neuron or AER-based input from an off-chip neuron. The initial state of each synapse can be set as potentiated or depressed, and the state of each synapse can be read and stored on a computer.

A vision sensor for low-cost, fast, and robust vision systems is described. The sensor includes an on-chip analog computation of contrast magnitude and direction of image features. A temporal ordering of this information according to the contrast magnitude is used to reduce the amount of data delivered. This sensor, realized in a 0.5-μm two-poly three-metal technology, features a contrast sensitivity of 2%, a contrast direction precision of ±3°, and an illumination dynamic range of 120 dB. Applications with uncontrolled lighting conditions are ideal for this sensor.

We study a range of neural dynamics under variations in biophysical parameters implementing extended Morris-Lecar and Hodgkin-Huxley models in three gating variables. The dynamics are emulated in NeuroDyn, an analog VLSI programmable neural emulation platform with generalized channel kinetics and biophysical membrane dynamics. We present simulation and measurement results and observe consistent agreement over a wide regime of tonic spiking and intrinsic bursting dynamics through the variation of a single conductance parameter governing calcium recovery.

We propose margin propagation as an alternative to probability propagation in forward decoding. In contrast to sumproduct probability propagation, margin propagation only incurs addition and subtraction in the computation and thus leads to reduced complexity of implementation. Simulations indicate that margin based forward decoding is more robust to input noise and parameter mismatch than sumproduct probability decoding, and offers superior decoding performance. We also present an analog VLSI implementation of the margin propagation network independent of MOS device models, and provide experimental results from a prototype fabricated in a ¢ ¤ £¥ § ¦ process.

Using a two-dimension array of MOSFET switches, a robust, high speed object tracking CMOS sensor is presented. The edges of the image scene are extracted by the in-pixel differential comparators and a region (object) of interest, which is selected by the user, is segmented using the switch network. Tracking is performed by automatic reselection of the desired region. The proposed design presents less sensitivity to threshold adjustments compared to the binarization technique. The processing is mainly performed in analog domain, thus reducing dynamic power dissipation and making the chip ideal for low power applications. The sensor has been designed as a 50 Â 50 pixel VLSI CMOS chip in the 0.6 mm technology. Features such as power dissipation, output latency, and operating frequency are reported.

An analog VLSI implementation which mimics the early visual processing stages in insects is described. The system is composed of sixty parallel channels of integrated photodetectors and processing elements. It serves as the front end processor for a motion detection chip. The pliotodetection circuitry includes p-well junction diodes on a 2pm CMOS process and a logarithmic coinpression to increase the dynamic range of the system. The processing elements consist of an analog differentiator behind each photodetector. The differentiators are low frequency and have been designed using subthreshold design methods.

Novel on-chip algorithms are proposed for face analysis on pictures obtained from a multi-camera surveillance system. According to the objective of the face detection sub-system, spatial positional relations to be presented for which the methodology we used is detailed in the paper. The uniqueness of the approach is the methodology we applied provides superior performance (50 fps) on standard database compared to most of the known face detection systems. In the general model based face part identification schema we relied on, the heavy use of morphologic operations gave robust results, even in analog VLSI implementation.

Fused Multiply Add Block is an important module in high-speed math co-processors and crypto processors. The main contribution of this paper is to reduce the latency. The vital components of Fused Multiply Add (FMA) unit with multi-mode operations are Alignment Shifter, Normalization shifter, Multiplier, Dual Adder by Carry Look Ahead Adder. The major technical challenges in existing FMA architectures are latency and higher precision. In order to reduce the latency, the Multiplier is designed by using reduced complexity Wallace Multiplier and the latency of overall architecture gets reduced up to 15-25 %. In this paper, the total delay of multiplier designed using reduced complexity Wallace Multiplier is found to be 37.673 ns. In order to get higher precision, we design explicitly Alignment Shifter and Normalization Shifter in the FMA unit by using Barrel Shifter as this Alignment Shifter and Normalization Shifter will have less precision, but since replacement of these blocks by Barrel Shifter will result into higher precision and the latency is further reduced by 25-35 % and the total delay of Alignment Shifter and Normalization Shifter using Barrel Shifter is found to be 5.845 ns.

An analog continuous-time neural network with on-chip learning is presented. The 4-3-2 feed-forward network with a modified back-propagation learning scheme was build using micropower building blocks in a double poly, double metal 2/z CMOS process. The weights are stored in non-volatile UV-light programmable analog floating gate memories. A differential signal representation is used to design simple building blocks which may be utilized to build very large neural networks. Measured results from on-chip learning are shown and an example of generalization is demonstrated. The use of micro-power building blocks allows very large networks to be implemented without significant power consumption.

Recurrent networks that perform a winner-take-all computation have been studied extensively. Although some of these studies include spik- ing networks, they consider only analog input rates. We present results of this winner-take-all computation on a network of integrate-and-fire neurons which receives spike trains as inputs. We show how we can con- figure the connectivity in the network so that the winner is selected after a pre-determined number of input spikes. We discuss spiking inputs with both regular frequencies and Poisson-distributed rates. The robustness of the computation was tested by implementing the winner-take-all network on an analog VLSI array of 64 integrate-and-fire neurons which have an innate variance in their operating parameters.

We have implemented a four-tap adaptive lter in a continuous-time analog VLSI circuit. Since an ideal delay is impossible to implement in continuous-time hardware, we implemented the delay line as a cascade of low-pass lters (called the gamma lter). Since many years of research in our lab has shown that the gamma lter outperforms the ideal delay line for a wide range of applications, the gamma lter should not be considered merely a crude approximation of the ideal delay line. We show measured results from an analog chip that solves the problem of system identi cation{identifying an unknown linear circuit from its input/output relationship. Furthermore, we believe that a cascade of all-pass lters (called the Laguerre lter) may potentially outperform the gamma. We have built an adaptive Laguerre lter and show that its measured convergence rate is superior to that of the gamma. Finally, rather than perform gradient descent on a multimodal error function to determine a single optimal time constant, we propose multi-scale realizations of these delay line structures.

We review a series of implementations of electronic devices aiming at imitating to some extent structure and function of simple neural systems, with particular emphasis on communication issues. We first provide a short overview of general features of such "neuromorphic" devices and the implications of setting up "tests" for them. We then review the developments directly related to our work at the Istituto Superiore di Sanità (ISS): a pilot electronic neural network implementing a simple classifier, autonomously developing internal representations of incoming stimuli; an output network, collecting information from the previous classifier and extracting the relevant part to be forwarded to the observer; an analog, VLSI (very large scale integration) neural chip implementing a recurrent network of spiking neurons and plastic synapses, and the test setup for it; a board designed to interface the standard PCI (peripheral component interconnect) bus of a PC with a spec...

Wave-front distortion compensation using direct system performance metric optimization is studied both theo-retically and experimentally. It is shown how different requirements for wave-front control can be incorpo-rated, and how information from different wave-front sensor types can be fused, within a generalized gradient descent optimization paradigm. In our experiments a very-large-scale integration (VLSI) system implement-ing a simultaneous perturbation stochastic approximation optimization algorithm was applied for real-time adaptive control of multielement wave-front correctors. The custom-chip controller is used in two adaptive laser beam focusing systems, one with a 127-element liquid-crystal phase modulator and the other with beam steering and 37-control channel micromachined deformable mirrors. The submillisecond response time of the micromachined deformable mirror and the parallel nature of the analog VLSI control architecture provide for high-speed adaptive compensation ...

We present the architecture and VLSI circuit implementation of a BiCMOS potentiostat bank for monitoring neurotransmitter concentration on a screen-printed carbon electrode array. The potentiostat performs simultaneous acquisition of bidirectional reduction-oxidation currents proportional to neurotransmitter concentration on 16 independent channels at controlled redox potentials. Programmable current gain control yields over 100-dB cross-scale dynamic range with 46-pA input-referred rms noise over 12-kHz bandwidth. The cutoff frequency of a second-order log-domain anti-aliasing filter ranges from 50 Hz to 400 kHz. Track-and-hold current integration is triggered at the sampling rate between dc and 200 kHz. A 2.25-mm 2.25-mm prototype was fabricated in a 1.2-m VLSI technology and dissipates 12.5 mW. Chronoamperometry dopamine concentration measurements results are given. Other types of neurotransmitters can be selected by adjusting the redox potential on the electrodes and the surface properties of the sensor coating.

We present and characterize an analog VLSI network of 4 spiking neurons and 12 conductance-based synapses, implementing a silicon model of biophysical membrane dynamics and detailed channel kinetics in 384 digitally programmable parameters. Each neuron in the analog VLSI chip (NeuroDyn) implements generalized Hodgkin-Huxley neural dynamics in 3 channel variables, each with 16 parameters defining channel conductance, reversal potential, and voltage-dependence profile of the channel kinetics. Likewise, 12 synaptic channel variables implement a rate-based first-order kinetic model of neurotransmitter and receptor dynamics, accounting for NMDA and non-NMDA type chemical synapses. The biophysical origin of all 384 parameters in 24 channel variables supports direct interpretation of the results of adapting/tuning the parameters in terms of neurobiology. We present experimental results from the chip characterizing single neuron dynamics, single synapse dynamics, and multi-neuron network dynamics showing phase-locking behavior as a function of synaptic coupling strength. Uniform temporal scaling of the dynamics of membrane and gating variables is demonstrated by tuning a single current parameter, yielding variable speed output exceeding real time. The 0.5 m CMOS chip measures 3 mm 3 mm, and consumes 1.29 mW. Index Terms-Neuromorphic engineering, reconfigurable neural and synaptic dynamics, silicon neurons, subthreshold metal-oxide semiconductor (MOS), translinear circuits.

Recurrent networks that perform a winner-take-all computation have been studied extensively. Although some of these studies include spiking networks, they consider only analog input rates. We present results of this winner-take-all computation on a network of integrate-and-fire neurons which receives spike trains as inputs. We show how we can configure the connectivity in the network so that the winner is selected after a pre-determined number of input spikes. We discuss spiking inputs with both regular frequencies and Poisson-distributed rates. The robustness of the computation was tested by implementing the winner-take-all network on an analog VLSI array of 64 integrate-and-fire neurons which have an innate variance in their operating parameters.

Analog VLSI on-chip learning Neural Networks represent a mature technology for a large number of applications involving industrial as well as consumer appliances. This is particularly the case when low power consumption, small size and/or very high speed are required. This approach exploits the computational features of Neural Networks, the implementation efficiency of analog VLSI circuits and the adaptation capabilities of the on-chip learning feedback schema. High-speed video cameras are powerful tools for investigating for instance the biomechanics analysis or the movements of mechanical parts in manufacturing processes. In the past years, the use of CMOS sensors instead of CCDs has enabled the development of high-speed video cameras offering digital outputs, readout flexibility, and lower manufacturing costs. In this paper, we propose a high-speed smart camera based on a CMOS sensor with embedded Analog Neural Network.

Typical analog VLSI architectures for on-chip learning are limited in functionality, and scale poorly under variable problem size. We present a scalable hybrid analog-digital architecture for backpropagation learning in multilayer feedforward neural networks, which integrates the¯exible functionality and programmability of digital control functions with the ef®ciency of analog parallel neural computation. The architecture is fully scalable, both in the parallel analog functions of forward and backward signal propagation through synaptic and neural functional units (SynMod and NeuMod), and in the global and local digital functions controlling recall, learning, initialization, monitoring and built-in test. The architecture includes local provisions for long-term weight storage using refresh, which is transparent to the functional operation both during recall and learning.`R efresh While Learning'' (RWL) provides a means to compensate for the ®nite precision of the quantized analog weights during learning. We include simulation results for a network of 32 6 32 neurons, mapped in parallel onto a MassPar computational engine, which validate the functionality of the architecture on simple character recognition tasks, and demonstrate robust operation of the trained network under 4-bit quantization of the weights owing to the RWL technique.

We present a hybrid VLSI and optical system for real-time adaptive phase distortion compensation. The system operates "model-free", independent of the specifics of the distorting optical medium and the compensation control elements. Our VLSI system implements stochastic parallel perturbative gradient descent/ascent so that we achieve fast optimization of the chosen performance metric to achieve realtime compensation. We include experimental results of the hybrid VLSI-optical system demonstrating successful operation for a laser-beam focusing/defocusing task.