160 questions
1
vote
1
answer
87
views
updating SCTLR_EL1 register not working in bare-matel ARMv8 program on QEMU
I am learning armv8 assembly program for my project. I wrote a simple program which tries to modify value of SCTLR_EL1 register. Unfortunately this code is not working. I am enabling I-cache, but the ...
- 143
0
votes
1
answer
153
views
ARMv8 (aarch64, RPi4) procedure for booting secondary CPUs
From https://github.com/s-matyukevich/raspberry-pi-os/blob/master/docs/lesson01/rpi-os.md I found such a statement:
The Raspberry Pi 3 has four core processors, and after the device is powered on, ...
- 759
0
votes
0
answers
39
views
Free running program captures wrong exception address
I'm using an ARM Cortex-A9 processor ZYNQ 7000. The processor raises an data abort exception if invalid address is accessed. The exception handler captures the data abort address, but if the program ...
- 299
0
votes
0
answers
105
views
Creating FreeRTOS Vector table for Cortex A72
I want to port FreeRTOS to RPi4 (Cortex A72, 64-bit, ARMv8). I use this port (Cortex A72, 64-bit, ARMv8) and this port (Cortex A9, 32-bit, ARMv7) as base.
In the FreeRTOS_asm_vectors.S the Software ...
- 5
0
votes
0
answers
87
views
working with TrustZone environment how can i communicate with the SMC API
i am starting a new project concerning trustZone cortex-A ,and i am having a bit of hard time to understand the technicalities lets say i want to communicate directly with the SMC for some non-secure ,...
0
votes
0
answers
70
views
ARM Cortex-A9 MCR for some CoProcs Causes Undefined Instruction in SYS Mode
We are currently developing firmware for an embedded system which operates a Cortex-A9 processor in bare-metal (no OS). We are using armclang and ARM Development studio, which provides the C library ...
- 561
0
votes
0
answers
130
views
Troubleshooting ARM Cortex-A72 Address Translation: Seeking Clarification on Level 1 vs. Level 2 Translation and Register Analysis
I'm using an ARM Cortex-A72 processor running a custom real-time operating system. I'm trying to understand how address translation is performed, but there are some points I couldn't grasp fully.
I ...
- 952
1
vote
0
answers
46
views
What proceedures should i implement to prevent a Cortex-A55 core reset on a remote target when connecting and disconnecting different GDB sessions?
What procedures should I implement to prevent a device reset on a remote target when connecting and disconnecting different GDB sessions?
Assume I run program A, exit GDB and then load a program B in ...
1
vote
0
answers
103
views
Trouble trying to disable L2 cache on BeagleBone Black
First of all, I'm a total beginner on ARM programming. I want to make some analysis with my L2 cache disabled. I'm running a U-boot environment, bare-metal, on my BeagleBone Black and I'm trying to ...
0
votes
0
answers
159
views
How to use AMP mode for cortex a9 baremetal system?
Im working on a cycloneVsoc board with a cortex a9 duel core HPS.
I found out my load was too heavy for one core. And I researched a lot for duel core solutions. It turns out that there is little ...
- 21
0
votes
0
answers
61
views
Qemu (aarch64) doesn't execute my assembler script properly
I try to create a trivial kernel for aarch64 (cortex-a72).
NB: What for? - Just for fun! It's interesting for me.
loader.s:
.global _reset
_reset:
# Set up stack pointer
LDR X2, =stack_top
...
- 7,789
4
votes
1
answer
1k
views
Relation between OP-TEE and ATF
I am confused with the terms and software packages related to ARM-A profile embedded systems.
Could anyone explain the relation between ATF (Arm Trusted Firmware), OP-TEE, Secure World and TEE (...
- 1,081
0
votes
0
answers
432
views
Cannot compile simple program which uses ARM Neon for Cortex A53
I am trying to cross compile a large project (XNNPACK at this specific commit) for an ARM Cortex A53 based linux system. This project uses ARMs arm_neon.h header and functions. While compiling, I get ...
- 792
-1
votes
1
answer
333
views
Linux kernel issue when booting from U-Boot on Cortex-A15 CPU QEMU
I am trying to run u-boot to boot Linux kernel on qemu vexpress-a15. The U-Boot and Linux kernel are configured to run on TI OMAP5, which has ARM Cortex A-15. So I have done some modification (uart, ...
- 3
0
votes
2
answers
517
views
ARM NEON: why is vector code slower than scalar?
I am working with assembly for ARM NEON, and I came to a sequence of unrolled instructions that has actually double the execution time when compared to an equivalent scalar loop. I am actually working ...
- 1
0
votes
1
answer
455
views
GCC generates SIMD and FP instructions for Cortex-A53 without NEON
I compile my C code with aarch64-none-elf-gcc and I add option -mcpu=cortex-a53+nofp. However it seems that the "+nofp" doesn't work and I still get FP instructions (3d8047e0). Could anyone ...
- 1
0
votes
2
answers
141
views
Cortex-A9 , Arm Compiler 5 (DS built int) , Read CNTFRQ register
I try to read CNTFRQ register with inline assembly code.
I use the following:
Arria V soc evaluation board
Bare-Metal app
Arm Compiler 5 (DS built in)
I encountered two issues:
I tried to use "...
- 103
3
votes
0
answers
211
views
Using stdarg.h in bare metal programming
I'm writing a small bootloader for a qemu virt using cortex a72.
I am able to write some text to the UART contrôler to display some text.
I want to write a light version of printf to have some ...
- 178
0
votes
1
answer
692
views
[ARM Cortex-A]: Permission fault due to code region mapped as read/write
When I try to execute code from a region mapped as read/write (AP[2] == 0), the CPU issues a permission fault (exception class == 0b100001, instruction fault status code == 0b001111). When I change ...
- 119
5
votes
3
answers
15k
views
What is my architecture and what does armv8l exactly means?
Firstly, I searched (a lot) and I'm confused about my Android architecture.
The main ways that I used are:
The uname -m command says that I'm using armv8l.
The dpkg --print-architecture command says ...
- 177
0
votes
1
answer
615
views
STM32MP1 OpenSTLinux - bitbake cross-compilation for custom machine does not generate sdcard.stm32 file
I am trying to deploy the st-image-core image on a custom machine board, following this approach described in the ST wiki. The custom device tree files were generated with the STM32CubeMX tool.
I have ...
- 3
1
vote
0
answers
313
views
Value is wrong first time pointer is dereferenced but correct after that
I have a ZYNQ Ultrascale+ MPSoC Genesys ZU dev board that I'm running my application on. I have an accelerator in the PL that is connected to the PS through a simple AXI DMA. The DMA reads the DDR ...
- 17.1k
0
votes
1
answer
343
views
Can't run simple printf on cortex a55
I'm trying to get started with the RK3568 controller (cortex a55)
I have a project and a makefile
I managed to output the character using registers and flashing the LED.
But if I try to output a ...
0
votes
2
answers
549
views
How to put data in L2 cache with A72 Core?
I have an array of data that looks like this :
uint32_t data[128]; //Could be more than L1D Cache size
In order to do computation on it, I want to put the data as close as possible to my computing ...
- 15
0
votes
1
answer
390
views
configure already deployed yocto build / flashing os with wifi
I got my hands on an already deployed yocto system (yocto 2.6.2 - thud) on a board with a NXP i.MX 6UL Cortex-A7. My only possible access at the moment is via wifi. I have access as root via wifi with ...
- 11
1
vote
0
answers
1k
views
Arm-v8 PMCCNTR_EL0 returns 0 if read several times without unloading the kernel object
I have a cpu that have multiple A72 cores.
I am trying to bench an algorithm and I want to count the number of core cycles that elapsed during the execution of a thread.
I've cross-compiled two kernel ...
- 15
2
votes
1
answer
2k
views
How can I know if an ELF file is for Cortex-A or Cortex-M?
I have a question when doing the binary analysis. For a given ELF file (hello.elf) that has already been identified for the ARM architecture, how can I quickly know if this ELF is for Cortex-A or ...
- 425
0
votes
0
answers
162
views
initialize cpu regs to zero in start of arm trusted firmware code
I am building a ATF bl1 secure-boot, currently in simulation I have an issue that I suspect that is related to accessing uninitialized registers.
I'm trying to understand if there is a code that in ...
- 179
1
vote
1
answer
931
views
ARM Cortex M7 MPU shareablility impact on M7 performance
I am running a system testcase in which QSPI, SRAM, DRAM and device (peripheral) memories MPU regions are kept as shareable in ARM_MPU_RASR. The testcase is doing SRAM-to-SRAM cacheable copy operation....
- 159
0
votes
0
answers
297
views
Linux kernel can't perform relocation for the hardware with ARM Cortex-A78
Linux Kernel Version: 5.1.39 and above
Tool chain:
gcc-linaro-aarch64-linux-gnu-4.9-2014.09_linux (for Linux compilation)
gcc-linaro-aarch64-none-elf-4.9-2014.09_linux. (for Boot code compilation)
...
0
votes
2
answers
1k
views
ARM Cortex-A9 NEON and VFP
I am using ARM Cortex-A9 (zynq7000) and I want to enable the neon SIMD but not to use it for floating points unless specified.
When compiled by arm-none-eabi-gcc with following fpu options (seperately)...
- 3
4
votes
1
answer
2k
views
Return Oriented Programming on ARM (64-bit)
I am studying Rop on ARM (64 bit). So i am testing Rop vulnerability on my ARMv8 Cortex A-72 in order to understand how it works on Arm64.
I wrote a very simple c vulnerable code:
#include <stdio.h&...
- 107
1
vote
0
answers
357
views
How to use Gnu assembler Arm system register encoding with .equ or macro's
I'm using the GNU Assembler (directly), for Arm Cortex-A system register access (CLUSTERCFR_EL1). ThIS register name is not recognized by the Assembler, so I needed to use register encoding as ...
- 19
0
votes
1
answer
65
views
Are there any CPU-state bits indicating being in an exception/interrupt handler in ARM Cortex-A processors?
Are there any CPU-state bits indicating being in an exception/interrupt handler in ARM Cortex-A processors (like e.g. IPSR reister in ARM Cortex-M CPUs)? In other words, can we tell whether the main ...
- 1,081
0
votes
0
answers
471
views
Cyclone V: Cortex A9 dma_alloc_coherent() Internal Error
I am trying to allocate some memory on CycloneV ARM9 in the Linux kernel.
This is the code in the driver
typedef struct tx_dma_buf {
volatile phys_addr_t phys_addr;
volatile unsigned int *...
- 583
0
votes
2
answers
987
views
Floating Precision problem on ARM FPU (Neon-vfvp3) on IMX.6 Sabre lite
Hi I am running a simple program to test out floating point unit on Imx6.sabre_lite
double z = 2.2250738585072014e-308;
double x = 3.0594765554474019e-308;
double ans = x-z;
Now ans comes ...
- 91
1
vote
1
answer
229
views
Cache blocking brings no improvement for image filter on ARM
I'm experimenting with cache blocking. To do that, I implemented 2 convolution based smoothing algorithms. The gaussian kernel I'm using looks like this:
The first algorithm is just the simple double ...
- 559
2
votes
1
answer
1k
views
Why cache misses happen more when more data is prefetched on ARM?
I'm using OProfile to profile the following function on a raspberry pi 3B+. (I'm using gcc version 10.2 on the raspberry (not doing cross-compilation) and the following flags for the compiler: -O1 -...
- 559
0
votes
0
answers
72
views
Virtual to Physical mapping
I am working on a Broadcom BCM2711, Quad-core Cortex-A72 (ARM v8) 64-bit SoC @ 1.5GHz.
I have a question: if i have two virtual/physical addresses like :
virtual: 0x55acd71000 physical: 0x28560000 ...
user13938059
0
votes
2
answers
1k
views
Keyboard problem on Lichee Pi Zero with kernel 5.2+
My question is about Lichee Pi Zero board (based on Allwinner/Sunxi V3s SoC).
Initially I used pre-built Linux image (kernel 4.10.02), it has no built-in Wi-Fi support (for Realtek 8327BS chip), so I ...
- 33
-1
votes
1
answer
64
views
Declaring struct instances as static/local in main() with while(1)
I am working on microntroller RZA1, with KPIT GNUARM 16 toolchain, in e2 studio. I am not an expert on the subject, so I'll try to explain the problem the best that I can. The issue is related to a ...
- 44
1
vote
1
answer
1k
views
Declare an array so that the address is aligned on 16 byte boundaries
I have an uint8 array and I need to pass the pointer of this array to a DMA, which transfers 16 bytes at once. So, the requirement is that the array address is 16 byte aligned, like 32'hxxxxxx00 - the ...
- 880
3
votes
1
answer
847
views
Zynq 7000: Minimum asm code to init cpu1 from cpu0
I'm trying to figure out the minimum requirements to initialize cpu1 from cpu0 in an amp configuration on a zynq-7000.
I have a given FSBL that hands over to u-boot with which I copy both programs (...
- 744
0
votes
0
answers
691
views
How to correct stack location arm-none-eabi-gcc?
I try to create a bare metal code using the standard lib C.
I started with an assembly code
.section .isr_vector
.global _Reset
_Reset:
B Reset_Handler /* Reset */
B . /* ...
5
votes
2
answers
3k
views
Reading Armv8-A registers with devmem from GNU/Linux shell
I want to read the values of some Cortex-A53 registers, such as
D_AA64ISAR0_EL1 (AArch64)
ID_ISAR5 (Aarch32)
ID_ISAR5_EL1 (Aarch64)
Unfortunately, I lack a little embedded/assembly experience. The ...
- 948
2
votes
0
answers
436
views
Any NEON instructions can be dual issued with vector long multiply accumulate (SMLAL) on Cortex A53 or A55?
I already asked on the ARM developer forums, but no answers. https://community.arm.com/developer/tools-software/hpc/f/hpc-user-group/45524/any-neon-instructions-can-be-dual-issued-with-vector-long-...
- 1,568
1
vote
0
answers
283
views
Can gated recurrent units be deployed on ARM cortex a53?
I have a task of performing regression learning on a target board (ARM Cortex A53 processor).
I have completed the tasks of data and feature extraction.
Now, i am analyzing the performances of ...
1
vote
0
answers
1k
views
Running Big endian process on little endian cortex A
Suppose i am running on Cortex-A53(ARMv8) on Ubuntu.
Cortex-A53 is using little little-endian architecture, is it possible to compile a program as a big-endian and run it on the little-endian system?
...
- 89
1
vote
0
answers
680
views
Issue in loading bss and data to memory
I have a very simple project compiled for cortex-A53 with arm-compiler-6 (armclang).
This project contains a main.c, a scatter file and a startup.s.
This is its scatter file:
LOAD 0x00000000
{
ROM +...
- 67
2
votes
0
answers
401
views
How to debug TF-A on ARM Cortex-A7
I'm trying a custom image for ARM STM32MP151A on a custom board. On power up nothing happens on the tty port (while using a wrong sd-card leads to a PANIC PC error - hence the port is ok). As far as I ...
- 4,986