304 questions
0
votes
0
answers
12
views
How to Calculate EMAT for a System with 30% L1-D Hit Rate and 98% L2 Hit Rate?
I’m trying to calculate the Effective Memory Access Time (EMAT) for a system described in the following problem:
Problem Setup
The system uses Intel Ice Lake Client micro-architecture with multiple ...
- 111
0
votes
0
answers
24
views
How to Calculate Effective Memory Access Time with Multi-Level TLBs?
I’m working on a problem involving the calculation of effective memory-access time (EMAT) for a system with multi-level TLBs, and I want to confirm if my understanding is correct. Here’s the problem ...
- 111
0
votes
1
answer
29
views
Cannot read type library file: '..\..\AuthAPI\Build\AuthAPIv24.tlb': Error loading type library/DLL
I'm using Visual Studio 2019. The line of code:
#import "..\..\AuthAPI\Build\AuthAPIv24.tlb" named_guids raw_interfaces_only
The error:
Error C1084 Cannot read type library file: '....\...
0
votes
0
answers
16
views
Are TLB and Cache Accesses Always Done in Series?
Since programs use virtual addresses and the cache operates on only physical addresses, does the a TLB(and potential page table access) have to happen before accessing the physical cache? If not, how ...
- 159
1
vote
1
answer
36
views
How can fragmented physical memory cause TLB thrashing?
I read this passage on https://en.wikipedia.org/wiki/Fragmentation_(computing) : "However, if the working set is fragmented, then it will not fit into 64 pages, and execution will slow due to ...
- 87
2
votes
0
answers
121
views
Determine TLB size on ARM64 (Linux)
For Intel there's cpuid command that can report TLB levels, sizes, associativity, etc. Is there a way to do the same on ARM64?
- 759
0
votes
1
answer
130
views
AT (Address Translation) instruction's privilege level in ARMv8
Executing AT instruction (Address Translation) from user-space (a.k.a EL0) gives SIGILL, so I tried executing it from kernel-space (EL1), this way it didn't fail.
I also found that AT is alias for SYS ...
- 759
0
votes
0
answers
59
views
TLB flush during context switch
I am investigating the effects of context switch on linux x86 machines. In particular, I am interested in TLB.
My understanding, after reading Intel Manual 3A (section 4.10.4 "Invalidation of ...
- 33
0
votes
0
answers
87
views
Does malloc consider TLB hits?
I recently tried to examine how malloc() and free() populate the address space with differently sized chunks of memory on my system. It is a debian linux with the glibc malloc implementation and 4 GB ...
- 146
0
votes
0
answers
48
views
os161: TLB miss for getpidtest
Im trying to test my getpid.c from os161 and it gives this error, i know its because it is trying to access some invalid pointer but it does not make any sense. I tried gdb and i cant really use it ...
0
votes
0
answers
29
views
How to remove the prefix auto added for C# enum when generate tlb
I have a C# dll which are COM visible.
public class Class1
{
public enum enumTest
{
None = 0,
enumA = 1,
enumB = 2,
enumC = 3
}
}
When use oleview.exe to ...
- 552
0
votes
0
answers
114
views
In x86_64 architecture, if I modify a PTE in the page table, when will it be sync to TLB?
I am designing an optimistic concurrency control mechanism to address TLB shootdowns for a specific application. The approach operates on the following principles:
The application manages data at the ...
- 1
0
votes
0
answers
129
views
Troubleshooting ARM Cortex-A72 Address Translation: Seeking Clarification on Level 1 vs. Level 2 Translation and Register Analysis
I'm using an ARM Cortex-A72 processor running a custom real-time operating system. I'm trying to understand how address translation is performed, but there are some points I couldn't grasp fully.
I ...
- 952
1
vote
0
answers
70
views
How does a TLB manage memory translation for addresses that cross page boundaries?
Let's say we have a page size of 4096 Bytes, and we have two contiguous virtual memory pages mapped to discontinuous physical pages, i.e
[x , x + 4096 * 2] - Maps to -> [A, A + 4096], [B, B + 4096]
...
- 345
0
votes
0
answers
126
views
size of TLB entry
Problem
What is the size of a TLB (translation lookaside buffer) entry in bits?
Reference
I use the definition/setup of a translation lookaside buffer from the book
Computer Systems: A Programmer's ...
0
votes
0
answers
22
views
What's the purpose of ref bit in TLB
From Computer Organization and Design, the concept of TLB is designed as the following
https://i.sstatic.net/0p3ZH.png
I understand that the ref bit should be used to indicate if a page has been ...
- 21
0
votes
0
answers
38
views
Why does it take so long for cpu to write memory after it has obtained the physical address?
https://github.com/torvalds/linux/commit/6ce64428d62026a10cb5d80138ff2f90cc21d367:
cpu0 cpu1 cpu2
---- ---- ----
[ ...
- 1
0
votes
0
answers
21
views
Will page table data be saved in the CPU cache? [duplicate]
The page table will be saved in memory and accessed during the page walk process after TLB miss. Will this portion of memory be treated as ordinary data and enter the traditional L1-D/L2/L3 cache?
If ...
- 591
1
vote
1
answer
284
views
Will an x86_64 CPU notice that a page-table entry has changed to not-present while setting the dirty flag in the PTE?
There is a scenario as follows:
The pte a of PAGE A set following field:
BIT(0) present
BIT(1) writable
BIT(M-1,12) page frame
dirty flag is NOT SET
CPU0 CPU1
...
- 51
0
votes
0
answers
85
views
Is L2 TLBs on the critical path for L1 cache accesses?
Considering only dcache and dTLB. Due to the current L1d-cache being VIPT, it is necessary to obtain a physical address before cache hit.
Now, it is sure that the hit judgment of L1d-cache depends on ...
- 591
1
vote
0
answers
215
views
How to set the Linux kernel to use transparent huge pages of 1GB page size?
I am using the 5.14 kernel, and I saw this option （CONFIG_HAVE_ARCH_TRANSPARENT_HUGEPAGE_PUD=y） in the compilation configuration.
Does it mean that I can use 1GB sized transparent huge pages instead ...
- 591
2
votes
0
answers
111
views
Is there any way to keep the dirty bit in x86 page tables coherent without TLB invalidates?
The Intel manual contains this admonishment (sec. 4.8):
A processor may cache information from the paging-structure entries in TLBs and paging-structure caches (see Section 4.10). This fact implies ...
- 560
1
vote
0
answers
140
views
Getting count of TLB misses that resulted in memory access in x86-64
I want to know the number of TLB misses that resulted in memory (DRAM) access. In "Intel(R) Xeon(R) W-2104" system, I can see perf counters like "dtlb_load_misses.miss_causes_a_walk&...
- 422
1
vote
0
answers
42
views
Measuring ITLB_FLUSH on icelake processors
According to the Intel website for performance counters at https://perfmon-events.intel.com/, there are counters specifically for ITLB.ITLB_FLUSH for processors based on the "skylake" ...
- 103
0
votes
0
answers
152
views
when to clear the TLB if using process identifier?
In 'Computer Organization and Design' RISC-V version ebook by Patterson and Hennessy p850, it says:
A common alternative is to extend the virtual address space by
adding a process identifier or task ...
- 527
1
vote
0
answers
91
views
What happens on a TLB miss? Is pipelined stalled? Exception raised?
Since a TLB miss means we have to traverse the page table, does TLB miss mean we need to stall the instruction pipeline?
0
votes
0
answers
50
views
Do hugepages guarantee a single tlb entry in the kernel driver when allocated with alloc_pages(GFP_KERNEL | __GFP_COMP)?
On a 5.19 linux kernel with transparent hugepages enabled (/sys/kernel/mm/transparent_hugepage/enabled set to "always"), I am using the following code to allocate a hugepage in a kernel ...
- 197
0
votes
1
answer
204
views
What happens to the TLB during a segmentation fault?
If the TLB is responsible for caching virtual and physical addresses, then what happens to it when a process tries to access an address space that doesn't belong to it? Can the TLB also handle empty ...
1
vote
0
answers
231
views
What happens after TLB miss in x86?
I am currently studying how the Page Miss Handler(PMH)/Page-structure cache works after a TLB/STLB miss, and I noticed that my measurements using the perf tool counters produced unexpected results. I ...
- 63
1
vote
1
answer
712
views
GPU (Nvidia) TLB misses
There are plenty of documentation/publications on CUDA/Nvidia GPUs, but I never encountered anything about TLBs.
Do GPUs use TLBs similar to CPUs (and, therefore, have TLB hits/misses)?
How are TLB ...
- 4,745
1
vote
1
answer
415
views
How do I get 4 MB huge pages on Linux
According to:
$ ls -l /sys/kernel/mm/hugepages
drwxr-xr-x 2 root root 0 Dec 6 10:38 hugepages-1048576kB
drwxr-xr-x 2 root root 0 Dec 6 10:38 hugepages-2048kB
There is a choice of 2 MB and 1 GB ...
- 11
1
vote
0
answers
41
views
is there any diffs hugepaged/nohuge ram map to cpu cache?
my server cpu info :
Model name: Intel(R) Xeon(R) CPU E5-2667 v3 @ 3.20GHz
Stepping: 2
CPU MHz: 3200.000
CPU max MHz: 3200.0000
CPU min MHz: ...
- 21
3
votes
1
answer
184
views
Page-Structure Cache perf events
I've been always thinking that if linear address translation process encounters TLB miss then it traverses page directory structure in memory. However Intel Manual Vol.3/4.10.3 defines the so called ...
- 9,465
1
vote
1
answer
807
views
What may occur if the OS doesn't flush a TLB entry when a process does a free()?
What may occur if the OS doesn't flush a TLB entry when a process does a free() ?
Can the process see the stale data or can another process might see data that does not belong to it?
Will the memory ...
- 13
3
votes
1
answer
1k
views
How does Linux use values for PCIDs?
I'm trying to understand how Linux uses PCIDs (aka ASIDs) on Intel architecture. While I was investigating the Linux kernel's source code and patches I found such a define with the comment:
/*
* 6 ...
- 759
1
vote
0
answers
461
views
Why is the TLB not saved on context switch?
According to this question the TLB content is not saved in the process control block in Linux, or equivalent in other operating systems. I would like to understand why that is, as saving and loading ...
- 11
-1
votes
1
answer
374
views
two-level paged memory exercise
Good morning everyone!
I'm struggling with an exercise of multilevel memory. Could someone help me in resolving it?
Consider a 2-level paged memory, with a size of 256MB, addressed to the byte and ...
- 1
0
votes
0
answers
207
views
Mapping virtual pages from different page directories to the same physical page
I'm working on a kernel for i386 and want to do the following:
Write data to a virtual 4MB page in the current page directory ("current" as in it's loaded to cr3).
Make a separate page ...
- 981
3
votes
1
answer
526
views
Sharing a TLB entry between two logical CPUs (Intel)
I wondered if it is possible if two threads belonging to the same program with the same PCID can share the TLB entry when they are scheduled to run on the same physical CPU?
I already looked into the ...
3
votes
1
answer
2k
views
How does the Dirty and Access bits affect the TLB?
I get it that if a page has been accessed it'll have the Access bit set, and if has been written to, the Dirty bit will also be set. But it's unclear to me how these bits affect the TLB/TLB caching? ...
user16469617
0
votes
1
answer
376
views
How is the LRU eviction policy less efficient than the random policy in this corner case?
I am reading OS Design: Three Easy Pieces, and I stumbled upon this quote in chapter 19: Translation Lookaside Buffers. It talks about eviction policies and comparing the hit efficiency of LRU vs. a ...
- 31
2
votes
0
answers
467
views
How does a CPU tell if a virtual address is pointing to a huge page? [duplicate]
I'm reading about huge pages in Linux, where the idea is using, say, 2MiB page size instead of 4KiB page size, to reduce TLB misses. I understand that modern CPUs have both data and instruction TLBs, ...
- 9,435
5
votes
2
answers
4k
views
.NET Core / .NET 6: Creating a TLB or DLL that can be added as reference in VBA
I am trying to do basically what it says in the title: I have created a class library (dll) using .NET 6.0 and I would like to add that as a reference in an Excel/Access VBA document. I diligently ...
- 51
4
votes
0
answers
654
views
How to achieve high TLB miss?
I'm trying to write a piece of code that achieves a very high TLB miss rate (over 95%). I have come up with the following C code that could reach around 30% d-TLB misses.
I use 4096 bytes page size on ...
- 1,242
1
vote
0
answers
90
views
How to get `dtlb_load_misses.miss_causes_a_walk` performance counter on a virtual machine?
I'm trying to get some TLB performance counters in a virtual machine (ESXi machine) using perf command but it always returns zero. I noted that the virtualize performance counters is disabled on the ...
- 1,242
2
votes
1
answer
580
views
What is the TL-B scheme in ton-solidity and how to use it?
This question is about ton-solidity language of Everscale blockchain smart contracts.
Sometimes, I see the code relative to TL-B scheme. For example, like this:
function getInvokeMessage(address ...
- 492
1
vote
1
answer
880
views
How does TLB differentiate between entries of different Page tables?
Since different processes have their own Page table, How does the TLB cache differentiate between two page tables?
Or is the TLB flushed every time a different process gets CPU?
2
votes
1
answer
329
views
TLB Cache Invalidation when EPT Violation occurs?
I'm currently developing a hypervisor feature.
I'm confused about what to do with TLB Invalidation when EPT Violation occurs
I'm developing on Linux, using an i7 CPU. My implementation:
VPID and EPT ...
- 21
1
vote
0
answers
2k
views
Creating a COM component in .NET 5 and exporting a TLB
I'm trying to create a simple COM component in .NET 5. I have gotten this far:
I have created an interface with the right attributes:
[ComVisible(true)]
[Guid("12345678-3e60-4c56-abcd-...
- 57
5
votes
1
answer
717
views
Cache set-sizes that aren't a power of two
I've got a Linux computer with a Ryzen 7 1800X CPU. According to WikiChip it has a L2-DTLB of 1536 entries. So I assumed the associativity to be divisible by 3. I wrote a little program that checks ...
- 3,061