All Questions
11 questions
2
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Why cache misses happen more when more data is prefetched on ARM?
I'm using OProfile to profile the following function on a raspberry pi 3B+. (I'm using gcc version 10.2 on the raspberry (not doing cross-compilation) and the following flags for the compiler: -O1 -...
- 559
1
vote
1
answer
536
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ARM Cortex-A8 L2 cache miss overhead
I am reading ARM Cortex-A8 data sheet, in data sheet ARM stated that an Load data that missed in L2 take at least 28 core cycle to complete, now i could not imagine that during this 28 cycle CPU will ...
2
votes
1
answer
322
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Cortex-A8 out-of-order execution and Spectre
I am reading about ARM Cortex-A8 processor and found that this processor does not support out-of-order execution. However, in https://developer.arm.com/support/arm-security-updates/speculative-...
-3
votes
1
answer
3k
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what are writing policies of L1 and L2 cache in cortex-A53?
The Cortex-A53 processor has one to four cores, each with an L1 memory system and a single shared L2 cache.
- 13
4
votes
2
answers
4k
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How to divide the L2 cache between the cores on a ARM Cortex-A7?
Context and goal
I'd like to run two fully standalone applications on my Olimex A20 Lime platform that run a ARM Cortex-A7. The goal is to dedicate one core to each application. So far so good.
Now ...
- 716
3
votes
1
answer
2k
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Arm cortex a9 memory access
I want to know the sequence an ARM core (Cortex-A series processor) accesses memory? Right from Virtual Address generated by core to memory and Instruction/Data transferred from the memory to the core....
0
votes
1
answer
1k
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Performance of Cortex-A9 Exclusive L2 Cache Setting
Will "Exclusive L2 Cache" in Cortext-A9 improve performance? ARM Cortext-A9 Technical Reference Manual has some explanation about "Exclusive L2 Cache":
8.1.5. Exclusive L2 cache
The Cortex-A9 ...
- 23
1
vote
2
answers
2k
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What is the difference between eviction buffer and merging store buffer on ARM CPU?
I use a Cortex A9 CPU with two L1 caches: One for data and the other for the instructions. Cache policy could be either "write-back" or "write-through".
The Cortex-A9 Technical Reference Manual part "...
- 57
0
votes
1
answer
3k
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SMP boot of ARM Cortex A9 sequence with MMU/cache enabled
I am trying to do SMP boot in U-boot on Dual core ARM Cortex A9 system with MMU/Cache enabled. I needed the sequence of initializations.
How should be the sequence of the following things happen. In ...
- 51
1
vote
2
answers
1k
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Measure cache access time/cycles for the ARM Cortex-A15
So I measured the cycles for accessing the L2 cache of the ARM Cortex-A15.
I did this by allocating one byte and
invalidate the address
read the PMCCNTR register
access the memory location of the ...
- 11
6
votes
2
answers
3k
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L1 cache ports in ARM Cortex processors
I did some reseach, but could not find much information.
I'd like to know how many L1 read and L1 write ports ARM embedded processors have and how wide the ports are. Specifically, I am interested ...
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