Phase Locked Loop Working With Applications
Phase Locked Loop Working With Applications
Phase Locked Loop Working With Applications
LIC
INTRODUCTION
Analog chips may also contain digital logic elements to replace some analog
reason, and since logic is commonly implemented using CMOS technology, these
chips typically use BiCMOS (BiCMOS technology combines Bipolar and CMOS
processing", and allows a designer to incorporate more functions into a single chip.
Some of the benefits of this mixed technology include load protection, reduced
Purely analog chips in information processing have been mostly replaced with
digital chips. Analog chips are still required for wide-band signals, high-power
analog chips are the 741 operational amplifier, and the 555 timer IC.
The phase-locked loop is one of the basic blocks in modern electronic systems. It is
generally used in multimedia, communication and in many other applications.
There are two different types of PLL’s – linear and nonlinear. The nonlinear is
difficult and complicated to design in the real world, but the linear control theory is
well modeled in analog PLL’s. The PLL has proved that a linear model is
sufficient for most of the electronic applications.
What is a phase-locked loop (PLL)?
A phase-locked loop (PLL) is an electronic circuit with a voltage or voltage-driven
oscillator that constantly adjusts to match the frequency of an input signal. PLLs
are used to generate, stabilize, modulate, demodulate, filter or recover a signal
from a "noisy" communications channel where data has been interrupted
A phase-locked loop consists of a phase detector and a voltage controlled
oscillator. The output of the phase detector is the input of the voltage-controlled
oscillator (VCO) and the output of the VCO is connected to one of the inputs of a
phase detector which is shown below in the basic block diagram. When these two
devices are feed to each other the loop forms.
PL
L Block Diagram
The output of the low pass filter, i.e., DC level is passed on to the VCO. The input
signal is directly proportional to the output frequency of the VCO (fo). The input
and output frequencies are compared and adjusted through the feedback loop until
the output frequency is equal to the input frequency. Hence, the PLL works like
free running, capture, and phase lock.
The phase-locked loop detector compares the input frequency and the output
frequency of the VCO to produces a DC voltage which is directly proportional to
the phase distinction of the two frequencies. The analog and digital signals are
used in the phase-locked loop. Most of the monolithic PLL integrated circuits use
an analog phase detector and the majority of phase detectors are from the digital
type. A double balanced mixture circuit is used commonly in analog phase
detectors. Some common phase detectors are given below:
An exclusive OR phase detector is CMOS IC 4070 type. The input and output
frequencies are applied to the EX OR phase detector. To obtain the output high at
least one input should be low and the other conditions of output are low which is
shown in the below truth table. Let us consider the waveform, the input and output
frequencies, i.e. fi and fo have a phase difference of 0 degrees. Then the DC output
voltage of the comparator will be a function of the phase difference between the
two inputs.
fi fo V dc
An edge trigger phase detector is used when the input and output frequencies are in
pulse waveform, which is less than 50% duty cycle. The R-S flip flop is used for
the phase detectors, which is shown in the below figure. To from R-S flip flop, the
two NOR gates are cross-coupled. The output of the phase detector can change its
logic state by triggering the R-S flip flop. The positive edge of the input and output
frequencies can change the output of the phase detector.
Signal recovery. To provide a "clean" signal and remember the frequency in case
of interruptions (e.g., when using pulsed transmissions)
Application of phase-locked loop.
The main goal of a PLL is to synchronize the output oscillator signal with a
reference signal. Even if the two signals have the same frequency, their peaks and
troughs may not occur in the same place. Simply put, they do not reach the same
point on the waveform at the same time.
Known as the phase difference, this is measured as the angle between the signals.
For signals with varying frequencies, the phase difference between them will
always vary, which means that one signal will lag or lead the other by a varying
amount.
A PLL reduces phase errors between output and input frequencies. When the phase
difference between these signals is zero, the system is said to be "locked." And this
locking action depends on the PLL's ability to provide negative feedback -- i.e.,
route the output signal back to the phase detector.
In addition to synchronizing the output and input frequencies, a PLL also helps
establish the input-output phase relationship to generate the appropriate control
voltage. Therefore, it helps achieve both frequency and phase lock in a circuit.
Applications
PLL IC is used in communication systems like satellites, radars, FMs, clock
generators, FM & FSK demodulation, etc.
Synchronization of Data & Tape.
Modems.
Coherent De-modulators.
Decoding of Tone.
Regeneration of Signal.
Frequency Division & Multiplication.
Telemetry Receivers.
Precision Waveform Generator/Voltage
Controlled Oscillator
It is a 14 pin IC, operated from a dual power supply +V (at pin no. 10) and –V (at
pin no. 1).
Pin no 2 & 3 -> Signal input for phase detector.
Pin no 4 ->VCO output is available
Pin no 4 & 5 are shorted externally so that VCO output is applied for phase
detection. In some applications PLL loop is broken and some circuit is to be
connected between pin no 4 and 5.
Pin no 6-> reference dc voltage is available.
Pin no 7 -> demodulated output.If input signal between pin no 2 and 3 is FM signal
then at pin no 7 we get FM demodulation output.
Pin no 8 and 9 -> external R1 and C1 for VCO (determines free running frequency
of VCO)
Internal resistance R2 and external capacitor C2 forms a LPF. The value of internal
resistance R2 is 3.6kΩ.
Features of IC 565:
1) Extreme stability of center frequency typically 200ppm.
2) Wide range of operating voltage ±6V to ±12V.
3) Very high linearity of demodulated output typically 0.2%
4) Centre frequency of VCO is programmable by means of resistor, capacitor or
voltage.
5) TTL compatible square wave output.
6) Highly linear triangular wave output available at pin no.9
7) Loop can be broken between pin no.4 and 5 and external circuit can be added.
8) Frequency adjustable over the range 1:10 with single capacitor.
Design Equations:
This IC operates in three modes like free running, capture, and lock mode
1. Centre Frequency (Free running freq./ output freq./oscillator freq.)
= 0.3/(R1 C1 )
2. Lock range
f L = (8fo)/V f L =8 f o /V
Features
Applications
TV sound systems,
Intercoms
Ultrasonic drivers
Line drivers
Alarms
Phonograph amplifiers
Some other applications of this mainly include AM radio, motor drivers, power
converters, FM radio, servo, etc.
Now when capacitor charging gets to voltage above than 2/3Vcc, then the voltage
of non-inverting end (Threshold PIN 6) becomes higher than the inverting end of
the comparator. This makes Upper comparator output HIGH and RESETs the Flip
flop, output of 555 chip becomes LOW. As soon as the output of 555 get LOW
means Q’=1, then transistor Q1 becomes ON and short the capacitor C1 to the
Ground. So the capacitor C1 starts discharging to the ground through the Discharge
PIN 7 and resistor R2.
ASTABLE MULTIVIBRATOR
Basic As table Multi vibrator Circuit
Assume a 6 volt supply and that transistor, TR1 has just switched “OFF” (cut-off)
and its collector voltage is rising towards Vcc, meanwhile transistor TR2 has just
turned “ON”. Plate “A” of capacitor C1 is also rising towards the +6 volts supply
rail of Vcc as it is connected to the collector of TR1 which is now cut-off.
Since TR1 is in cut-off, it conducts no current so there is no volt drop across load
resistor R1.
The other side of capacitor, C1, plate “B”, is connected to the base terminal of
transistor TR2 and at 0.6v because transistor TR2 is conducting (saturation).
Therefore, capacitor C1 has a potential difference of +5.4 volts across its plates,
(6.0 – 0.6v) from point A to point B.
Since TR2 is fully-on, capacitor C2 starts to charge up through
resistor R2 towards V CC . When the voltage across capacitor C2 rises to more than
0.6v, it biases transistor TR1 into conduction and into saturation.
The instant that transistor, TR1 switches “ON”, plate “A” of the capacitor which
was originally at V CC potential, immediately falls to 0.6 volts. This rapid fall of
voltage on plate “A” causes an equal and instantaneous fall in voltage on plate “B”
therefore plate “B” of C1 is pulled down to -5.4v (a reverse charge) and this
negative voltage swing is applied the base of TR2 turning it hard “OFF”. One
unstable state.
Transistor TR2 is driven into cut-off so capacitor C1 now begins to charge in the
opposite direction via resistor R3 which is also connected to the +6 volts supply
rail, V CC . Thus the base of transistor TR2 is now moving upwards in a positive
direction towards V CC with a time constant equal to the C1 x R3 combination.
However, it never reaches the value of V CC because as soon as it gets to 0.6 volts
positive, transistor TR2 turns fully “ON” into saturation. This action starts the
whole process over again but now with capacitor C2 taking the base of
transistor TR1 to -5.4v while charging up via resistor R2 and entering the second
unstable state.
Then we can see that the circuit alternates between one unstable state in which
transistor TR1 is “OFF” and transistor TR2 is “ON”, and a second unstable in
which TR1 is “ON” and TR2 is “OFF” at a rate determined by the RC values. This
process will repeat itself over and over again as long as the supply voltage is
present.
The amplitude of the output waveform is approximately the same as the supply
voltage, V CC with the time period of each switching state determined by the time
constant of the RC networks connected across the base terminals of the transistors.
As the transistors are switching both “ON” and “OFF”, the output at either
collector will be a square wave with slightly rounded corners because of the
current which charges the capacitors. If the two time constants produced by C2 x
R2 and C1 x R3 in the base circuits are the same, the mark-to-space ratio ( t1/t2 )
will be equal to one-to-one making the output waveform symmetrical in shape. By
varying the capacitors, C1, C2 or the resistors, R2, R3 the mark-to-space ratio and
therefore the frequency can be altered.
1
f=
( t 1 +t 2 ) ln 2
where t 1=C1 R1
t 2=C 2 R2
If C 1=C2 ∧R 1=R2=R❑ so
1
f= HZ
2 R . C . ln 2
Mono stable multi-vibrators have only one stable state that is used to generate a
single output pulse of a specified width either high or low when an external trigger
pulse is applied. This trigger pulse starts a timing cycle, which causes the output to
change its state at the time of start of timing cycle and continues in the second state
which is decided by the time constant of the capacitor C and resistor R until it
returns to its original state. It will continue in this state until another input signal is
received. Mono stable multi-vibrators can produce a much longer rectangular
waveform. When a trigger pulse is applied externally then the leading edge of the
waveform rises with the externally applied trigger. Here, trailing edge depends
upon the RC time constant of the feedback components used. This RC time
constant may be varied with time to produce a series of pulses which have a fixed
time delay to the original triggered pulse.
In the above circuit, the pin1 is connected to the ground and the trigger input is
given to the pin2. In inactive condition of output, this input is kept at +VCC. To
get transition of the output from a stable state to unstable state, a negative going
pulse of narrow width and amplitude of greater than +2/3 VCC is applied to pin2.
The output is taken from pin3 and pin4 is connected to +VCC to avoid accidental
reset. Pin5 is connected to the ground via a 0.01uF capacitor to avoid noise. Pin6
and pin7 are shorted and a resistor is connected between pins 6 and 8. A discharge
capacitor is connected to pin7 while pin8 is connected to VCC.
Firstly, when the circuit is switched ON, transistor Q1 will be in OFF state and
Q2 will be in ON state. This is the stable state. As Q1 is OFF, the collector voltage
will be VCC at point A and hence C1 gets charged. A positive trigger pulse applied
at the base of the transistor Q1 turns the transistor ON. This decreases the collector
voltage, which turns OFF the transistor Q2. The capacitor C1 starts discharging at
this point of time. As the positive voltage from the collector of transistor Q2 gets
applied to transistor Q1, it remains in ON state. This is the quasi-stable state or
Meta-stable state.
The output wave-forms at the collectors of Q1 and Q2 along with the trigger input
given at the base of Q1 are shown bellow
The width of this output pulse depends upon the RC time constant. Hence it
depends on the values of R1C1. The duration of pulse is given by
T=0.69R1C1T=0.69R1C1
ln2 = 0.693
The trigger input given will be of very short duration, just to initiate the action.
This triggers the circuit to change its state from Stable state to Quasi-stable or
Meta-stable or Semi-stable state, in which the circuit remains for a short duration.
There will be one output pulse for one trigger pulse.
Finally we can conclude that, in the mono stable multi vibrator using 555 timer, the
output stays in a low state until it gets a trigger input. This type of operation is used
in push to operate systems. When the input is triggered, then the o/p will go to high
state & comes back to its original state.
1. It needs only one single pulse to start its operation there is no need of extra
The major drawback of using a mono stable multi vibrator is that the time between
the applications of trigger pulse T has to be greater than the RC time constant of
the circuit.
WAVEFORM GENERATOR.
Among the wave-forms that can be generated with an op amps, the most common
are the triangular, the ramp ( saw tooth) and square wave.
LOW-PASS FILTER
A low-pass filter (LPF) is a circuit that only passes signals below its cutoff
frequency while attenuating all signals above it. It is the complement of a high-
pass filter, which only passes signals above its cutoff frequency and attenuates all
signals below it.
Low-pass filters can also be used in conjunction with high-pass filters to form
band-pass, band-stop, and notch filters. A band-pass filter passes a range of
frequencies while attenuating all frequencies outside of the band. A band-stop filter
(also called a band reject filter) does the opposite, attenuating signals within its
stop-band while passing all frequencies outside of it. Notch filters are a type of
band-stop filter that attenuate a very narrow set of frequencies, which can be
created from a combination of low-pass and high-pass filters with cutoff
frequencies very close to each other.
A low-pas filter can be made with an op amp as the active element and resistors
and capacitors as passive components.
Note:Z1=R20, Z2=C6, Z3=R22, Z4=C10, Z5=R23
The low-pass filter has impedance of Z1 -Z5 where Z1, Z3 and Z5 are resistors and
Z2 and Z4 are capacitors. The characteristics of the filter are determined by the
type and value of the impedance used. The input output relationship is represented
by:
Vo Z 2. Z 4. Z 5
=
V ¿ Z 1. Z 3. Z 5+ Z 1. Z 2. Z 5+ Z 1. Z 2. Z 3+ Z 2. Z 3. Z 5 − Z 2. Z 1. Z 4
The relationship assumes that the input impedance of the operational amplifier is
infinite ( the inverting input can be considered to be a virtual ground. By applying
the superposition principle the equation given can be obtained.
1
Vo R 20 ∗ R 22 ∗C 6 ∗C 10
=
( )
V¿ jω 1 1 1
− ω2 + ∗ + + + R 20 ∗ R 23 ∗C 6 ∗C 10
C1 R20 R22 R23
1
F C= the gain of the filter at the frequency f Hz dc is given by:
2 π √ R 2 ∗ R 3 ∗ C1 ∗C 2
R3
Go=−
R1
Figure 1Amplitude and group delay vs. frequency for various filter types
normalized to a 1-rad bandwidth