Experiment No.-9: Objective:-Brief Theory

Institute of Engineering & Science, IPS Academy Indore
Department of Electrical & Electronics Engg.

Linear IC Application (EX-405)
EXPERIMENT No.-9
Objective:- Study of phase locked loop(PLL)
Brief Theory:Phase locked loops are found in many types of radio equipment. They can be used
as modulators, demodulators, oscillators, synthesizers, clock signal recovery
circuits and the list goes on.
Phase refers to the relative phase difference between an input signal and the loops
internal oscillator. Locked means that the oscillators phase maintains a constant
relationship of that of the input signal. This also means the frequencies of the two
signals are the same, otherwise the phase difference would change. Loop comes
from the feedback loop that controls the internal oscillators frequency to remain in
sync with that of the input signal. Thus, a phase locked loop.
Loop Components
The PLL has three basic components, seen in Figure 1 the phase detector, the
loop filter and a voltage-controlled oscillator (VCO). The output from the phase
detector (C in Figure 1) is a signal that contains the frequency and phase difference
between the input signal and VCO output. The loop filter creates the VCO control
voltage based on the difference signal. The VCO changes frequency in response to
the control voltage until the two frequencies are the same.

The VCO is a special type of oscillator that has a frequency controlled by an
applied voltage. The frequency of the VCO without any control signal applied is
called the free-running frequency, f0. Depending on the circuit design, the VCO
may be designed so that f0 occurs with zero dc voltage input and a bipolar control
signal or at some non-zero dc voltage so the circuit can operate from a single
power supply voltage.
The high frequency of the sum product at fA + fB is not suitable as a VCO control
voltage and so must be removed. That is the job of the low-pass loop filter to
remove everything but the phase detectors fA fB product, along with the phase
information. Depending on the design of the phase detector and the nature of the
signals (sine, square, pulse), the loop filter may also need to convert short bursts of
current into a smoothly varying voltage.
PLL Operation
After the PLL is turned on with no input signal, the VCO will oscillate at the freerunning frequency, f0, until an input signal is applied. The phase detector generates
sum and difference products, the loop filter removes the sum product, and the VCO
output frequency begins to change. Assuming the input and VCO frequencies are
not the same, the output of the loop filter (D in Figure 1) will be an increasing or
decreasing voltage depending on which signal has the higher frequency.
This changing voltage causes the VCO to respond very quickly, reducing the
difference between the VCO and input frequencies. Consequently, the loop filters
output voltage is also reduced, making smaller and smaller changes in the VCO
frequency. Within a short time (typically a few milliseconds for RF PLLs) the VCO
frequency is equal to that of the input signal and the loop is locked. Any change
in either the PLL input or VCO frequencies is tracked by a change in the loop filter
output, keeping the two frequencies the same.

This process of adjust and hold is called capture. The minimum and maximum
input frequencies to which the loop can move the VCO as it captures an input
signal is called the capture range as shown in Figure 2. The segments of the
capture range above and below f0 are called the pull-in range. The pull-in ranges
are not necessarily symmetrical.
If the control signal is proportional to the cosine of the phase difference, it will be
zero when the phase difference is 90 (cos 90 = 0). It will be a maximum when
the two signals are in phase (cos 0 = 1) or out of phase (cos 180 = 1). This
defines the range over which the PLL can keep the input and VCO frequencies
locked together. As the input frequency moves farther and farther from f0, the
VCOs free-running frequency, the loops control action will keep the VCO
frequency the same as the input frequency, but with a phase difference that gets
closer to 0 or 180, depending on which direction the input frequency changes.
If the input frequency has moved so far that the phase difference between it and the
VCO frequency is either 0 or 180, any further change will cause the control signal
to move back toward its 90 value and the VCO frequency away from the input
signal. The loop is no longer locked and the input and VCO frequencies are no
longer the same. The range of input frequencies between the value at which the
loop is locked with a phase difference of 0 and 180 is called the loops lock

range. The lock range above and below f0 are called the loops hold ranges. The
lock range is not always centered on f0.
Building A PLL
Set the potentiometer to half-range, about 5 k. Without connecting any input
signal, apply power and use an oscilloscope or frequency counter to measure the
free-running frequency at VCO out. It should be close to f0 = 1.2/4RTCT 1360 Hz.
Set your function generator to output a sine wave at the measured value of f 0. 0.5 to
1 VP-P will be sufficient. Apply the sine wave to the PLLs input. Use a dual-channel
oscilloscope to monitor both the function generator output and the VCO output.
Use the function generator output to trigger the scope. The sine waves on both
channels should be stable (because they are locked in frequency) but will be
somewhat out of phase.
Slowly reduce the generator output frequency until the PLL loses lock seen as
one trace suddenly becoming unstable. That frequency is the lower limit of the
PLLs lock range. Return the generator frequency to f 0 and then increase it until the
PLL loses lock again at the upper limit of the lock range. Total lock range is the
difference between these two frequencies.

Slowly reduce the generator frequency until the PLL suddenly captures the input
signal and locks again both traces will be stable. This frequency, the upper limit
of the PLL capture range, will be somewhat lower than the upper lock range limit.
Change the generator frequency to something below the lower limit of lock range
you measured previously. Slowly increase frequency until the PLL captures the
input signal at the lower limit of capture range. Total capture range is the difference
between these two frequencies.
Capture range depends on the time constant of the loop filter, determined by CF and
a 3.6 k resistor connected inside the IC. The time constant of the filter equals R
C = 3.6 k 10 F = 36 ms. The larger the time constant, the smaller the capture
range because the loop doesnt respond quickly enough.

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Institute of Engineering & Science, IPS Academy Indore

Department of Electrical & Electronics Engg.

Institute of Engineering & Science, IPS Academy Indore

Institute of Engineering & Science, IPS Academy Indore

Institute of Engineering & Science, IPS Academy Indore

Institute of Engineering & Science, IPS Academy Indore

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