Data Sheet: HEF4046B MSI
Data Sheet: HEF4046B MSI
Data Sheet: HEF4046B MSI
DATA SHEET
For a complete data sheet, please also download:
The IC04 LOCMOS HE4000B Logic
Family Specifications HEF, HEC
The IC04 LOCMOS HE4000B Logic
Package Outlines/Information HEF, HEC
HEF4046B
MSI
Phase-locked loop
Product specification
File under Integrated Circuits, IC04
January 1995
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
DESCRIPTION
The HEF4046B is a phase-locked loop circuit that consists
of a linear voltage controlled oscillator (VCO) and two
different phase comparators with a common signal input
amplifier and a common comparator input. A 7 V regulator
(zener) diode is provided for supply voltage regulation if
necessary. For functional description see further on in this
data.
FAMILY DATA
HEF4046BP(N):
HEF4046BD(F):
(SOT38-1)
IDD LIMITS category MSI
(SOT74)
HEF4046BT(D):
January 1995
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
PINNING
1. Phase comparator pulse output
2. Phase comparator 1 output
3. Comparator input
4. VCO output
5. Inhibit input
6. Capacitor C1 connection A
7. Capacitor C1 connection B
8. VSS
9. VCO input
10. Source-follower output
11. Resistor R1 connection
12. Resistor R2 connection
13. Phase comparator 2 output
14. Signal input
FUNCTIONAL DESCRIPTION
VCO part
The VCO requires one external capacitor (C1) and one or
two external resistors (R1 or R1 and R2). Resistor R1 and
capacitor C1 determine the frequency range of the VCO.
Resistor R2 enables the VCO to have a frequency off-set
if required. The high input impedance of the VCO simplifies
the design of low-pass filters; it permits the designer a wide
choice of resistor/capacitor ranges. In order not to load the
low-pass filter, a source-follower output of the VCO input
voltage is provided at pin 10. If this pin (SFOUT) is used, a
load resistor (RSF) should be connected from this pin to
VSS; if unused, this pin should be left open. The VCO
output (pin 4) can either be connected directly to the
comparator input (pin 3) or via a frequency divider. A LOW
level at the inhibit input (pin 5) enables the VCO and the
source follower, while a HIGH level turns off both to
minimize stand-by power consumption.
Phase comparators
The phase-comparator signal input (pin 14) can be
direct-coupled, provided the signal swing is between the
standard HE4000B family input logic levels. The signal
must be capacitively coupled to the self-biasing amplifier
at the signal input in case of smaller swings. Phase
comparator 1 is an EXCLUSIVE-OR network. The signal
and comparator input frequencies must have a 50% duty
January 1995
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
Fig.3
Fig.4 Typical waveforms for phase-locked loop employing phase comparator 1 in locked condition of fo.
January 1995
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
Fig.5 Typical waveforms for phase-locked loop employing phase comparator 2 in locked condition.
January 1995
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
Figure 6 shows the state diagram for phase comparator 2.
Each circle represents a state of the comparator. The
number at the top, inside each circle, represents the state
of the comparator, while the logic state of the signal and
comparator inputs are represented by a 0 for a logic LOW
or a 1 for a logic HIGH, and they are shown in the left and
right bottom of each circle.
January 1995
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
DC CHARACTERISTICS
VSS = 0 V
Tamb (C)
VDD
V
Supply current
40
SYMBOL
+ 25
+ 85
TYP.
MAX.
TYP.
MAX.
20
TYP.
MAX.
300
15
750
Quiescent device
20
20
150
current (note 2)
10
(note 1)
10
ID
IDD
15
40
40
300
80
80
600
Notes
1. Pin 15 open; pin 5 at VDD; pins 3 and 9 at VSS; pin 14 open.
2. Pin 15 open; pin 5 at VDD; pins 3 and 9 at VSS; pin 14 at VDD; input current pin 14 not included.
AC CHARACTERISTICS
VSS = 0 V; Tamb = 25 C; CL = 50 pF; input transition times 20 ns
VDD
V
SYMBOL MIN.
TYP.
MAX.
Phase comparators
Operating supply voltage
Input resistance
at SIGNIN
A.C. coupled input
VDD
15
750
10 RIN
220
15
140
150
mV
sensitivity
10 VIN
150
mV
at SIGNIN
15
200
mV
at self-bias
operating point
peak-to-peak values;
R1 = 10 k; R2 = ;
C1 = 100 pF; independent
of the lock range
5
10 VIL
15
5
HIGH level
10 VIH
15
Input current
at SIGNIN
3,0
4,0
3,5
7,0
11,0
V
7
10 + IIN
30
15
70
10 IIN
18
15
45
January 1995
1,5
SIGNIN at VDD
SIGNIN at VSS
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
VDD
V
SYMBOL MIN.
TYP.
MAX.
VCO
Operating supply
VDD
voltage
Power dissipation
Maximum operating
frequency
15
15
150
10 P
2500
15
9000
0,5
1,0
MHz
10 fmax
1,0
2,0
MHz
15
1,3
2,7
MHz
Temperature/
0,220,30
%/C
frequency
10
0,040,05
%/C
stability
15
0,010,05
%/C
00,22
%/C
10
00,04
%/C
15
Linearity
Duty factor at
VCOOUT
no frequency offset
(fmin = 0);
see also note 1
00,01
%/C
0,50
R1 > 10 k
see Fig.13
10
0,25
R1 > 400 k
and Figs 14
15
0,25
R1 = 1 M
15 and 16
50
50
10
50
106
10 RIN
106
15
106
1,7
VCOIN minus
10
2,0
SFOUT
15
2,1
1,5
10
1,7
VCOIN
VCOIN at VDD;
R1 = 10 k; R2 = ;
C1 = 50 pF
15
Input resistance at
fo = 10 kHz; R1 = 1 M;
R2 = ; VCOIN at 12 VDD;
see also Figs 10 and 11
Source follower
Offset voltage
Linearity
15
1,8
0,3
10
1,0
15
1,3
RSF = 10 k;
VCOIN at 12 VDD
RSF = 50 k;
VCOIN at 12 VDD
RSF > 50 k;
see Fig.13
Zener diode
Zener voltage
VZ
7,3
IZ = 50 A
Dynamic resistance
RZ
25
IZ = 1 mA
Notes
1. Over the recommended component range.
January 1995
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
DESIGN INFORMATION
CHARACTERISTIC
No signal on SIGNIN
always 0 in lock
(positive-going edges)
Locks on harmonics of
centre frequency
yes
no
high
low
Lock frequency
range (2 fL)
the frequency range of the input signal on which the loop will stay locked if it was
initially in lock; 2 fL = full VCO frequency range = fmax fmin
Capture frequency
range (2 fC)
the frequency range of the input signal on which the loop will lock if it was initially
out of lock
depends on low-pass
filter characteristics; fC < fL
fC = fL
January 1995
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
Fig.7
Typical centre frequency as a function of capacitor C1; Tamb = 25 C; VCOIN at 12 VDD; INH at VSS; R2 = .
January 1995
10
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
Fig.8 Typical frequency offset as a function of capacitor C1; Tamb = 25 C; VCOIN at VSS; INH at VSS; R1 = .
January 1995
11
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
January 1995
12
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
January 1995
13
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
f o = -------------2
f o fo
- 100%
lin. = --------------
fo
Figure 13 and the above
formula also apply to
source follower linearity:
substitute VSF OUT for f.
V = 0,3 V at VDD = 5 V
V = 2,5 V at VDD = 10 V
V = 5 V at VDD = 15 V
January 1995
14
Philips Semiconductors
Product specification
HEF4046B
MSI
Phase-locked loop
January 1995
15