UNIT-II

1. Draw the block diagram of 8-bit successive approximation ADC and explain
its operation. Why is this preferred when conversion time is a main factor?

Successive Approximation Converter

The successive approximation Analog to digital converter circuit typically consists of

four sub-circuits:

1. A sample and hold circuit to acquire the input voltage (Vin).

2. An analog voltage comparator that compares V in to the output of the
internal DAC and outputs the result of the comparison to the successive
approximation register (SAR).
3. A successive approximation register subcircuit designed to supply an
approximate digital code of Vin to the internal DAC.
4. An internal reference DAC that supplies the comparator with an analog
voltage equivalent of the digital code output of the SAR for comparison
with Vin.

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Circuit Operation

 The successive approximation register is initialized so that the most significant bit
(MSB) is set to binary bit - 1.
 This code is fed into the DAC which then supplies the analog equivalent of this
digital code (Vref/2) into the comparator circuit for comparison with the sampled
input voltage.
 If this analog voltage exceeds Vin the comparator causes the SAR to reset this bit
and set the next bit to a digital 1.
 If it is lower then the bit is left a 1 and the next bit is set to 1. This binary search
continues until every bit in the SAR has been tested.
 The resulting code is the digital approximation of the sampled input voltage and is
finally output by the ADC at the end of the conversion (EOC).

Successive approximation conversion sequence for typical analog input

Correct Successive approximation

digital register output Vd at Comparator
representation different stages in the output
, conversion

11010100 10000000 1 (initial output)

11000000 1
11100000 0
11010000 1
11011000 0
11010100' 1
11010110 0
11010101 0
11010100

2. Explain the basic principle of operation of 555

timer IC.

555 TIMER

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  The 555 timer is a highly stable device for generating accurate time delay or
oscillation
 A single 555 timer can provide time delay ranging from microseconds to hours
whereas counter timer can have a maximum timing range of days.
Pin diagram

 It is compatible with both TTL and CMOS logic circuits. Because of the wide
range of supply voltage, the 555 timer is versatile (can be used AC as well as
DC) and easy to use in various applications.

 Applications of IC 555
Various applications include

1. oscillator,
2. pulse generator,
3. ramp and square wave generator',
4. mono-shot multivibrator,
5. burglar alarm, traffic light control and
6. voltage monitor etc.
7.
Functional Diagram of IC 555

 Three 5 kΩ internal resistors act as voltage divider, providing bias

voltage of (2/3) V CC to the upper comparator (UC) and (1/3) VCC to
the lower comparator (LC), where V,, is the supply voltage.

 Since these two voltages fix the threshold voltage for each
comparator and these voltages are also determining the timing
interval.

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  It is possible to vary time electronically too, by applying a
modulation voltage to the control voltage input terminal (pin 5).

 In applications where no such modulation is intended, it is

recommended by manufacturers that a capacitor (0.01 pF) be
connected between control voltage terminal (pin 5) and ground to by-
pass noise or ripple from the supply.

Operation of IC 555

1.In the stable state, the output Q of the flip-flop (FF) is HIGH. This makes the output
LOW because of power amplifier which is basically an inverter.

2.If negative going trigger pulse is applied to pin 2 and should have its dc level greater
than the threshold level of the lower comparator (i.e. V CC / 3), now the trigger passes
through (VCC / 3), the output of the lower comparator goes HIGH and sets the FF (Q
= 1, Q = 0).

3.when the threshold voltage at pin 6 passes through (2/3) V CC , the output of the upper
comparator goes HIGH and resets the FF (Q = 0, Q =1).

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4.The reset input (pin 4) is used to reset the FF and the flip flop output Q becomes
HIGH and the output of IC 555 becomes LOW because the output of FF is 1.

3. Mention the basic blocks of PLL and explain each one of them. Explain
how PLL is used as frequency multiplier?

Phase - Locked Loop

Block diagram of PLL

The basic block schematic of the PLL is shown in Fig. 17This feedback system
consists of:
1. Phase detector/comparator

2. A low pass filter

3. An error amplifier

4. A Voltage Controlled Oscillator (VCO).

Operating Principle

 The VCO is a free running multivibrator and operates at a set frequency f o called
free running frequency. This frequency is determined by an external timing
capacitor and an external resistor.

 This frequency can be varied by applying a dc control voltage V C.

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  If an input signal V S of frequency f s is applied to the PLL, the phase detector
compares the phase and frequency of the incoming signal, which is coming from
the output of VCO (fo) and external input (fs).

 If the two signals differ in frequency and/or phase, an error voltage V e (phase
detector output) is generated. The phase detector is basically a multiplier and
produces the sum. ( f s + f o) and difference ( f s- f o) at its output.

 The high frequency- component ( f s + f o ) is removed by the low pass filter and
the difference frequency ( f s- f o) is amplified and then applied as control voltage
VC to VCO.

 This control voltage VC shifts the VCO frequency in a direction to reduce the
frequency difference between f and fo.

 Once above process starts, we say that the signal is in the capture range. The VCO
continues to change frequency till its output frequency is exactly the same as the
input signal frequency.

 Now the circuit is then said to be locked. Once locked, the output frequency f o of
VCO is identical to fs except for a finite phase difference ф.

 This phase difference ф generates a corrective control voltage V C to shift the VCO
frequency from fo to fs, and thereby maintain the lock. Once locked, PLL tracks the
frequency changes of the input signal.

Various stages of PLL

PLL goes through three stages

(i) free running,
(ii) capture and
(iii) locked or tracking.

Free running

It is initial stage, in this stage the PLL is unlocked

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Capture Stage

As capture starts, a small sine wave appears. This is due to the difference frequency
between the VCO and the input signal. The dc component of the beat drives the VCO
towards the lock. Each successive cycle causes the VCO frequency to move closer to the
input signal frequency. The low pass filter controls the capture range. If VCO frequency
is far away, the beat frequency will be too high to pass through the filter and the PLL will
not respond. We say that the signal is out of the capture band.

Locking or Tracking

Once the PLL is locked, the filter no longer restricts the PLL. The VCO can track the
signal well beyond the capture band. Thus tracking range is always larger than the
capture range.

Frequency Multiplication:

 Figure 20 shows the block diagram of a frequency multiplier using PLL. A

divide by N network is inserted between the VCO output and the phase
comparator input.
 The divide by N (÷ N network ) is divide the VCO frequency by N and this
frequency (fo/N) is applied one of the input of comparator.
 The comparator compares the incoming frequencies and produce the
corresponding output. Hence the locking range is (fo/N)
 The output is taken from VCO and that the frequency range is given by

f o  Nf s

 From the above equation, it can be seen that the output frequency (VCO
output) is N times of input frequency.

4. Describe in detail any two methods of digital to analog conversion?

Expansion of DAC is Digital to Analog Converte

1. The input of DAC is n-bit binary and is combined with the reference voltage
VR to give an analog output signal.
2. The output of a DAC can be either a voltage or current.
3. For a voltage output DAC expressed mathematically as

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 
VO  KVFS d1 2 1  d 2 2 2  d 3 2 3  .......  d n 2  n 
where, Vo = output voltage

VFS = full scale output voltage

K= scaling factor usually adjusted to unity

d1 , d 2 , d 3 .....d n  = n-bit binary fractional word with the decimal point located at the left
d1= most significant bit (MSB) with a weight of V FS / 2
dn =least significant bit (LSB) with a weight of V FS / 2n

Types of Circuit for DAC

1. Weighted resistor DAC

2. R-2R ladder
3. Inverted R-2R laddeR
Weighted Resistor DAC

 Figure shows the binary weighted resistor DAC network

 It consist of a summing amplifier with a binary weighted resistor network and n-
electronic switches d„ d2, . . ., dn controlled by binary input word.
 If the binary input to a particular switch is 1, it connects the resistance to the
reference voltage (-VR).
 If the input bit is 0, the switch connects the resistor to the ground.

I O  I1  I 2  I 3  ....  I n

V   V  V   V 
=  R d1   2R d 2   3R d 3  ....   nR d n
 2R  2 R 2 R 2 R

=
VR
R

d1 2 1  d 2 2 2  d 3 2 3  .......  d n 2 n 
The output voltage

VO  I O R f  VR
Rf
R
d 2
1
1
 d 2 2 2  d 3 2 3  .......  d n 2 n 

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 From the above equation, it can be seen that if Rf =R then K=1 and VFS =VR

Advantage of weighted resistor DAC

Simple design procedure

Dis-advantage of weighted resistor DAC

1.Large value of resistor required if we increase the binary word length

2.power dissipation is high

3.Resolution is poor

4.Wide range of resistor required to construct weighted resistor DAC

R-2R Ladder DAC

 Wide range resistors are required in binary weighted resistor type DAC.
 This can be avoided by using R-2R ladder type DAC where only two values
resistors are required
 A better-designed and more commonly-used circuit for digital-to-analog conversion
is known as the R-2R ladder DAC, a 4-bit version of which is shown in Fig.26
 It consists of a network of resistors with only two values, R and 2R. The input SN
to bit N is '1' if it is connected to a voltage VR and '0' if it is grounded.
 Thevenin's Theorem may be applied to prove that the output Vo of an R-2R ladder
DAC with N bits is:

Vo = VR/2N (SN-12N-1 + SN-22N-2+...+S020).

Thus, the output of the R-2R ladder in Figure 27 is Vo = VR/24

(S323+S222+S121+S020) or Vo = VR (S3 / 2 + S2 / 4 + S1 / 8 + S0 / 16) .

 In effect, contribution of each bit to the analog output is proportional to its binary
weight.

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