2.

10 Phase Locked Loop (PLL) Applications:

1. It is useful in communication systems.
2. radars, satellites,
3. Frequency Modulators
4. Frequency divider
5. Pulse width modulation.

2.9 Block Diagram of PLL

A Phase Locked Loop (PLL) mainly consists of the following three blocks −

 Phase Detector
 Active Low Pass Filter
 Voltage Controlled Oscillator (VCO)


The output of a phase detector is applied as an input of active low pass filter. Similarly, the
output of active low pass filter is applied as an input of VCO.

 working of a PLL:
 Phase detector produces a DC voltage, which is proportional to the phase difference
between the input signal having frequency of fin and feedback (output) signal having
frequency of fout.

 A Phase detector is a multiplier and it produces two frequency components at its output
− sum of the frequencies fin and fout and difference of frequencies fin & fout.
 An active low pass filter produces a DC voltage at its output, after eliminating high
frequency component present in the output of the phase detector. It also amplifies the
signal.
 A VCO produces a signal having a certain frequency, when there is no input applied to
it. This frequency can be shifted to either side by applying a DC voltage to it. Therefore,
 the frequency deviation is directly proportional to the DC voltage present at the output
of a low pass filter.
The above operations take place until the VCO frequency equals to the input signal frequency.
Based on the type of application, we can use either the output of active low pass filter or output
of a VCO. PLLs are used in many applications such as FM demodulator, clock generator etc.
PLL operates in one of the following three modes −

 Free running mode

 Capture mode
 Lock mode
Initially, when no input is applied to it, PLL operates in free running mode.
When an input signal having some frequency is applied to PLL, then the output signal
frequency of VCO will start to change. At this stage, the PLL is said to be operating in
the capture mode.
The output signal frequency of VCO will change continuously until it is equal to the input
signal frequency. Now, it is said to be PLL is operating in the lock mode.

UNIT-3

3.1. Define Filter.

Ans: Filter is a frequency selective circuit that allows certain frequency components and
rejects the other.

3.2. Define Pass band and Stop band.

Ans: A pass band is the range of frequencies that can pass through a filter.

A stop band is the range of frequencies that are stopped by the filter and are not transmitted.

3.4. List the limitations/ disadvantages of passive filters.

Ans:

1. Response problems.
2. Large in size.
3. There is no isolation between input and output.
4. The circuit becomes bulky if inductors are used.
5. There is always some loss of signal it can be in the passband.
6. This circuit cannot provide any gain.
3.3 Draw the ideal and practical frequency responses of first order LPF, HPF, BPF, and
BSF.

3.5 Show how active filters overcome the above limitations.

 (Or)
Advantages of Active filters over passive filters.
Ans:

1. ability to provide signal gain,

2. Higher input impedance

3. lower output impedance,

4. no need for buffer amplifiers,

5. less dependency on inductors

6. Most electronic filters are linear.

7. low cost

8. Small size

9. circuit is simple.

3.6. Draw and explain the operation of Low pass filter using op-amp.

Ans: Active Low Pass Filter

If an active filter allows (passes) only low frequency components and rejects (blocks) all other
high frequency components, then it is called as an active low pass filter.

The simplest form of a low pass active filter is to connect an inverting or non-inverting amplifier,
to the basic RC low pass filter circuit.

For a non-inverting amplifier circuit,

 Where:
  AF = the pass band gain of the filter, (1 + R2/R1)
  ƒ = the frequency of the input signal in Hertz, (Hz)
  ƒc = the cut-off frequency in Hertz, (Hz)
the operation of a low pass active filter can be verified from the frequency gain equation.
 1. At very low frequencies, ƒ < ƒc

 2. At the cut-off frequency, ƒ = ƒc

 3. At very high frequencies, ƒ > ƒc

Thus, the Active Low Pass Filter has a constant gain AF from 0Hz to the high frequency cut-off
point, ƒC.
At ƒC the gain is 0.707AF, and
after ƒC it decreases at a constant rate as the frequency increases.

3.6 Draw and explain the operation of high pass filter using op-amp.

Ans:  An Active High Pass Filter attenuates low frequencies and passes high frequency
signals. It consists simply of a passive filter section followed by a non-inverting operational
amplifier.
 Where:
  AF = the Pass band Gain of the filter, (1 + R2/R1 )
  ƒ = the Frequency of the Input Signal in Hertz, (Hz)
  ƒc = the Cut-off Frequency in Hertz, (Hz)

operation of a high pass active filter can be verified from the frequency gain equation above as:
 1. At very low frequencies, ƒ < ƒc

 2. At the cut-off frequency, ƒ = ƒc

 3. At very high frequencies, ƒ > ƒc

the Active High Pass Filter has a gain AF that increases from 0Hz to the low frequency cut-off
point, ƒC , at 20dB/decade as the frequency increases.
At ƒC the gain is 0.707*AF, 
and after ƒC all frequencies are pass band frequencies so the filter has a constant gain AF .
3.6 Draw and explain the operation of band pass filter using op-amp.

Ans: (for equations check the notes)

Active Band Pass Filter can be easily made by cascading together a single Low Pass Filter with
a single High Pass Filter.

The cut-off or corner frequency of the low pass filter (LPF) is higher than the cut-off frequency
of the high pass filter (HPF) and the difference between the frequencies at the -3dB point will
determine the “bandwidth” of the band pass filter

Wide Band Pass Filter

According to the size of bandwidth, it can divide into a wide bandpass filter and a narrow
bandpass filter.

If the Q-factor is less than 10, the filter is known as a wide pass filter.

If the Q-factor is more than 10, the filter is known as a narrow pass filter.

circuit can be done by using an active high pass and an active low pass filter. where the first half
is for active high pass filter and the second half is for active low pass filter.

it is easy to design the circuit for a wide range of bandwidth.

Narrow Band Pass Filter
The band pass filter which has a quality factor greater than ten.

The bandwidth of this filter is narrow.

Therefore, it allows the signal with a small range of frequencies. It has multiple feedback. This
band pass filter uses only one op-amp.

This band pass filter is also known as multiple feedback filter because there are two feedback
paths.

In this band pass filter, the op-amp is used in non-inverting mode.

3.6 Draw and explain the operation of band pass filter using op-amp.

Ans: If an active filter rejects (blocks) a particular band of frequencies, then it is called as
an active band stop filter.
Wide band Reject filter: if Q value is less than 10, it is a wide band reject filter

In general, this frequency band lies between low frequency range and high frequency range. So,
active band stop filter allows (passes) both low and high frequency components.

block diagram of an active band stop filter consists of two blocks in its first stage:
an active low pass filter and an active high pass filter.
The outputs of these two blocks are applied as inputs to the block that is present in the second
stage.
So, the summing amplifier produces an output, which is the amplified version of sum of the
outputs of the active low pass filter and the active high pass filter.
We have to choose the cut-off frequency of low pass filter to be smaller than cut-off frequency
of a high pass filter.
The circuit diagram of an active band stop filter is shown in the following figure −
Narrow band Reject filter: if Q value is more than 10, it is a narrow band reject filter.

It is also called as notch filter. This is used for rejecting a single frequency.

The most common notch filter design is the twin-T notch filter network. In its basic form, the
twin-T, also called a parallel-tee, configuration consists of two RC branches in the form of two
tee sections.

The frequency at which this basic twin-T notch filter design offers maximum attenuation is
called the “notch frequency”, ƒN
3.7 List the disadvantages of active filters.

Ans:

UNIT -4

4.1 Draw the block diagram of 555 timer IC.

Ans:
4.2 Explain the operation of various blocks of a 555 timer IC.

Ans: The functional diagram of 555 Timer contains a voltage divider network, two comparators,
one SR flip-flop, two transistors and an inverter. 

Voltage Divider Network:

 The voltage divider network consists of a three 5KΩ resistors that are connected in series
between the supply voltage Vcc and ground.

 This network provides a voltage of (1/3) Vcc between a point and ground, if there exists
only one 5KΩ resistor.

 Similarly, it provides a voltage of (2/3)Vcc  between a point and ground, if there exists
only two 5KΩresistors.

Comparator
 The 555 Timer IC consists of two comparators:
Upper Comparator (UC) and a Lower Comparator (LC).
 a comparator compares the two inputs that are applied to it and produces an output.
 If the voltage present at the non-inverting terminal of an op-amp is greater than the
voltage present at its inverting terminal, then the output of comparator will be +Vsat
 . This can be considered as Logic High ('1') in digital representation.
 If the voltage present at the non-inverting terminal of op-amp is less than or equal to the
voltage at its inverting terminal, then the output of comparator will be –Vsat.
 This can be considered as Logic Low ('0') in digital representation.

SR Flip-Flop
 It has two inputs: S and R, and two outputs: Q(t) and Q(t)’.
 The outputs, Q(t) & Q(t)’ are complement to each other.

truth table of SR flip flop

  The outputs of Lower Comparator (LC) and Upper Comparator (UC) are applied
as inputs of SR flip-flop.
Transistors and Inverter
 The functional diagram of a 555 Timer IC consists of one npn transistor Q1 and one pnp
transistor Q2.
 The npn transistor Q1 will be turned ON if its base to emitter voltage is positive and
greater than cut-in voltage. Otherwise, it will be turned-OFF.

 The pnp transistor Q2 is used as buffer in order to isolate the reset input from SR flip-
flop and npn transistor Q1.
 The inverter used in the functional diagram of a 555 Timer IC not only performs the
inverting action but also amplifies the power level.

4.3. Draw the pin diagram of 555 IC and mention the function of each pin.

Ans: Pin Diiagram:

Pin 1- Ground:
All the voltages are measured with respect to ground.

Pin 2. Trigger: Trigger pin is taken from the negative input of upper comparator. The upper
comparator output is connected to SET pin of flip-flop. With the upper comparator output high,
we get high voltage at the timer output. So we can say the trigger pin controls timer output.

Pin 3: output
Output is taken from this pin. Load can be connected in two ways.
In one way load is connected between pin 3 and ground, the other way is connecting load
between pin 3 and pin 8.

Pin 4: Reset

It is used to restart the 555's timing operation. Reset is an active low input. So, pin 4 must be
connected to the supply voltage for the 555 timer to operate.
Pin 5: Control Voltage

This pin controls the timing of the 555 timer by overriding the 2/3Vcc level of the voltage
divider network. By applying a voltage to this pin the width of the output signal can be varied
independently of the RC timing network.

Pin 6: Threshold

 It is the Threshold pin. The timing cycle is completed when voltage on this pin is equal to or

greater than two-third of Vcc.

Pin 7: Discharge

This pin is used to discharge an external capacitor that works in conjunction with a resistor
to control the timing interval.

Pin 8: Vcc

This is the positive supply voltage terminal of the IC. The supply voltage range vary between
+5V and +15V. 

4.4 Draw and explain the operation of monostable multivibrator using 555 IC.
Ans: The IC 555 timer can be operated as a Monostable Multivibrator Using IC 555 by
connecting an external resistor and a capacitor 

1
The circuit has only one stable state and one quasi stable state.

When trigger is applied, it produces a pulse at the output and returns back to its stable state. The
duration of the pulse depends on the values of R and C. As it has only one stable state, it is called
one shot multivibrator.

Operation

The flip-flop is initially set i.e. Q is high. This drives the transistor Q d in saturation. The
capacitor discharges completely and voltage across it is nearly zero. the output at pin 3 is low.

When a trigger input, a low going pulse is applied, then circuit state remains unchanged till
trigger voltage is greater than 1/3 Vcc. When it becomes less than 1/3 Vcc, then comparator 2
output goes high. This resets the flip-flop so Q goes low and Q goes high. Low Q makes the
transistor Qd off. Hence capacitor starts charging through resistance R, as shown by dark arrows
in the Fig 1.

The voltage across capacitor increases exponentially. This voltage is nothing but the threshold
voltage at pin 6. When this voltage becomes more than 2/3 V cc , then comparator 1 output goes
high. This sets the flip-flop i.e. Q becomes high and low. This high Q drives the transistor Q d in
saturation. Thus capacitor C quickly discharges through Qd as shown by dotted arrows in the Fig
2.
 Fig 2

So it can be noted that Vout at pin 3 is low at start, when trigger is less than 1/3 V cc it becomes
high and when threshold is greater than 2/3 Vcc again becomes low, till next trigger pulse occurs.
So a rectangular wave is produced at the output. The pulse width of this rectangular pulse is
controlled by the charging time of capacitor. This depends on the time constant RC. Thus RC
controls the pulse width. The waveforms are shown in the Fig 2.

Derivation of Pulse Width:

The voltage across capacitor increases exponentially and is given by

where C in farads, R in ohms, t in seconds.

Thus, we can say that voltage across capacitor will reach 2/3 Vcc in approximately 1.1 times,
time constant i.e. 1.1 RC

Thus the pulse width denoted as W is given by,

W = 1.1 RC

4.5 Draw and explain the operation of astable multivibrator using 555 IC.
Ans: This circuit has no stable state. The circuits changes its state alternately. Hence the
operation is also called free running nonsinusoidal oscillator.

1
Working of Astable Multivibrator using IC 555:

When the flip-flop is set, Q is high which drives the transistor Q d in saturation and the capacitor
gets discharged. Now the capacitor voltage is nothing but the trigger voltage. So while
discharging, when it becomes less than 1/3 VCC, comparator 2 output goes high. This resets the
flip-flop hence Q goes low and Q goes high

The low Q makes the transistor off. Thus capacitor starts charging through the resistances R A,
RB and VCC. The charging path is shown by thick arrows in the Fig.1. As total resistance in the
charging path is (RA + RB), the charging time constant is (RA + RB) C.

Now the capacitor voltage is also a threshold voltage. While charging, capacitor voltage
increases i.e. the threshold voltage increases. When it exceeds 2/3 VCC, then the comparator 1
output goes high which sets the flip-flop. The flip-flop output Q becomes high and output at pin
3 i.e. Q becomes low. High Q drives transistor Qd in saturation and capacitor starts discharging
through resistance RB and transistor Qd. This path is shown by dotted arrows in the Fig. 1, Thus
the discharging time constant is RB C. When capacitor voltage becomes less than 1/3 V CC,
comparator 2 output goes high, resetting the flip-flop. This cycle repeats.

Thus when capacitor is charging, output is high while when it is discharging the output is low.
The output is a rectangular wave. The capacitor voltage is exponentially rising and falling. The
waveforms of Astable Multivibrator Using IC 555 are shown in the Fig. 2.
Duty Cycle of Astable Multivibrator:

It is defined as the ratio of ON time i.e. high output to the total time of one cycle. As shown
in the Fig. 2.

W = time for output is high = TON

T = time of one cycle

D = duty cycle = W/T

% D = W/T x 100%

The charging time for the capacitor is given by,

Tc = Charging time = 0.693 (RA + RB) C

While the discharge time is given by,

Td = Discharging time = 0.693 RB C

Hence the time for one cycle is

T = Tc + Td = 0.693 (RA + RB) C + 0.693 RB C

= 0.693 (RA + 2 RB) C

While
 W = Tc = 0.693 (RA + RB) C

While the frequency of oscillations is given by,

If RA is much smaller than RB, duty cycle approaches to 50% and output waveform approaches to
square wave.

4.6 Mention the applications of 555 IC timers.

Ans:
1. Square wave generation
2. FSK generator
3. Voltage controlled oscillator (VCO)
4. Frequency divider
5. Pulse width modulation
6. Linear ramp generator
7. Pulse position modulation
8. Missing pulse detector
9. Timer in relay