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regulations and safety requirements or standards, regardless of any support or applications information provided by onsemi. “Typical” parameters which may be provided in onsemi data sheets and/
or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application
by customer’s technical experts. onsemi does not convey any license under any of its intellectual property rights nor the rights of others. onsemi products are not designed, intended, or authorized
for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification in a foreign jurisdiction or any devices intended for
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Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. Other names and brands may be claimed as the property of others.
NTMD3N08LR2

Power MOSFET
2.3 Amps, 80 Volts
N−Channel Enhancement−Mode
SO−8 Dual Package
http://onsemi.com
Features
• Ultra Low On−Resistance Provides Higher Efficiency
♦ RDS(on) = 0.215 W, VGS = 10 V
2.3 AMPERES
♦ RDS(on) = 0.245 W, VGS = 5.0 V 80 VOLTS
• Low Reverse Recovery Losses 215 mW @ VGS = 5 V (Typ)
• Internal RG = 50 W
• Designed for Power Management Solutions in 42 V Automotive MARKING DIAGRAM &
System Applications PIN ASSIGNMENT
• IDSS and RDS(on) Specified at Elevated Temperature 8 D1 D1 D2 D2
8
• Avalanche Energy Specified 1
• Miniature SO−8 Surface Mount Package − Saves Board Space 3N08
SOIC−8 AYWW G
• Mounting Information for SO−8 Package Provided CASE 751 G
• Pb−Free Package is Available STYLE 11
1
S1 G1 S2 G2
Applications
• Integrated Starter Alternator 3N08 = Device Code
A = Assembly Location
• Electronic Power Steering Y = Year
• Electronic Fuel Injection WW = Work Week
• Catalytic Converter Heaters G = Pb−Free Package
(Note: Microdot may be in either location)
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating Symbol Value Unit
ORDERING INFORMATION
Drain−to−Source Voltage VDSS 80 V
Drain−to−Source Voltage (RGS = 1.0 mW) VDGR 80 Device Package Shipping†
Gate−to−Source Voltage − Continuous VGS ±15 V NTMD3N08LR2 SO−8 2500/Tape & Reel
Gate−to−Source Voltage −
Non−Repetitive (tp ≤ 10 ms) VGSM ±20 NTMD3N08LR2G SO−8 2500/Tape & Reel
Continuous Drain Current @ TA = 25°C ID 2.3 A (Pb−Free)
Pulsed Drain Current (Note 1) IDM 25
†For information on tape and reel specifications,
Total Power Dissipation @ TA = 25°C (Note 2) PD 3.1 W including part orientation and tape sizes, please
Operating and Storage Temperature Range TJ, Tstg −55 to °C refer to our Tape and Reel Packaging Specification
+175 Brochure, BRD8011/D.

Single Pulse Drain−to−Source Avalanche EAS 25 mJ

Energy − Starting TJ = 25°C
(VDD = 50 Vdc, VGS = 5.0 Vdc, Peak
IL = 7.0 Apk, L = 1.0 mH, RG = 25 W)
Thermal Resistance − RqJA 48 °C/W
Junction−to−Ambient (Note 2)
Maximum Lead Temperature for Soldering TL 260 °C
Purposes for 10 Seconds
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Pulse Test: Pulse Width = 10 ms, Duty Cycle = 2%
2. Mounted onto a 2″ square FR−4 board
(1in sq, oz. Cu 0.06″ thick single sided), t ≤ 5 seconds

© Semiconductor Components Industries, LLC, 2009 1 Publication Order Number:

October, 2009 − Rev. 7 NTMD3N08LR2/D
 NTMD3N08LR2

ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)

Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage V(BR)DSS
(VGS = 0 Vdc, ID = 250 mAdc) 80 − − Vdc
Positive Temperature Coefficient − 99.8 − mV/°C

Zero Gate Voltage Drain Current IDSS mAdc

(VDS = 80 Vdc, VGS = 0 Vdc) − − 2.0
(VDS = 80 Vdc, VGS = 0 Vdc, TJ = 150°C) − − 250
Gate−Body Leakage Current IGSS nAdc
(VGS = 15 Vdc, VDS = 0 Vdc) − − 100
(VGS = −15 Vdc, VDS = 0 Vdc) − − −100

ON CHARACTERISTICS
Gate Threshold Voltage VGS(th)
(VDS = VGS, ID = 250 mAdc) 1.0 1.9 3.0 Vdc
Negative Temperature Coefficient − 4.6 − mV/°C

Static Drain−to−Source On−State Resistance RDS(on) W

(VGS = 5.0 Vdc, ID = 1.0 Adc) − 0.215 0.245
(VGS = 10 Vdc, ID = 2.5 Adc) − 0.190 0.215
(VGS = 4.5 Vdc, ID = 1.0 Adc, TJ @ 150°C) − 0.446 0.505

DYNAMIC CHARACTERISTICS
Input Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss − 218 480 pF
Output Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Coss − 54 150
Reverse Transfer Capacitance (VDS = 25 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Crss − 15 50
SWITCHING CHARACTERISTICS (Notes 3 and 4)
Turn−On Delay Time (VDD = 40 Vdc, ID = 1.0 A, VGS = 4.5 V, RG = 27 W) td(on) − 21 34 ns
Turn−On Delay Time (VDD = 40 Vdc, ID = 2.5 A, VGS = 10 V, RG = 47 W) − 13 −

Rise Time (VDD = 40 Vdc, ID = 1.0 A, VGS = 4.5 V, RG = 27 W) tr − 62 104

Rise Time (VDD = 40 Vdc, ID = 2.5 A, VGS = 10 V, RG = 47 W) − 95 −

Turn−Off Delay Time (VDD = 40 Vdc, ID = 1.0 A, VGS = 4.5 V, RG = 27 W) td(off) − 52 85

Turn−Off Delay Time (VDD = 40 Vdc, ID = 2.5 A, VGS = 10 V, RG = 47 W) − 47 −

Fall Time (VDD = 40 Vdc, ID = 1.0 A, VGS = 4.5 V, RG = 27 W) tf − 48 81

Fall Time (VDD = 40 Vdc, ID = 2.5 A, VGS = 10 V, RG = 47 W) − 104 −

Total Gate Charge (VDS = 40 Vdc, VGS = 5.0 Vdc, ID = 1.0 A) QG(TOT) − 5.1 9.0 nC
Total Gate Charge (VDS = 40 Vdc, VGS = 10 Vdc, ID = 1.0 A) − 8.8 15

Gate−Source Charge (VDS = 40 Vdc, VGS = 5.0 Vdc, ID = 1.0 A) QGS − 0.95 −
Gate−Drain Charge (VDS = 40 Vdc, VGS = 5.0 Vdc, ID = 1.0 A) QGD − 2.75 −
Threshold Gate Charge (VDS = 40 Vdc, VGS = 5.0 Vdc, ID = 1.0 A) QG(TH) − 0.35 −
BODY−DRAIN DIODE RATINGS (Note 3)
Diode Forward On−Voltage VSD Vdc
(IS = 1.0 Adc, VGS = 0 V) − 0.8 1.0
(IS = 1.0 Adc, VGS = 0 V, TJ = 150°C) − 0.6 −
Reverse Recovery Time trr − 47 93 ns
(IS = 1.0 A, dIS/dt = 100 A/ms, VGS = 0 V)
ta − 25 −
tb − 22 −
Reverse Recovery Stored Charge QRR − 0.067 0.134 mC
(IS = 1.0 A, dIS/dt = 100 A/ms, VGS = 0 V)
3. Indicates Pulse Test: Pulse Width = 300 ms max, Duty Cycle = 2%.
4. Switching characteristics are independent of operating junction temperatures.

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 NTMD3N08LR2

TYPICAL ELECTRICAL CHARACTERISTICS

5 6
10 V 4V
9V 5V
ID, DRAIN CURRENT (AMPS)

ID, DRAIN CURRENT (AMPS)

5 VDS ≥ 10 V
4
8V 6V
7V VGS = 3.5 V 4
3
3
2
2 TJ = 25°C

1 TJ = 25°C
1 TJ = 100°C TJ = − 55°C

0 0
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 0 1 2 3 4 5 6
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) VGS, GATE−TO−SOURCE VOLTAGE (VOLTS)

Figure 1. On−Region Characteristics Figure 2. Transfer Characteristics

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

RDS(on), DRAIN−TO−SOURCE RESISTANCE (W)

0.5 0.3
TJ = 25°C
VGS = 5.0 V
0.25
0.4
VGS = 5.0 V
TJ = 100°C
0.2
0.3
VGS = 10 V
TJ = 25°C 0.15
0.2
0.1
TJ = −55°C
0.1
0.05

0 0
0 1 2 3 4 5 0 1 2 3 4 5
ID, DRAIN CURRENT (AMPS) ID, DRAIN CURRENT (AMPS)

Figure 3. On−Resistance versus Figure 4. On−Resistance versus Drain Current

Drain Current and Temperature and Gate Voltage
RDS(on), DRAIN−TO−SOURCE RESISTANCE

2.5 100,000
VGS = 5.0 V VGS = 0 V
ID = 1.5 A
2 10,000
IDSS, LEAKAGE (nA)

TJ = 175°C
(NORMALIZED)

1.5 1000

1 100

0.5 10 TJ = 100°C

0 1
−50 −25 0 25 50 75 100 125 150 175 10 20 30 40 50 60 70 80
TJ, JUNCTION TEMPERATURE (°C) VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 5. On−Resistance Variation with Figure 6. Drain−To−Source Leakage

Temperature Current versus Voltage

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 NTMD3N08LR2

POWER MOSFET SWITCHING

Switching behavior is most easily modeled and predicted The capacitance (Ciss) is read from the capacitance curve at
by recognizing that the power MOSFET is charge a voltage corresponding to the off−state condition when
controlled. The lengths of various switching intervals (Dt) calculating td(on) and is read at a voltage corresponding to
are determined by how fast the FET input capacitance can the on−state when calculating td(off).
be charged by current from the generator. At high switching speeds, parasitic circuit elements
The published capacitance data is difficult to use for complicate the analysis. The inductance of the MOSFET
calculating rise and fall because drain−gate capacitance source lead, inside the package and in the circuit wiring
varies greatly with applied voltage. Accordingly, gate which is common to both the drain and gate current paths,
charge data is used. In most cases, a satisfactory estimate of produces a voltage at the source which reduces the gate drive
average input current (IG(AV)) can be made from a current. The voltage is determined by Ldi/dt, but since di/dt
rudimentary analysis of the drive circuit so that is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
t = Q/IG(AV)
complicates the mathematics. And finally, MOSFETs have
During the rise and fall time interval when switching a finite internal gate resistance which effectively adds to the
resistive load, VGS remains virtually constant at a level resistance of the driving source, but the internal resistance
known as the plateau voltage, VSGP. Therefore, rise and fall is difficult to measure and, consequently, is not specified.
times may be approximated by the following: The resistive switching time variation versus gate
tr = Q2 x RG/(VGG − VGSP) resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
tf = Q2 x RG/VGSP
the parasitics were not present, the slope of the curves would
where maintain a value of unity regardless of the switching speed.
VGG = the gate drive voltage, which varies from zero to VGG The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
RG = the gate drive resistance is believed readily achievable with board mounted
and Q2 and VGSP are read from the gate charge curve. components. Most power electronic loads are inductive; the
During the turn−on and turn−off delay times, gate current is data in the figure is taken with a resistive load, which
not constant. The simplest calculation uses appropriate approximates an optimally snubbed inductive load. Power
values from the capacitance curves in a standard equation MOSFETs may be safely operated into an inductive load;
for voltage change in an RC network. The equations are: however, snubbing reduces switching losses.
td(on) = RG Ciss In [VGG/(VGG − VGSP)]
td(off) = RG Ciss In (VGG/VGSP)

600
VDS = 0 V VGS = 0 V
TJ = 25°C
500 Ciss
C, CAPACITANCE (pF)

400

Crss
300
Ciss
200

100 Coss
Crss
0
−10 −5 0 5 10 15 20 25
VGS VDS

GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE (VOLTS)

Figure 7. Capacitance Variation

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 NTMD3N08LR2

10 1000
VGS, GATE−TO−SOURCE VOLTAGE (V) QT
VDD = 64 V
ID = 2.3 A
8 VGS = 5.0 V
100
tr

t, TIME (ns)
6
td(off)
tf
Q1 Q2 td(on)
4
10

2
ID = 1.0 A
TJ = 25°C
0 1
0 1 2 3 4 5 6 7 8 9 1 10 100
QG, TOTAL GATE CHARGE (nC) RG, GATE RESISTANCE (W)
Figure 8. Gate−To−Source and Drain−To−Source Figure 9. Resistive Switching Time
Voltage versus Total Charge Variation versus Gate Resistance

DRAIN−TO−SOURCE DIODE CHARACTERISTICS

The switching characteristics of a MOSFET body diode high di/dts. The diode’s negative di/dt during ta is directly
are very important in systems using it as a freewheeling or controlled by the device clearing the stored charge.
commutating diode. Of particular interest are the reverse However, the positive di/dt during tb is an uncontrollable
recovery characteristics which play a major role in diode characteristic and is usually the culprit that induces
determining switching losses, radiated noise, EMI and RFI. current ringing. Therefore, when comparing diodes, the
System switching losses are largely due to the nature of ratio of tb/ta serves as a good indicator of recovery
the body diode itself. The body diode is a minority carrier abruptness and thus gives a comparative estimate of
device, therefore it has a finite reverse recovery time, trr, due probable noise generated. A ratio of 1 is considered ideal and
to the storage of minority carrier charge, QRR, as shown in values less than 0.5 are considered snappy.
the typical reverse recovery wave form of Figure 14. It is this Compared to ON Semiconductor standard cell density
stored charge that, when cleared from the diode, passes low voltage MOSFETs, high cell density MOSFET diodes
through a potential and defines an energy loss. Obviously, are faster (shorter trr), have less stored charge and a softer
repeatedly forcing the diode through reverse recovery reverse recovery characteristic. The softness advantage of
further increases switching losses. Therefore, one would the high cell density diode means they can be forced through
like a diode with short trr and low QRR specifications to reverse recovery at a higher di/dt than a standard cell
minimize these losses. MOSFET diode without increasing the current ringing or the
The abruptness of diode reverse recovery effects the noise generated. In addition, power dissipation incurred
amount of radiated noise, voltage spikes, and current from switching the diode will be less due to the shorter
ringing. The mechanisms at work are finite irremovable recovery time and lower switching losses.
circuit parasitic inductances and capacitances acted upon by
2.5

VGS = 0 V
IS, SOURCE CURRENT (AMPS)

2 TJ = 25°C

1.5

0.5

0
0 0.2 0.4 0.6 0.8 1
VSD, SOURCE−TO−DRAIN VOLTAGE (VOLTS)

Figure 10. Diode Forward Voltage versus Current

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 NTMD3N08LR2

SAFE OPERATING AREA

The Forward Biased Safe Operating Area curves define total power averaged over a complete switching cycle must
the maximum simultaneous drain−to−source voltage and not exceed (TJ(MAX) − TC)/(RqJC).
drain current that a transistor can handle safely when it is This power MOSFET can be safely used in switching
forward biased. Curves are based upon maximum peak circuits with unclamped inductive loads. For reliable
junction temperature and a case temperature (TC) of 25°C. operation, the stored energy from circuit inductance
Peak repetitive pulsed power limits are determined by using dissipated in the transistor while in avalanche must be less
the thermal response data in conjunction with the procedures than the rated limit and must be adjusted for operating
discussed in AN569, “Transient Thermal Resistance − conditions differing from those specified. Although industry
General Data and Its Use.” practice is to rate in terms of energy, avalanche energy
Switching between the off−state and the on−state may capability is not a constant. The energy rating decreases
traverse any load line provided neither rated peak current non−linearly with an increase of peak current in avalanche
(IDM) nor rated voltage (VDSS) is exceeded, and that the and peak junction temperature.
transition time (tr, tf) does not exceed 10 ms. In addition the

100 25

EAS, SINGLE PULSE DRAIN−TO−SOURCE

VGS = 20 V
ID = 2.3 A
SINGLE PULSE
ID, DRAIN CURRENT (AMPS)

TC = 25°C 10 ms 20

AVALANCHE ENERGY (mJ)

10
100 ms
15
1 ms
1
10 ms 10

0.1 RDS(on) LIMIT 5

THERMAL LIMIT dc
PACKAGE LIMIT
0.01 0
0.1 1 10 100 25 50 75 100 125 150 175
VDS, DRAIN−TO−SOURCE VOLTAGE (VOLTS) TJ, STARTING JUNCTION TEMPERATURE (°C)

Figure 11. Maximum Rated Forward Biased Figure 12. Maximum Avalanche Energy versus
Safe Operating Area Starting Junction Temperature

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 NTMD3N08LR2

TYPICAL ELECTRICAL CHARACTERISTICS

10
Rthja(t), EFFECTIVE TRANSIENT
THERMAL RESISTANCE

1 D = 0.5
0.2
0.1
0.1
0.05 Normalized to qja at 10s.
0.02 Chip 0.0175 W 0.0710 W 0.2706 W 0.5776 W 0.7086 W
0.01
0.01
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
SINGLE PULSE Ambient
0.001
1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 1.0E+00 1.0E+01 1.0E+02 1.0E+03
t, TIME (s)

Figure 13. Thermal Response

di/dt
IS
trr
ta tb
TIME

tp 0.25 IS

IS

Figure 14. Diode Reverse Recovery Waveform

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 NTMD3N08LR2

PACKAGE DIMENSIONS

SOIC−8 NB
CASE 751−07
ISSUE AJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER
−X− ANSI Y14.5M, 1982.
A 2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
8 5 PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
B S 0.25 (0.010) M Y M PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
1 IN EXCESS OF THE D DIMENSION AT
4 MAXIMUM MATERIAL CONDITION.
−Y− K 6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
MILLIMETERS INCHES
G
DIM MIN MAX MIN MAX
A 4.80 5.00 0.189 0.197
C N X 45 _ B 3.80 4.00 0.150 0.157
SEATING C 1.35 1.75 0.053 0.069
PLANE D 0.33 0.51 0.013 0.020
−Z− G 1.27 BSC 0.050 BSC
H 0.10 0.25 0.004 0.010
0.10 (0.004) J 0.19 0.25 0.007 0.010
H M J K 0.40 1.27 0.016 0.050
D
M 0_ 8_ 0 _ 8 _
N 0.25 0.50 0.010 0.020
S 5.80 6.20 0.228 0.244
0.25 (0.010) M Z Y S X S
SOLDERING FOOTPRINT* STYLE 11:
PIN 1. SOURCE 1
2. GATE 1
3. SOURCE 2
1.52 4. GATE 2
5. DRAIN 2
0.060 6. DRAIN 2
7. DRAIN 1
8. DRAIN 1

7.0 4.0
0.275 0.155

0.6 1.270
0.024 0.050

SCALE 6:1 ǒinches

mm Ǔ

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent
rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other
applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur.
Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury
or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an
Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.

PUBLICATION ORDERING INFORMATION

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8