MUN5214DW1, NSBC114YDXV6, NSBC114YDP6 Dual NPN Bias Resistor Transistors R1 10 KW, R2 47 KW

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MUN5214DW1,

NSBC114YDXV6,
NSBC114YDP6
Dual NPN Bias Resistor
Transistors
R1 = 10 kW, R2 = 47 kW www.onsemi.com
NPN Transistors with Monolithic Bias PIN CONNECTIONS
Resistor Network
This series of digital transistors is designed to replace a single (3) (2) (1)
device and its external resistor bias network. The Bias Resistor
Transistor (BRT) contains a single transistor with a monolithic bias R1 R2
network consisting of two resistors; a series base resistor and a
Q1
base-emitter resistor. The BRT eliminates these individual
components by integrating them into a single device. The use of a BRT Q2
can reduce both system cost and board space.
R2
Features R1
• Simplifies Circuit Design
• Reduces Board Space
(4) (5) (6)

• Reduces Component Count


MARKING DIAGRAMS
• S and NSV Prefix for Automotive and Other Applications
Requiring Unique Site and Control Change Requirements; 6
AEC-Q101 Qualified and PPAP Capable* 7D MG
• These Devices are Pb-Free, Halogen Free/BFR Free and are RoHS SOT−363 G
CASE 419B
Compliant 1

MAXIMUM RATINGS
(TA = 25°C, common for Q1 and Q2, unless otherwise noted)
Rating Symbol Max Unit SOT−563 7D M G
Collector-Base Voltage VCBO 50 Vdc CASE 463A
1
Collector-Emitter Voltage VCEO 50 Vdc
Collector Current − Continuous IC 100 mAdc
Input Forward Voltage VIN(fwd) 40 Vdc SOT−963 PM
Input Reverse Voltage VIN(rev) 6 Vdc CASE 527AD
1
Stresses exceeding those listed in the Maximum Ratings table may damage the
device. If any of these limits are exceeded, device functionality should not be
assumed, damage may occur and reliability may be affected. 7D/P = Specific Device Code
M = Date Code*
ORDERING INFORMATION G = Pb-Free Package

Device Package Shipping† (Note: Microdot may be in either location)

MUN5214DW1T1G, SOT−363 3,000 / Tape & Reel *Date Code orientation may vary depending up-
SMUN5214DW1T1G* on manufacturing location.

NSVMUN5214DW1T3G* SOT−363 10,000 / Tape & Reel


NSBC114YDXV6T1G SOT−563 4,000 / Tape & Reel
NSVBC114YDXV6T1G*
NSBC114YDXV6T5G SOT−563 8,000 / Tape & Reel
NSBC114YDP6T5G SOT−963 8,000 / Tape & Reel
†For information on tape and reel specifications, including part orientation and
tape sizes, please refer to our Tape and Reel Packaging Specifications
Brochure, BRD8011/D.

© Semiconductor Components Industries, LLC, 2014 1 Publication Order Number:


April, 2018 − Rev. 4 DTC114YD/D
MUN5214DW1, NSBC114YDXV6, NSBC114YDP6

THERMAL CHARACTERISTICS
Characteristic Symbol Max Unit
MUN5214DW1 (SOT−363) ONE JUNCTION HEATED
Total Device Dissipation PD
TA = 25°C (Note 1) 187 mW
(Note 2) 256
Derate above 25°C (Note 1) 1.5 mW/°C
(Note 2) 2.0
Thermal Resistance, (Note 1) RqJA 670 °C/W
Junction to Ambient (Note 2) 490
MUN5214DW1 (SOT−363) BOTH JUNCTION HEATED (Note 3)
Total Device Dissipation PD
TA = 25°C (Note 1) 250 mW
(Note 2) 385
Derate above 25°C (Note 1) 2.0 mW/°C
(Note 2) 3.0
Thermal Resistance, RqJA °C/W
Junction to Ambient (Note 1) 493
(Note 2) 325
Thermal Resistance, RqJL °C/W
Junction to Lead (Note 1) 188
(Note 2) 208
Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C
NSBC114YDXV6 (SOT−563) ONE JUNCTION HEATED
Total Device Dissipation PD
TA = 25°C (Note 1) 357 mW
Derate above 25°C (Note 1) 2.9 mW/°C
Thermal Resistance, RqJA °C/W
Junction to Ambient (Note 1) 350
NSBC114YDXV6 (SOT−563) BOTH JUNCTION HEATED (Note 3)
Total Device Dissipation PD
TA = 25°C (Note 1) 500 mW
Derate above 25°C (Note 1) 4.0 mW/°C
Thermal Resistance, RqJA °C/W
Junction to Ambient (Note 1) 250
Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C
NSBC114YDP6 (SOT−963) ONE JUNCTION HEATED
Total Device Dissipation PD
TA = 25°C (Note 4) 231 MW
(Note 5) 269
Derate above 25°C (Note 4) 1.9 mW/°C
(Note 5) 2.2
Thermal Resistance, RqJA °C/W
Junction to Ambient (Note 4) 540
(Note 5) 464
NSBC114YDP6 (SOT−963) BOTH JUNCTION HEATED (Note 3)
Total Device Dissipation PD
TA = 25°C (Note 4) 339 MW
(Note 5) 408
Derate above 25°C (Note 4) 2.7 mW/°C
(Note 5) 3.3
Thermal Resistance, RqJA °C/W
Junction to Ambient (Note 4) 369
(Note 5) 306
Junction and Storage Temperature Range TJ, Tstg −55 to +150 °C
1. FR−4 @ Minimum Pad.
2. FR−4 @ 1.0 × 1.0 Inch Pad.
3. Both junction heated values assume total power is sum of two equally powered channels.
4. FR−4 @ 100 mm2, 1 oz. copper traces, still air.
5. FR−4 @ 500 mm2, 1 oz. copper traces, still air.

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2
MUN5214DW1, NSBC114YDXV6, NSBC114YDP6

ELECTRICAL CHARACTERISTICS (TA = 25°C, common for Q1 and Q2, unless otherwise noted)
Characteristic Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Collector-Base Cutoff Current ICBO nAdc
(VCB = 50 V, IE = 0) − − 100
Collector-Emitter Cutoff Current ICEO nAdc
(VCE = 50 V, IB = 0) − − 500
Emitter-Base Cutoff Current IEBO mAdc
(VEB = 6.0 V, IC = 0) − − 0.2
Collector-Base Breakdown Voltage V(BR)CBO Vdc
(IC = 10 mA, IE = 0) 50 − −
Collector-Emitter Breakdown Voltage (Note 6) V(BR)CEO Vdc
(IC = 2.0 mA, IB = 0) 50 − −
ON CHARACTERISTICS
DC Current Gain (Note 6) hFE
(IC = 5.0 mA, VCE = 10 V) 80 140 −
Collector-Emitter Saturation Voltage (Note 6) VCE(sat) V
(IC = 10 mA, IB = 0.3 mA) − − 0.25
Input Voltage (Off) Vi(off) Vdc
(VCE = 5.0 V, IC = 100 mA) − 0.7 0.3
Input Voltage (On) Vi(on) Vdc
(VCE = 0.2 V, IC = 1.0 mA) 1.4 0.8 −
Output Voltage (On) VOL Vdc
(VCC = 5.0 V, VB = 2.5 V, RL = 1.0 kW) − − 0.2
Output Voltage (Off) VOH Vdc
(VCC = 5.0 V, VB = 0.5 V, RL = 1.0 kW) 4.9 − −
Input Resistor R1 7 10 13 kW
Resistor Ratio R1/R2 0.17 0.21 0.25
6. Pulsed Condition: Pulse Width = 300 ms, Duty Cycle ≤ 2%.

400
PD, POWER DISSIPATION (mW)

350

300

250
(1) SOT−363; 1.0 × 1.0 Inch Pad
200
(1) (2) (3) (2) SOT−563; Minimum Pad
(3) SOT−963; 100 mm2, 1 oz. Copper Trace
150

100

50

0
−50 −25 0 25 50 75 100 125 150
AMBIENT TEMPERATURE (°C)
Figure 1. Derating Curve

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3
MUN5214DW1, NSBC114YDXV6, NSBC114YDP6

TYPICAL CHARACTERISTICS
MUN5214DW1, NSBC114YDXV6
VCE(sat), COLLECTOR−EMITTER VOLTAGE (V)

1 1000
IC/IB = 10 VCE = 10 V
150°C
25°C

hFE, DC CURRENT GAIN


25°C 100
−55°C
0.1 150°C

10

−55°C

0.01 1
0 10 20 30 40 50 0.1 1 10 100
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)

Figure 2. VCE(sat) vs. IC Figure 3. DC Current Gain

3.6 100
Cob, OUTPUT CAPACITANCE (pF)

3.2 f = 10 kHz
IC, COLLECTOR CURRENT (mA)

IE = 0 A
2.8 10 −55°C
TA = 25°C
2.4
2 1
25°C
1.6
0.1 150°C
1.2
0.8
0.01
0.4
VO = 5 V
0 0.001
0 10 20 30 40 50 0 1 2 3 4 5 6 7 8 9 10
VR, REVERSE VOLTAGE (V) Vin, INPUT VOLTAGE (V)

Figure 4. Output Capacitance Figure 5. Output Current vs. Input Voltage

100
Vin, INPUT VOLTAGE (V)

10
25°C −55°C

1
150°C

VO = 0.2 V
0.1
0 10 20 30 40 50
IC, COLLECTOR CURRENT (mA)

Figure 6. Input Voltage vs. Output Current

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4
MUN5214DW1, NSBC114YDXV6, NSBC114YDP6

TYPICAL CHARACTERISTICS
NSBC114YDP6
VCE(sat), COLLECTOR−EMITTER VOLTAGE (V)

1 1000
IC/IB = 10 VCE = 10 V
150°C
25°C

hFE, DC CURRENT GAIN


25°C
100 −55°C

0.1 150°C

10
−55°C

0.01 1
0 10 20 30 40 50 0.1 1 10 100
IC, COLLECTOR CURRENT (mA) IC, COLLECTOR CURRENT (mA)

Figure 7. VCE(sat) vs. IC Figure 8. DC Current Gain

2.4 100
Cob, OUTPUT CAPACITANCE (pF)

f = 10 kHz
IC, COLLECTOR CURRENT (mA)

2 IE = 0 A −55°C
10
TA = 25°C
1.6
1
1.2

0.1 25°C
0.8

0.4 0.01 150°C


VO = 5 V
0 0.001
0 10 20 30 40 50 0 1 2 3 4 5 6 7
VR, REVERSE VOLTAGE (V) Vin, INPUT VOLTAGE (V)

Figure 9. Output Capacitance Figure 10. Output Current vs. Input Voltage

100
Vin, INPUT VOLTAGE (V)

10
25°C
−55°C

1
150°C

VO = 0.2 V
0.1
0 10 20 30 40 50
IC, COLLECTOR CURRENT (mA)

Figure 11. Input Voltage vs. Output Current

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5
MUN5214DW1, NSBC114YDXV6, NSBC114YDP6

PACKAGE DIMENSIONS

SC−88/SC70−6/SOT−363
CASE 419B−02
ISSUE Y
2X
aaa H D
NOTES:
D H 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
A 3. DIMENSIONS D AND E1 DO NOT INCLUDE MOLD FLASH,
D PROTRUSIONS, OR GATE BURRS. MOLD FLASH, PROTRU-
GAGE
PLANE SIONS, OR GATE BURRS SHALL NOT EXCEED 0.20 PER END.
4. DIMENSIONS D AND E1 AT THE OUTERMOST EXTREMES OF
6 5 4 THE PLASTIC BODY AND DATUM H.
L 5. DATUMS A AND B ARE DETERMINED AT DATUM H.
L2 6. DIMENSIONS b AND c APPLY TO THE FLAT SECTION OF THE
E E1 LEAD BETWEEN 0.08 AND 0.15 FROM THE TIP.
DETAIL A 7. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION.
1 2 3
ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 TOTAL IN
EXCESS OF DIMENSION b AT MAXIMUM MATERIAL CONDI-
2X aaa C TION. THE DAMBAR CANNOT BE LOCATED ON THE LOWER
2X 3 TIPS RADIUS OF THE FOOT.
bbb H D
e MILLIMETERS INCHES
DIM MIN NOM MAX MIN NOM MAX
B 6X b A −−− −−− 1.10 −−− −−− 0.043
ddd M C A-B D A1 0.00 −−− 0.10 0.000 −−− 0.004
TOP VIEW A2 0.70 0.90 1.00 0.027 0.035 0.039
b 0.15 0.20 0.25 0.006 0.008 0.010
C 0.08 0.15 0.22 0.003 0.006 0.009
A2 DETAIL A D 1.80 2.00 2.20 0.070 0.078 0.086
E 2.00 2.10 2.20 0.078 0.082 0.086
A E1 1.15 1.25 1.35 0.045 0.049 0.053
e 0.65 BSC 0.026 BSC
L 0.26 0.36 0.46 0.010 0.014 0.018
L2 0.15 BSC 0.006 BSC
aaa 0.15 0.006
bbb 0.30 0.012
6X ccc C ccc 0.10 0.004
A1 ddd 0.10 0.004
SEATING c
C PLANE
SIDE VIEW END VIEW

RECOMMENDED
SOLDERING FOOTPRINT*
6X 6X
0.30 0.66

2.50

0.65
PITCH
DIMENSIONS: MILLIMETERS

*For additional information on our Pb−Free strategy and soldering


details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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6
MUN5214DW1, NSBC114YDXV6, NSBC114YDP6

PACKAGE DIMENSIONS

SOT−563, 6 LEAD
CASE 463A
ISSUE G

NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
D 2. CONTROLLING DIMENSION: MILLIMETERS
A 3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
−X−
L FINISH THICKNESS. MINIMUM LEAD THICKNESS
IS THE MINIMUM THICKNESS OF BASE MATERIAL.

6 5 4 MILLIMETERS INCHES
E DIM MIN NOM MAX MIN NOM MAX
HE A 0.50 0.55 0.60 0.020 0.021 0.023
−Y−
1 2 3 b 0.17 0.22 0.27 0.007 0.009 0.011
C 0.08 0.12 0.18 0.003 0.005 0.007
D 1.50 1.60 1.70 0.059 0.062 0.066
b 5 PL
6 C E 1.10 1.20 1.30 0.043 0.047 0.051
e e 0.5 BSC 0.02 BSC
0.08 (0.003) M X Y L 0.10 0.20 0.30 0.004 0.008 0.012
HE 1.50 1.60 1.70 0.059 0.062 0.066

SOLDERING FOOTPRINT*
0.3
0.0118

0.45
0.0177
1.0
1.35 0.0394
0.0531

0.5 0.5
0.0197 0.0197

SCALE 20:1 ǒinches


mm Ǔ

*For additional information on our Pb−Free strategy and soldering


details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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7
MUN5214DW1, NSBC114YDXV6, NSBC114YDP6

PACKAGE DIMENSIONS

SOT−963
CASE 527AD
ISSUE E

NOTES:
D X 1. DIMENSIONING AND TOLERANCING PER ASME
A
Y Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS
3. MAXIMUM LEAD THICKNESS INCLUDES LEAD
FINISH THICKNESS. MINIMUM LEAD
6 5 4 THICKNESS IS THE MINIMUM THICKNESS OF
E HE BASE MATERIAL.
4. DIMENSIONS D AND E DO NOT INCLUDE MOLD
1 2 3 FLASH, PROTRUSIONS, OR GATE BURRS.
MILLIMETERS
DIM MIN NOM MAX
TOP VIEW C A 0.34 0.37 0.40
SIDE VIEW b 0.10 0.15 0.20
C 0.07 0.12 0.17
D 0.95 1.00 1.05
e 6X L E 0.75 0.80 0.85
e 0.35 BSC
HE 0.95 1.00 1.05
L 0.19 REF
L2 0.05 0.10 0.15

6X L2 6X b
0.08 X Y
BOTTOM VIEW

RECOMMENDED
MOUNTING FOOTPRINT*
6X 6X
0.20 0.35

PACKAGE
OUTLINE
1.20

0.35
PITCH
DIMENSIONS: MILLIMETERS

*For additional information on our Pb-Free strategy and soldering


details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.

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