FDD6637 888878 PDF
FDD6637 888878 PDF
FDD6637 888878 PDF
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FDD6637 35V P-Channel PowerTrench MOSFET
March 2015
FDD6637
35V P-Channel PowerTrench MOSFET
• RoHS Compliant
Applications
• Inverter
• Power Supplies
D
G
G
S
D-PAK
TO-252 S
(TO-252)
Thermal Characteristics
RθJC Thermal Resistance, Junction-to-Case (Note 1) 2.2 °C/W
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 40
RθJA Thermal Resistance, Junction-to-Ambient (Note 1b) 96
Off Characteristics(Note 2)
Drain–Source Breakdown
BVDSS VGS = 0 V, ID = –250 µA –35 V
Voltage
IDSS Zero Gate Voltage Drain Current VDS = –28 V, VGS = 0 V –1 µA
IGSS Gate–Body Leakage VGS = ±25 V, VDS = 0 V ±100 nA
On Characteristics (Note 2)
Dynamic Characteristics
Ciss Input Capacitance 2370 pF
VDS = –20 V, V GS = 0 V,
Coss Output Capacitance 470 pF
f = 1.0 MHz
Crss Reverse Transfer Capacitance 250 pF
RG Gate Resistance f = 1.0 MHz 3.6 Ω
Notes:
1. RθJA is the sum of the junction-to-case and case -to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0%
PD
3. Maximum current is calculated as: R DS(ON)
where PD is maximum power dissipation at T C = 25°C and RDS(on) is at T J(max) and V GS = 10V. Package current limitation is 21A
4. BV(avalanche) Single-Pulse rating is guaranteed if device is operated within the UIS SOA boundary of the device.
100 2.4
VGS = -10V -6.0V VGS = -3.5V
-5.0V
DRAIN-SOURCE ON-RESISTANCE
2.2
-4.5V
80
-I D, DRAIN CURRENT (A)
NORMALIZED
-4.0V 1.8
60
1.6 -4.0V
-4.5V
40 -3.5V
1.4 -5.0V
-6.0V
1.2
20 -3.0V -8.0V
-10V
1
0 0.8
0 1 2 3 4 0 20 40 60 80 100
-VD S, DRAIN-SOURCE VOLTAGE (V) -I D, DRAIN CURRENT (A)
1.8 0.05
ID = -14A
V GS = -10V I D = -7A
DRAIN-SOURCE ON-RESISTANCE
1.6
0.04
1.4
NORMALIZED
0.03
o
1.2 TA = 125 C
0.02
1
TA = 25o C
0.01
0.8
0.6 0
-50 -25 0 25 50 75 100 125 150 2 4 6 8 10
o
TJ , JUNCTION TEMPERATURE ( C) -VGS, GATE TO SOURCE VOLTAGE (V)
100 1000
VD S = -5V VGS = 0V
-I S, REVERSE DRAIN CURRENT (A)
100
80 o
-I D , DRAIN CURRENT (A)
T A = -55 C o
125 C 10
60 TA = 125o C
1
o
25 C
0.1 o
40 25 C
0.01 -55 C
o
20
0.001
0 0.0001
1 2 3 4 5 0 0.2 0.4 0.6 0.8 1 1.2 1.4
-VGS, GATE TO SOURCE VOLTAGE (V) -VSD , BODY DIODE FORWARD VOLTAGE (V)
10 3200
I D = -14A VDS = 10V f = 1MHz
-VGS, GATE-SOURCE VOLTAGE (V)
30V VGS = 0 V
8
2400
CAPACITANCE (pF)
20V C iss
6
1600
C oss
800
2
C rss
0 0
0 10 20 30 40 50 0 5 10 15 20 25 30
Qg, GATE CHARGE (nC) VD S, DRAIN TO SOURCE VOLTAGE (V)
1000 100
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
Rθ JA = 96°C/W
100 100µs 80 T A = 25°C
-I D , DRAIN CURRENT (A)
1ms
R DS(ON) LIMIT 10ms
10 100ms 60
1s
10s
DC 40
1
VGS = -10V
SINGLE PULSE
o 20
0.1 R θJA = 96 C/W
o
T A = 25 C
0
0.01 0.01 0.1 1 10 100 1000
0 0 1 10 100
t1 , TIME (sec)
-VDS, DRAIN-SOURCE VOLTAGE (V)
Figure 9. Maximum Safe Operating Area Figure 10. Single Pulse Maximum
Power Dissipation
100 1000
I(pk), PEAK TRANSIENT CURRENT (A)
SINGLE PULSE
Rθ JA = 96°C/W
I (AS) , AVALANCHE CURRENT
80 T A = 25°C
o
TJ = 25 C
100
60
40
10
20
0 1
0.01 0.1 1 10 100 1000 0.001 0.01 0.1 1 10
t1 , TIME (sec) tA V, TIME IN AVANCHE(ms)
1
TRANSIENT THERMAL RESISTANCE
D = 0.5
r(t), NORMALIZED EFFECTIVE
T J - T A = P * Rθ JA (t)
SINGLE PULSE
Duty Cycle, D = t1 / t 2
0.001
0.001 0.01 0.1 1 10 100 1000
t 1, TIME (sec)
L BVDSS
VDS
tP
VG VDS
RGEN DUT
- IAS
VDD VDD
0V +
VGS tp IAS
vary tP to obtain
required peak IAS 0.01Ω
tAV
Figure 14. Unclamped Inductive Load Test Figure 15. Unclamped Inductive Waveforms
Circuit
-
QG
50kΩ 10V
10V
10µF
+ 1µF -
VGS Q GS QGD
VDD
+
VG
DUT
Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveform
RL t ON tOFF
VDS
t d(ON) td(OFF)
VGS - VDS tr tf
90% 90%
RGEN DUT VDD
+
10% 10%
VGS 0V
Pulse Width ≤ 1µs
Duty Cycle ≤ 0.1% 90%
V GS
50% 50%
10%
Pulse Width
0V
Figure 18. Switching Time Test Circuit Figure 19. Switching Time Waveforms
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