EXCEL ENGINEERING COLLEGE

(Autonomous)
ELECTRONICS AND COMMUNICATION ENGINEERING
Fifth Semester
20PE021 ASIC Design
Regulations 2020
Question Bank
UNIT – I (Introduction to ASIC, CMOS LOGIC and ASIC Library Design)
PART- A
Q.No Questions
Define ASIC.
 ASIC - Application Specific Integrated Circuit. ASIC is a non-standard integrated circuit that is designed for a
specific use or application.
 ASIC design is undertaken for a product that will have a large production run and it may contain a very large
1
part of the electronics needed on a single integrated circuit.
 Examples for ASIC ICs are: chips for a toy bear that talk, a chip for a satellite, a chip designed to handle the
interface between memory and a microprocessor for a workstation CPU and a chip containing a
microprocessor as a cell together with other logic.
Classify the types of ASIC.
 Full Custom Design
2
 Semi- Custom Design
 Standard Cell Based ASICs
Label the functions of Transmission gates.
 Transmission gates represent another class of logic circuits. It consists of a PMOS and NMOS connected in
parallel.
 Gate voltage applied to these gates is complementary of each other (C and Cbar shown in figure).
Transmission gates act as bidirectional switch between two nodes A and B controlled by signal C.
 Gate of NMOS is connected to C and gate of PMOS is connected to Cbar. When control signal C is high both
the transistors are on and provides a low resistance path between A and B.
 When C is low both the transistors are turned off and provide high impedance path between A and B.
3

State full custom ASIC design.

 It is a design methodology useful for integrated circuits. In this design the resistors, transistors, digital logic,
4 capacitors and analog circuits are all positioned in the circuit layout.
 Generally full custom designs are referred as “handcrafted” designs. Microprocessor is a simple example of full
custom IC.
What is standard cell-based ASIC design?
 A cell-based ASIC (CBIC) uses predesigned logic cells known as standard cells. The standard cell areas also
5 called flexible blocks in a CBIC are built of rows in standard cells.
 The ASIC designer defines only the placement of standard cells and the interconnect in a CBIC. All the mask
layers of a CBIC are customized and are unique to a particular customer.
 Compare channeled gate array and channel less gate array.
Sl.No channeled gate array channel less gate array
1 There are predefined areas set There are no predefined areas set
6 aside for routing between cells. aside for routing between cells.
2 Only the interconnect isOnly some mask layers are customized
customized. for the interconnect.
3 Manufacturing lead time is betweenManufacturing lead time is between two
two days and two weeks days and two weeks
Classify the two main approaches of clocking in sequential Logic Cells.
7  Multiphase clocks or a single clock
 Synchronous design
Label the steps in ASIC design flow.
 Design entry
 Logic synthesis
 System partitioning
 Prelayout simulation
8
 Floor planning
 Placement
 Routing
 Extraction
 Post layout simulation
Name the advantages of synchronous design.
 It allows automated design and safe.
9
 It permits vendor signoff (a guarantee that the ASIC will work as simulated).
 The majority of ASICs use a synchronous design style.
State Gate Array Based ASIC.
 It is a prefabricated silicon chip in which transistors, logic gates and other active devices are placed at
predefined positions and manufactured on a wafer. Predefined pattern of gate array based ASIC is known
as Base Array.
10
 The element or logic cell present in the base array is often called as Base Cell. Usually gate array based ASIC
designs are known popularly by the name Masked Gate Array.
 ASIC designer can choose predesigned logic cells from the gate array library for better and easy design. The
cells present in the gate array library are often called as Macros.
Infer about Logic synthesis.
 Logic synthesis is a high-level description of the design which is converted into an optimized gate-level
11 representation of a given standard cell library and certain design constraints.
 The code is in the form of a gate-level netlist of a particular standard cell library. During logical Synthesis we
also get various reports on timing power and area of design.
List the types of gate arrays in ASIC.
 Channeled gate arrays
12
 Channel less gate arrays
 Structured gate arrays
13 Calculate the intrinsic trans conductance k 'n of n-channel transistor with the following parameters I DSn (sat) = 2.5 mA
(with V DS = 3.0 V, V GS = 3.0 V, V t n = 0.65 V, T ox =100 Å), W = 60 m m, L = 6 m m.
2(L/W) IDSn (sat)
k n = –––––––––––––
'

( V GS – V t n ) 2
 2 (6/60) (2.5 ¥ 10 –3 )
= ––––––––––––––––
(3.0 – 0.65) 2
= 9.05 ¥ 10 –5 AV –2
Mention the pros and cons of data path.
Pros:
 Regular layout produces predictable and equal delay for each bit.
 Interconnect between cells can be built into each cell.
14
Cons:
 The overhead can make a narrow data path larger and slower than a standard-cell implementation.
 Data path cells have to be predesigned for use in a wide range of data path sizes
 Software to assemble a data path is more complex.
List the construction steps of single-stage combinational CMOS logic cell.
 Draw a schematic icon with an inversion on the last cell. Use de Morgan’s theorems “A NAND is an OR with
inverted inputs and a NOR is an AND with inverted inputs” to push the output bubble back to the inputs.
15  Form the n -channel stack working from the inputs on the bubble-out schematic: OR translates to a parallel
connection, AND translates to a series connection. If you have a bubble at an input, you need an inverter.
 Form the p -channel stack using the bubble-in schematic. If you do not have a bubble at the input gate
terminals, you need an inverter.
Mention the basic rules to size a logic cell.
 Any string of transistors connected between a power supply and the output in a cell with 1X drive should have
the same resistance as the n -channel transistor in a 1X inverter.
 A transistor with shape factor W 1/L 1 has a resistance proportional to L 1 /W 1.
16
 Two transistors in parallel with shape factors W 1 /L 1 and W 2 /L 2 are equivalent to a single transistor (W 1 /L 1 +
W 2 /L 2)/1.
 Two transistors with shape factors W 1 /L 2 and W 2 /L 2 , in series are equivalent to a single 1/(L 1 /W 1 + L 2 /W 2 )
transistor.
Predict the issues in deciding the parallel multiplier architectures.
 It is easier to fold triangles rather than trapezoids into squares. Wallace-tree multiplier is more suited to full
custom layout but is slightly larger than a Dadda multiplier.
 Both are less regular than an array multiplier. For cell-based ASICs, Dadda multiplier is smaller than a Wallace-
17 tree multiplier.
 The overall multiplier speed does depend on the size and architecture of the final CPA, but this may be
optimized independently. This means a Dadda multiplier is always at least as fast as the Wallace-tree version.
 The low-order bits of any parallel multiplier settle first and can be added in the CPA before the remaining bits
settle. This allows multiplication and the final addition to be overlapped in time.
Define Junction capacitance.
 Junction capacitance is the capacitance which forms in a PN junction diode under reverse bias.
 When reverse bias voltage is applied across a PN junction diode the two regions P and N behave as electrodes
18
and the depletion region between two regions acts as dielectric medium.
 The P N regions and depletion region allows the storage of charge in electric field. This capacitance thus
formed is termed as junction capacitance or transition capacitance or depletion capacitance.
State Logical effort.
19  It is the ratio of the input capacitance of a gate to the input capacitance of an inverter delivering the same
output current.
Name the equivalent transistor size calculation methods.
20  Add transistors in parallel make all the lengths 1 and add the widths.
 Add transistors in series make all the widths 1 and add the lengths.
 PART- B
Q.No Questions
1 Describe in detail about ASIC and its types.
 ASIC - Application Specific Integrated Circuit. It is a non-standard integrated circuit that is designed for a
specific use or application.
 ASIC design is undertaken for a product that will have a large production run and the ASIC may contain a very
large part of the electronics needed on a single integrated circuit.
 Examples for ASIC ICs are: chips for a toy bear that talk, a chip for a satellite, a chip designed to handle the
interface between memory and a microprocessor for a workstation CPU and a chip containing a
microprocessor as a cell together with other logic.
Types of ASIC:

Full-Custom ASICs
 In a full-custom ASIC an engineer designs some or all of the logic cells, circuits or layout specifically for one
ASIC.
 It makes sense to take this approach only if there are no suitable existing cell libraries available that can be used
for the entire design. This might be because existing cell libraries are not fast enough or the logic cells are not
small enough or consume too much power.
 Need to use full-custom design if the ASIC technology is new or so specialized that there are no existing cell
libraries or because the ASIC is so specialized that some circuits must be custom designed.
 Fewer full-custom ICs are being designed because of the problems with these special parts of the ASIC. There
are one growing member of this family though the mixed analog/digital ASIC.
 In all integrated circuits the matching of component characteristics between chips is very poor, while the matching
of characteristics between components on the same chip is excellent.
 All mask layers are customized in a full-custom ASIC.
 It only makes sense to design a full-custom IC if there are no libraries available.
 Full-custom offers the highest performance and lowest part cost with the disadvantages of increased design time,
complexity, design expense, and highest risk.
Semi-Custom ASICs
 In this type of design logic cells are taken from standard libraries some masks are customized while some are
taken from the predesigned library.
 Based on the type of logic cells taken from the library and amount of customization allowed for interconnects
these ASICs are divided into two types- Standard cell-based ASIC and Gate Array-based ASIC.
Standard-Cell–Based ASICs
 A cell-based ASIC - Standard cells
 Possibly mega cells, mega functions, full custom blocks, system-level macros (SLMs), fixed blocks, cores, or
Functional Standard Blocks (FSBs)
 All mask layers are customized—transistors and interconnect.
  Custom blocks can be embedded and manufacturing lead time is about eight weeks.

Gate-Array–Based ASICs
 A gate array, masked gate array, MGA, or pre diffused array uses macros to reduce turn around time and
comprises a base array made from a base cell or primitive cell. There are three types:
 Channeled gate arrays
 Channel less gate arrays
 Structured gate arrays
Channeled Gate Array
 Only the interconnect is customized
 The interconnect uses predefined spaces between rows of base cells
 Manufacturing lead time is between two days and two weeks

Channel less Gate Array

 A channel less gate array (channel-free gate array, sea of-gates array, or SOG array)
 Only some (the top few) mask layers are customized— the interconnect
 Manufacturing lead time is between two days and two weeks.

Structured Gate Array

 An embedded gate array or structured gate array (master slice or master image)
 Only the interconnect is customized
 Custom blocks (the same for each design) can be embedded
 Manufacturing lead time is between two days and two weeks.
 Programmable Logic Devices
There are two types of programmable ASICs. They are PLD and FPGA
PLDs (Programmable Logic Devices)
 These are the standard cells readily available. We can program a PLD to customize a part of the application,
so they are considered as ASIC.
 We can use different methods and software to program a PLD. These contain a regular matrix of logic cells
usually programmable array logic along with flip-flops or latches. Here interconnects are present as a single
large block.
 PLDs have no customized logic cells or interconnect.

Field-Programmable Gate Arrays

 A field-programmable gate array (FPGA) or complex PLD
 None of the mask layers are customized
 A method for programming the basic logic cells and the interconnect
 The core is a regular array of programmable basic logic cells that can implement combinational as well as
sequential logic.
 A matrix of programmable interconnect surrounds the basic logic cells
 Programmable I/O cells surround the core
 Design turnaround is a few hours

2 Illustrate the various steps in ASIC Design flow with neat sketch.
 Design entry: Enter the design into an ASIC design system, either using a hardware description
language (HDL) or schematic entry.
 Logic synthesis: Use an HDL (VHDL or Verilog) and a logic synthesis tool to produce a netlist —a description
of the logic cells and their connections.
 System partitioning: Divide a large system into ASIC-sized pieces.
 Pre layout simulation: Check to see if the design functions correctly.
 Floor planning: Arrange the blocks of the netlist on the chip.
  Placement: Decide the locations of cells in a block.
 Routing: Make the connections between cells and blocks.
 Extraction: Determine the resistance and capacitance of the interconnect.
 Post layout simulation: Check to see the design still works with the added loads of the interconnect.
 Steps 1–4 are part of logical design, and steps 5–9 are part of physical design.
 There is some overlap. For example, system partitioning might be considered as either logical or physical
design.
 While performing system partitioning we have to consider both logical and physical factors.

3 Explain the working principle of n -channel MOS transistor.

 The below figure illustrates how electrons and holes abandon their dopant atoms leaving a depletion
region around a transistor’s source and drain. The region between source and drain is normally non
conducting.

An n -channel MOS transistor

 To make an n -channel transistor conducting, we must apply a positive voltage VGS that is greater than
the n -channel transistor threshold voltage Vtn.
 This establishes a thin conducting channel of electrons under the gate. MOS transistors can carry a very small
current with V GS < V tn , but we shall ignore this.
 A transistor can be conducting (V GS > V t n ) without any current flowing. To make current flow in an n -channel
transistor we must also apply a positive voltage, VDS.
 The above figure shows these connections and the connection to the fourth terminal of an MOS transistor
the bulk (well, tub, or substrate) terminal.
  For an n -channel transistor we must connect the bulk to the most negative potential, GND or VSS, to reverse
bias the bulk-to-drain and bulk-to-source pn -diodes.
 The arrow in the four-terminal n -channel transistor symbol in Figure which reflects the polarity of these PN -
diodes.
 The current flowing in the transistor is
Current (amperes) = charge (coulombs) per unit time (second). --------- (1)
 We can express the current in terms of the total charge in the channel Q.
 If tf (sometimes called the transit time) is the time that it takes an electron to cross between source and drain,
the drain-to-source current, IDSn , is
I DSn = Q / t f . -------------- (2)
 To find Q and tf. The velocity of the electrons v is given by the equation that forms the basis of Ohm’s law:
v = – m n E --------------- (3)
 Where m n is the electron mobility (m p is the hole mobility) and E is the electric field.
 Equation 3 is a vector equation, but we shall ignore the vertical electric field and concentrate on the horizontal
electric field, Ex, that moves the electrons between source and drain.
 The horizontal component of the electric field is E x = – V DS / L, directed from the drain to the source, where L is
the channel length. The electrons travel a distance L with horizontal velocity v x = – m n E x , so that
L L2
t f = ––– = ––––––– -------------- (4)
vx m n V DS
 To find the channel charge Q . The channel and the gate form the plates of a capacitor, separated by an
insulator the gate oxide.
 We know that the charge on a linear capacitor, C is Q = CV. Our lower plate, the channel, is not a linear
conductor. Charge only appears on the lower plate when the voltage between the gate and the channel, VGC,
exceeds the n -channel threshold voltage.
 For our nonlinear capacitor we need to modify the equation for a linear capacitor to the following:
Q = C ( V GC – V t n ) ---------- (5)
 The lower plate of our capacitor is resistive and conducting current, so that the potential in the channel, VGC,
varies. In fact, VGC = VGS at the source and VGC = VGS – VDS at the drain.
 What we really should do is find an expression for the channel charge as a function of channel voltage and sum
the charge all the way across the channel, from x = 0 (at the source) to x = L (at the drain).
 Instead we shall assume that the channel voltage, VGC (x), is a linear function of distance from the source and
take the average value of the charge, which is thus
Q = C [ ( V GS – V t n ) – 0.5 V DS ] ------------- (6)
 The gate capacitance C, is given by the formula for a parallel-plate capacitor with length L, width W, and plate
separation equal to the gate-oxide thickness Tox . Thus the gate capacitance is
WL e ox
C = –––––– = WLC ox ------------- (7)
T ox
where e ox is the gate-oxide dielectric permittivity.
 Now we can express the channel charge in terms of the transistor parameters,
Q = WL C ox [ ( V GS – V t n ) – 0.5 V DS ] ------------ (8)
Finally, the drain–source current is
I DSn = Q/ t f
= (W/L) m n C ox [ ( V GS – V t n ) – 0.5 V DS ] V DS
= (W/L)k ' n [ ( V GS – V t n ) – 0.5 V DS ] V DS ----------- (9)
The constant k n is the process transconductance parameter (or intrinsic trans conductance):
'
 k 'n = m n C ox ---------- (10)
We also define b n, the transistor gain factor (or just gain factor) as
(11)
b n = k ' n (W/L) ---------------

 The factor W/L (transistor width divided by length) is the transistor shape factor.
 Equation 9 describes the linear region of operation. This equation is valid until V DS = VGS – Vtn and then predicts
that IDS decreases with increasing VDS, which does not make physical sense.
 At V DS = V GS – V t n = V DS (sat) there is no longer enough voltage between the gate and the drain end of the
channel to support any channel charge.
 Clearly a small amount of charge remains or the current would go to zero, but with very little free charge the
channel resistance in a small region close to the drain increases rapidly and any further increase in V DS is
dropped over this region.
 Thus for V DS > V GS – V t n, the drain current IDS remains approximately constant at the saturation
current, I DSn (sat), where
I DSn (sat) = ( b n /2)( V GS – V t n ) 2 ; V GS > V t n ------------- (12)

4 Describe the working principle of CMOS Latch and Flip flop.

Latch:
 In CMOS Latch the clock input is high, the latch is transparent - changes at the D input appear at the output Q.
 When the enable (clock) goes low (Figure c), inverters I2 and I3 are connected together, forming a storage loop
that holds the last value on D until the enable goes high again.
 The storage loop will hold its state as long as power is on. A sequential logic cell is different from a
combinational cell because it has this feature of storage or memory.
 The output Q is unbuffered and connected directly to the output of I2 (and the input of I3), which is a storage
node.

CMOS latch
(a) A positive-enable latch using transmission gates without output buffering, the enable (clock) signal is buffered
inside the latch. (b) A positive-enable latch is transparent while the enable is high. (c) The latch stores the last
value at D when the enable goes low.
Flip Flop:
 In the below figure (b) the clock input is high, the master latch is transparent, and node M (for master) will
follow the D input.
 Meanwhile the slave latch is disconnected from the master latch and is storing whatever the previous value
of Q was.
 As the clock goes low (the negative edge) the slave latch is enabled and will update its state (and the output
 Q) to the value of node M at the negative edge of the clock.
 The slave latch will then keep this value of M at the output Q, despite any changes at the D input while the
clock is low (Figure c).
 When the clock goes high again, the slave latch will store the captured value of M. The combination of the
master and slave latches acts to capture or sample the D input at the negative clock edge, the active clock
edge.
 This type of flip-flop is a negative-edge–triggered flip-flop and its behavior is quite different from a latch. A
bubble shows the input is sensitive to the negative edge.
 To build a positive-edge–triggered flip-flop we invert the polarity of all the clocks—as we did for a latch.
 The waveforms in Figure (d) show the operation of the flip-flop as we have described it, and illustrate the
definition of setup time ( t SU ), hold time ( t H ), and clock-to-Q propagation delay ( t PD ).
 We must keep the data stable (a fixed logic '1' or '0') for a time t SU prior to the active clock edge, and stable
for a time t H after the active clock edge.

CMOS flip-flop
(a) This negative-edge–triggered flip-flop consists of two latches: master and slave.
(b) While the clock is high, the master latch is loaded.
(c) As the clock goes low, the slave latch loads the value of the master latch.
(d) Waveforms illustrating the definition of the flip-flop setup time t SU, hold time t H, and propagation delay from clock to
Q, t PD
5 Summarize any four types of adders with neat sketch.
Ripple carry adder:
 An N-bit adder can be constructed by casing N full adders as shown in below Figure for N=4. The carry-out of
bit i, Ci is the carry-in to bit i + 1.
 This carry is said to have twice the weight of the sum Si. The delay of the adder is set by the time for the carries
to ripple through the N stages.
 In carry-ripple adders, the critical path goes from C to Cout through many full adders, so the extra delay
 computing S.

Carry save adders:

 In most computations, we need to add several operands together, carry save adders are ideal for this type of
addition.
 A carry save adder consists of a ladder of standalone full adders, and carries out a number of partial additions.
 The principal idea is that the carry has a higher power of 2 and thus is routed to the next column. Doing
additions with Carry save adder saves time and logic.

 In this method, for the first 3 numbers a row of full adders are used. Then a row of full adders is added for each
additional number.
 The final results, in the form of two numbers SUM and CARRY, are then summed up with a carry propagate
adder or any other adder.
Carry skip adders:
 A carry-skip adder consists of a simple ripple carry-adder with a special speed up carry chain called a skip
chain. This chain defines the distribution of ripple carry blocks, which compose the skip adder.
 The addition of two binary digits at stage i, where i is not equal to 0, of the ripple carry adder depends on the
carry in, Ci , which in reality is the carry out, Ci-1, of the previous stage.
 Therefore, in order to calculate the sum and the carry out, Ci+1 , of stage i, it is imperative that the carry in, Ci,
be known in advance. It is interesting to note that in some cases Ci+1 can be calculated without knowledge of
Ci.
 Carry select adders:

 The concept of the carry-select adder is to compute alternative results in parallel and subsequently selecting
the correct result with single or multiple stage hierarchical techniques.
 In order to enhance its speed performance, the carry- select adder increases its area requirements. In these
adders both sum and carry bits are calculated for the two alternatives: input carry “0” and “1”.

 Once the carry-in is delivered, the correct computation is chosen (using a MUX) to produce the desired
output.
 Therefore instead of waiting for the carry-in to calculate the sum, the sum is correctly output as soon as the
carry-in gets there.
 The time taken to compute the sum is then avoided which results in a good improvement in speed.
6 Interpret the concepts of two multipliers and several issues in deciding the parallel multiplier architectures.
Dadda multiplier
 In a Dadda multiplier we work backward from the final product. Each stage has a maximum of 2, 3, 4, 6, 9, 13,
19 . . . outputs.
 Thus, in a 6-bit Wallace-tree multiplier Figure we require 3 stages (with 3 adder delays—plus the delay of a
10-bit output CPA) for a 6-bit Dadda multiplier.
 There are 19 adders (4 half adders) in the CSA plus the 10 adders (2 half adders) in the CPA. A
Dadda multiplier is usually faster and smaller than a Wallace-tree multiplier.
 Ferrari–Stefanelli multiplier
The Ferrari–Stefanelli multiplier (Figure b) “nests” multipliers—the 2-bit sub multipliers reduce the number of
partial products.

Ferrari–Stefanelli multiplier
(a) A conventional 4-bit array multiplier using AND gates to calculate the summands with (2, 2) and (3, 2) counters to sum
the partial products. (b) A 4-bit Ferrari–Stefanelli multiplier using 2-bit sub multipliers to construct the partial product array.
(c) A circuit implementation for an inverting 2-bit sub multiplier.
There are several issues in deciding between parallel multiplier architectures:
1. It is easier to fold triangles rather than trapezoids into squares, a Wallace-tree multiplier is more suited to full-
custom layout, but is slightly larger, than a Dadda multiplier—both are less regular than an array multiplier. For
cell-based ASICs, a Dadda multiplier is smaller than a Wallace-tree multiplier.
2. The overall multiplier speed does depend on the size and architecture of the final CPA, but this may be
optimized independently of the CSA array. This means a Dadda multiplier is always at least as fast as the
Wallace-tree version.
3. The low-order bits of any parallel multiplier settle first and can be added in the CPA before the remaining bits
settle. This allows multiplication and the final addition to be overlapped in time.
4. Any of the parallel multiplier architectures may be pipelined. We may also use a variably pipelined approach
that tailors the register locations to the size of the multiplier.
5. Power dissipation is reduced by the tree-based structures. The simplified carry-save logic produces fewer
signal transitions and the tree structures produce fewer glitches than a chain.

(Note:*Blooms Level (R – Remember, U – Understand, AP – Apply, AZ – Analyze, E – Evaluate, C – Create)

PART A- Blooms Level : Remember, Understand, Apply
PART B- Blooms Level: Understand, Apply, Analyze, Evaluate(if possible)
 Marks: 16 Marks, 8+8 Marks, 10+6 Marks)

Subject In charge Course Coordinator HOD IQAC

(Name & Signature) (Name & Signature)