Physical Design

IL2200 ASIC Design
Muhammad Ali Shami

Physical Design
Lecture Outline

Physical Implementation Styles ASIC Design Flow Floor and Power planning Placement Clock Tree Synthesis Routing Timing Analysis Verification and Energy Calculation
22 November, 2010
IL2200 , ASIC Design
Slide 2
Physical Implementation Styles

Semi Custom ASICs/FPGAs AMD Newer Intel Array Based Full Custom Older Intel
Cell Based
Standard Cells
Macro Cells
Pre Diffused Gate Arrays Structured ASICs !
Pre Wired FPGAs
Coarse Grain Reconfigurable Architecture
Standard Cell Layout

Cells are of same height but different width. The layout is organised as rows of cells seperated by channels used for routing. The routing channels are not fixed in their height. This is dependent on the routing density in it. This is one important reason why standard cell layout is more flexible compared to array based designs where the routing channels have a fixed capacity. Cells in the same row or adjacent rows can be connected by running wires through the adjacent channel. To connect cells in non-adjacent rows, vertical routing space on the sides is used or special feed through cells are instantiated as shown in It is possible that in some rows, some space may be left unused, as either no cell would fit there or routing considerations dictate placing cells elsewhere. Cells may have the same height but can differ in complexity from simple gates to cells as complex as full adders. Complex cells use the width to spread out the necessary logic. As the logic can be spread out only horizontally, the interconnection delay is typically larger compared to cells design without the fixed height constraint. As the same std. cell is supposed to work correctly in a variety of circuit conditions, the transistors are typically larger than in a custom layout. Some libraries may provide two varieties: low and high power. Technology mapping tools will select one based on estimation. c e l ls Rats nest are a good way to judge wire congestion and long nets.
r o u ti n g a r e a
f e e d th r o u g h c e ll
r o u ti n g a re a w a s te d sp a ce
Standard Cells
Standard Cell Height
VDD Bus P-Type Transistor Diff Spacing N-Type Transistor VSS Bus
2-input AND
4-input AND
22 November, 2010
Slide 5
Design Flow
Design Specification
VHDL Code
Logical Design
Thing you already learned in IL2204
learned in IL2200 till now
RTL Development Functional Verification
Simulation
No
Synthesis
Yes
Gate Level Net list
22 November, 2010
Slide 6
Physical Design
Converting gate-level netlist to physical layout
22 November, 2010
Slide 7
Physical Design Flow

Synthesis
Gate Level Net list
Floor and Power Planning

Floor Planning
Placement CTS Routing
Physical Design
Thing to Learn in this lecture
Routing
STA
Post Route Verification
Verification
Sign Off
22 November, 2010
Slide 8
Before Physical Design..
You must have synthesized gate level netlist. Please verify that this netlist is working properly by doing gate level simulation in NCSim/ModelSim Also Generate Standard delay constraint file .sdc.
22 November, 2010
Slide 9
SoC Encounter
We use Cadence SoC Encounter 8.1 for Layout.
10
Design Import
Before starting the Physical Design We first have to import the design and associated libraries
.LEF File Contains layer, via and macro definition .LIB File (.TLF) This file has timing information e.g delay and capacitance Verilog Netlist Netlist file generated by Synthesis Tool .SDC File (Synopsys Design Constraints Format) Constraint file generated by synthesis tool .DEF File Design exchange format to output the design so it is readable by other modules.
IL2200 , ASIC Design Slide 11
22 November, 2010
Design Import
Design Import Design

Veriglog Netlist File Toplevel of the design .Lib .TLF Files .LEF File .SDC File
22 November, 2010
Slide 12
Design Import
Advance Power
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Slide 13
Floor Planning
Results in Efficient Design Implementation Two styles of Implementation
Flat
Small to Medium ASIC Better Area Usage Since no reserve space around each sub-design for power/ground
Hierarchical

For very large design When sub-systems are design individually Possible only if a design hierarchy exist.
22 November, 2010
#/* Translate to target independent structure (GTECH) */ analyze -format vhdl -lib WORK {"./SOURCE/mics.vhd"} analyze -format vhdl -lib WORK {"./SOURCE/SRAM.vhd"} .. elaborate FIR_Toplevel -lib WORK -update -param "width = 4" -param "filter_taps=5" ungroup all Link uniquify set_wire_load_mode segmented set_wire_load_model -name "TSMC8K_Lowk_Conservative" #T=-40, V=1.1 set_units -time ns -resistance kOhm -capacitance pF -voltage V -current mA set_operating_conditions LTCOM #/* Specify clock constraint */ create_clock clk -period 4 set_false_path -from rst_n compile -map_effort medium -boundary_optimization write -hierarchy -format verilog -output /home/ali/ASICLABS/LAB2/LAB2_FIRToplevel.v write_sdc /home/ali/ASICLABS/LAB2/MAPPED/constraints.sdc
22 November, 2010
Floor Planning

Automatic Floor Planning Seed Selection: USB controllers PCI controllers Hierarchical modules Automatic Floorplan Synthesis analyzes the data flow between seeds (design blocks) based on their connectivity and their location
22 November, 2010
Slide 16
Floor Planning
Relative Floor Planning
Capture and define the placement relationship of floorplan objects independently from the actual coordinates in a floorplan
flexible way to place objects, such as modules, blocks, groups, blockages, pin guides, pre-routed wires, and power domains
I/O pins can be used as reference objects but they cannot be relative objects
22 November, 2010
Slide 17
Floor Planning
Orientation Keys for Relative Floor Planning
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Slide 18
Floor Planning
Pre-route example: S1 and S2 are relative to the object I2 and the Core_Boundary
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Slide 19
Floor Planning
Manually Floor Planed DRRA Fabric
22 November, 2010
Slide 20
Floor Planning
Aspect Ratio
Height/Width
Area of Stand. Cell/Area of Core Distance from IO Boundary Distance from Die Boundary
Core Utilization
Core to IO Boundary
Core to Die Boundary
22 November, 2010
Slide 21
Floor Planning
Adjustable Routing Channel Width

0um every row 10um every second row 10um every row
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Slide 22
Floor Planning
Cutting with Rectilinear Tool
Move Tool
Rectilinear Tool
Blockage tools
Clusters
22 November, 2010
Slide 23
Partitioning

Part of Floor Planning Standard Cells are in Floating States before placement.

Have not been assigned a fixed location in Core Time to define clusters and regions
To keep time critical component close
Soft Regions
Boundary can change during standard cell placement Prevent Standard cell crossing boundaries
Hard Regions
22 November, 2010
Partitioning
Exclusive Regions
Allow standard cells assigned to the region to be placed within the region Allow standard cells that do not belong to the region to be placed within the region
Non Exclusive Regions
22 November, 2010
Slide 25
Power Planning
Deal with Power Distribution Network Three levels of Power Distribution
Rings
Carries VDD and VSS around the chip Carries VDD and VSS from Rings across the chip
Stripes
Rails
Connect VDD and VSS to the standard cell VDD and VSS
22 November, 2010
Slide 26
Power Planning
Rings Stripes (vertical or horizontal) VDD VSS Rails Special Route
Power Distribution Network

22 November, 2010
Power Planning
Add Rings, Stripes & do a special route (SROUTE)
28
Power Distribution network Example
Power Distribution Network in DRRA
22 November, 2010
Slide 29
Placement
Global Placement algorithm are partitioned based Two Associated Cost functions
Reduce Total wiring or routing length Distribute standard cell instances homogeneously in ASIC Core such that optimal equilibrium among vertical and horizontal routing is achieved
22 November, 2010
Slide 30
Detailed Placement
After global placement
To Refine placement based on congestion, timing and power To distance standard cell instances from each other such that more routing tracks are created between them To optimize large sets of path delays Try to control the delay on signal path by imposing an upper bound delay or weight to net
Congestion Driven Placement
Timing Driven Placement
Net Based
22 November, 2010
Slide 31
Clock Tree Synthesis
Automatic insertion of buffers/inverters along the clock path to balance the clock delay to all the clock inputs.
Why balancing clock delay? Clock Skew?
22 November, 2010
Slide 34
Clock Distribution: How?
Source: MIT 6.375 Complex Digital System

22 November, 2010
Delay of a wire
Elmore Delay
Vin R1 C1 R2 C2 Ri-1 Ci-1 Ri Ci RN CN
T DN
i 1
Ci
j 1
Rj R1 R2 ... CN (R1 R2 ... RN)
T DN
C 1R 1 C
22 November, 2010
Slide 36
Optimizing Wire Delay
Divide the wire into N identical segments with length L/N Resistance= rL/N. Capacitance= cL/N
2
T DN
L N
2
rc N N 2
2 rc 1
2
...
Nrc
T DN
rc L
T DN
RC RC 2
N 2N
T DN
22 November, 2010
rcL 2
Slide 37
Equation shows that the wire delay depends on RC effect. One method to reduce RC is to insert intermediate buffers. Most Popular technique to reduce propagation delay Making a line m times shorter reduces its propagation delay quadratically
Vin
R/M C/M R/M C/M R/M C/M R/M C/M
Vout
22 November, 2010
Slide 38
For optimal propagation delay, buffer size increases in their drive strength d by a factor a for each level of clock tree path
Clock Source
a0 d
a1 d
a2 d
aNd
If clock buffers are not selected correctly they may cause the clock pulse width to degrade as the clock propagates through them
d
22 November, 2010
d
d
Slide 39
Skew and Jitter

Clock Skew = t2 - t1
Positive skew occurs when the transmitting register receives the clock earlier than the receiving register. Negative skew is the opposite: the receiving register gets the clock earlier than the sending register
t1 clk
D Q
Combinational Logic
D Q
t2
Clock Jitter
Period A
22 November, 2010
!= Period B
Why minimizing Skew and Jitter is hard?

22 November, 2010
Clock Distribution

22 November, 2010
Clock Distribution

22 November, 2010

D Q
clk
Combinational Logic
Without On-Chip Variation Awareness
Combinational Logic
clk
With On-Chip Variation Awareness

22 November, 2010
Clock Tree Synthesis in SoC Encounter

Fish Bone Routing Style
22 November, 2010
Slide 45
Clock Tree Synthesis in SoC Encounter
The color Difference tells us about clock skew
22 November, 2010
Slide 46
Electromigration
Electromigration (EM) is the movement or molecular transfer of metal from one area to another area that is caused by an excessive electrical current in the direction of electron flow. EM currents exceeding recommended guidelines can result in premature ASIC device failure
22 November, 2010
Slide 47
Routing
Global Routing
Decomposes ASIC design interconnection into net segments Assign these segments to regions Follows global routing Performs actually physical interconnection of ASIC design Places actual wire segments in the region defined by the global router to complete the connections between the ports
Detail Routing

22 November, 2010
Slide 48
Power Analysis
Power analysis
Reduces risk of IR voltage drops in power nets Ground bounce on the ground nets Reduces Electromigration effects due to high current
Resistance of power and ground net extracted Average current of each transistor connected to power net is calculated Average currents are distributed throughout the power net Calculate node voltages and branch currents Design goal violations shown
22 November, 2010
Slide 49
RC Extraction
RC extraction is the calculation of all the routed net capacitances and resistances Used for
Delay calculation Static Timing Analysis Circuit Simulation Signal Integrity Analysis
22 November, 2010
Slide 50
Verification
The complete placed and routed design is verified before fabrication Functional Verification
Verification is performed against behavioral RTL pre-layout and post-layout structural description (netlist) for the design validation. Assertion based verification Assertions macros are expressions that, if false, indicate and error Instantiated in RTL Code
Rule Based
22 November, 2010
Energy Calculation
Save your design as a Verilog Netlist Simulate the Design in NCSim/ModelSim Create a VCD File Restore the Design in encounter Read the VCD Activity file Report Power to get the average power Energy= Pave * Tperiod * No of Cycles
22 November, 2010
Slide 52
VCD File Script

run -timepoint 0 ns -absolute database -open /media/disk-1/mdpu/ADD2/MAC_0.vcd vcd -default -timescale us probe -create :mTile -vcd -all -depth all run -timepoint 100 us -absolute database -close /media/disk-1/mdpu/ADD2/MAC_0.vcd
22 November, 2010
Slide 53
Power Calculation in Encounter

restoreDesign /home/ali/PhysicalDesign/ICAD2/mdpu/Tile_final.enc.dat Tile extractRC -outfile file.cap read_activity_file -format VCD -vcd_scope Tile_tb/mTile /media/disk-1/mdpu/ADD2/MAC_0.vcd reportPower -noRailAnalysis -outfile /media/disk1/mdpu/ADD2/reports/powenc_0.rep exit
22 November, 2010
Slide 54

Physical Design

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IL2200 ASIC Design

Muhammad Ali Shami

IL2200 , ASIC Design

Physical Implementation Styles

Pre Diffused Gate Arrays Structured ASICs !

Pre Wired FPGAs

Coarse Grain Reconfigurable Architecture

Standard Cell Layout

IL2200 , ASIC Design

RTL Development Functional Verification

Gate Level Net list

IL2200 , ASIC Design

Converting gate-level netlist to physical layout

IL2200 , ASIC Design

Physical Design Flow

Floor and Power Planning

Placement CTS Routing

IL2200 , ASIC Design

Before Physical Design..

IL2200 , ASIC Design

We use Cadence SoC Encounter 8.1 for Layout.

Design Import Design

IL2200 , ASIC Design

IL2200 , ASIC Design

Results in Efficient Design Implementation Two styles of Implementation

IL2200 , ASIC Design

Relative Floor Planning

IL2200 , ASIC Design

IL2200 , ASIC Design

IL2200 , ASIC Design

Manually Floor Planed DRRA Fabric

IL2200 , ASIC Design

Core to Die Boundary

IL2200 , ASIC Design

Adjustable Routing Channel Width

IL2200 , ASIC Design

Cutting with Rectilinear Tool

IL2200 , ASIC Design

To keep time critical component close

Non Exclusive Regions

IL2200 , ASIC Design

Deal with Power Distribution Network Three levels of Power Distribution

IL2200 , ASIC Design

Power Distribution Network

Add Rings, Stripes & do a special route (SROUTE)

Power Distribution network Example

Power Distribution Network in DRRA

IL2200 , ASIC Design

IL2200 , ASIC Design

After global placement

Congestion Driven Placement

Timing Driven Placement

IL2200 , ASIC Design

Clock Tree Synthesis

Why balancing clock delay? Clock Skew?

IL2200 , ASIC Design

Clock Distribution: How?

Source: MIT 6.375 Complex Digital System

Clock Tree Synthesis