Cmos Chip Design Options

CMOS CHIP DESIGN
OPTIONS
ASIC Vs STANDARD IC
Standard ICs : ICs sold as standard parts.
- SSI/LSI/MSI IC such as MUX, encoder, memory
chips or microprocessor IC.
Application Specific Integrated Circuits (ASIC) :

- An IC customized to a particular system or
application.
- Chip for toy bear that talks, chip for satellite,
auto mobile control chip, etc.
ASIC Vs STANDARD IC
Application-Specific Standard Products (ASSP):-
- Some ICs might or might not be considered as
ASICs.
- Controller chip for a PC or Modem.
- Both are specific to an application but are sold to

many different system vendors.
Types of ASICs
ASICs
Semi-Custom
Full-Custom ASICs
ASICs
Stnadard-Cell Gate-Array based Praogrammable

based ASICs ASICs ASICs
PLDs FPGA
Full Custom ASICs
Full-custom ASIC design makes sense only
- When no suitable existing libraries exist or
- Existing library cells are not fast enough or
- The available pre-designed/pre-tested cells
consume too much power that a design can allow
or
- The available logic cells are not compact enough to
fit or
- ASIC technology is new or/and so special that no
cell library exits.
Full Custom ASICs – Cont’d
- All mask layers are customized .
- Include some (possibly all) customized logic
cells
- The use of predefined masks for
manufacturing leaves no option for circuit
modification during fabrication.
- Hence a full-custom ASIC cannot be modified
to suit different applications, and is generally
produced as a single, specific product for a
particular application only.
Masking
Mask Layers: Each IC is manufactured with
successive mask layers(10 – 15 layers)
- First half-dozen or so layers define

transistors
- Other half-dozen or so define
Interconnect
MASK LAYERS OF CMOS INVERTER
n well
Polysilicon
A
GND VDD
Y
n+ Diffusion
p+ n+ n+ p+ p+ n+
n well
p substrate
p+ Diffusion
substrate tap well tap
Contact
Metal
MOS TRANSISTOR FABRICATION
gate
IC package IC oxide
source channel drain
Silicon substrate
Full Custom ASICs – Cont’d
Advantages :
Offer highest performance
Lowest cost (smallest die size)
Disadvantages :
Increased design time
Complexity
Higher design cost and higher risk.
Examples :
High-Voltage Automobile Control Chips,
Analog/Digital Communication Chips, Sensors
and Actuators.
Semi-Custom ASICs
- can be partly customized to serve
different functions within its general area
of application.
- semi-custom ASIC's are designed to allow

a certain degree of modification during the
manufacturing process.
Semi-Custom ASICs – Cont’d
- It is manufactured with the masks for the diffused
layers already fully defined, so the transistors
and other active components of the circuit are
already fixed for that semi-custom ASIC design
- The customization of the final ASIC product to
the intended application is done by varying the
masks of the interconnection layers, e.g., the
metallization layers.
Semi-Custom ASICs – Cont’d
1. Standard Cell based ASICs (CBIC) :
-Uses predesigned logic cells (mux, flip-flops, AND gates etc)

known as standard cells (flexible blocks).
- Standard cells are used in combination with larger

predesigned cells (μcontroller or μp) known as mega cells (fixed
blocks).
- the standard cells can be placed anywhere in the silicon.

Standard Cell based ASICs (CBIC)
- Each standard cell can be optimized
individually.
- Each and every transistor in every standard
cell library can be chosen to maximize speed or
minimize area.
- Get all mask layers customized- transistors and
interconnect
- Manufacturing lead time is around 8 weeks
- Less efficient in size and performance but lower
in design cost
Standard Cell based ASICs (CBIC) :
Cell Based ASIC (CBIC)
2. Gate Array based ASICs
-Predefined pattern of transistors on a gate

array is the base array.
- The smallest element that is replicated to make
base array is the base cell (primitive cell).
- The designer chooses from a gate-array library
of pre-designed and pre-characterized logic cells
often called as macros.
- To distinguish it from other types of gate array,
it is also called as Masked Gate Array (MGA).
2. Gate Array based ASICs – Cont’d
Types of Masked Gate Array :-
a) Channeled gate arrays

b) Channel less gate arrays
c) Structured gate arrays
a) Channeled Gate Array
- Only the interconnect is customized.
- The interconnect uses predefined spaces
between rows of base cells.
- Manufacturing lead time
is between two days &
two weeks
b) Channeless Gate Array
- Also known as channel-free gate array, sea-of-
gate arrays, or SOG array.
- Only some mask layers are customized – the
interconnect.
- no predefined areas for
routing between cells.
- Route over the top of
the gate array devices.
b) Channeless Gate Array – Cont’d
- When we use an area of transistors for
routing, simply leave the transistors unused.
- The logic density – amount of logic that can be

implemented in a silicon area is higher compared
to channeled type.
- Manufacturing lead time is between two days

and two weeks
c) Structured Gate Array
- Also called Embedded Gate Array or
masterslice.
- Custom blocks (same for each design eg.
Memory) can be embedded.
3. Programmable ASICs
i) PLDs – Programmable Logic Devices are low-
density devices which contain 1k – 10 k gates and
are available both in bipolar and CMOS
technologies.
- PLDs may be programmed to a create a part
customized to a specific application.
- No customized mask layers or logic cells.
- A single large block of programmable
interconnect.
Programmable logic devices (PLD)
- The simplest programmable IC is a PROM.
- Uses fuse programming.
- ‘n’ address input can implement ‘n’ input logic
function.
Problem :-
Area efficiency.
Programmable logic devices – Cont’d
Programmable Logic Array (PLA)

- It has programmable AND logic array or
AND plane, followed by a programmable OR
logic array or OR plane.
- Sum of product form.
Problem :-
Two level programming adds
delay.
Programmable logic devices – Cont’d
Programmable Array Logic (PAL) :
- Programmable AND plane and fixed OR
plane.
- Flexible comparably.
All these PLA & PAL are Simple Programmable
Logic Devices (SPLD).
Problem :-
Logic plane structure grow rapidly as the
number of input increases.
Complex Programmable Logic Devices
(CPLD)
- To overcome the problems in SPLD.
- Programmably interconnect multiple SPLDs.
Problem:-
- high density difficult
- less flexibility.
Field Programmable Gate Array (FPGA)
- FPGA is a programmable logic device (PLD) with
higher densities and capable of implementing
different functions in a short period of time.
- Consists of 2D array of logic blocks and flip-flops
with programmable interconnections.
- Compact design.
FPGA – cont’d
FPGA – cont’d
Users can configure
- Intersections between logic blocks.
- The function of each block.
Advantages :
- FPGAs are perfect for rapid prototyping of
digital circuits.
- Mistakes not detected at design time have large
impact on development in time and cost.
FPGA – cont’d
Logic Blocks :-
- to implement combinational and sequential
logic functions.
- Logic blocks can be implemented by
multiplexers
Look up tables (LUT) – SRAM functions as
LUT in Xilinx.
wide fan-in AND – OR structure.
FPGA – cont’d
FPGA – cont’d
Programming Technologies :
- Antifuse technology
- Static RAM technology
- EPROM and EEPROM technology.
FPGAs from various vendors
Vendor/ Product Architechture Capacity Basic Cell Programming Technology

Actel Gate Array 2-8 k MUX Antifuse
QuickLogic Matrix 1.2-1.8 k MUX Antifuse
Xilinx Matrix 2-10 k RAM Block SRAM
Altera Extended PLA 1- 5 k PLA EPROM
Concurrent Matrix 3-5 k XOR, AND SRAM
Plessy SOG 2-40 k NAND SRAM
FPGA Vs ASIC
FPGA ASIC
Easy to Design Difficult to design
Short Development Time Long development time
Design Size Limited Support large designs
Design Complexity Limited Support complex designs
Performance Limited High performance
High Power Consumption Low power consumption
High Per-Unit Cost High per-unit cost.
CHIP FABRICATION
QUESTIONS & DISCUSSIONS
THANK YOU

Cmos Chip Design Options

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CMOS CHIP DESIGN

Application Specific Integrated Circuits (ASIC) :

- Controller chip for a PC or Modem.

- Both are specific to an application but are sold to

Stnadard-Cell Gate-Array based Praogrammable

- First half-dozen or so layers define

substrate tap well tap

- semi-custom ASIC's are designed to allow

-Uses predesigned logic cells (mux, flip-flops, AND gates etc)

- Standard cells are used in combination with larger

- the standard cells can be placed anywhere in the silicon.

-Predefined pattern of transistors on a gate

a) Channeled gate arrays

- The logic density – amount of logic that can be

- Manufacturing lead time is between two days

Programmable Logic Array (PLA)

Vendor/ Product Architechture Capacity Basic Cell Programming Technology

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