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 FDD8896 / FDU8896
March 2015

FDD8896 / FDU8896
N-Channel PowerTrench® MOSFET
30V, 94A, 5.7mΩ
General Description Features
This N-Channel MOSFET has been designed specifically to • rDS(ON) = 5.7mΩ, VGS = 10V, ID = 35A
improve the overall efficiency of DC/DC converters using
either synchronous or conventional switching PWM • rDS(ON) = 6.8mΩ, VGS = 4.5V, ID = 35A
controllers. It has been optimized for low gate charge, low
rDS(ON) and fast switching speed. • High performance trench technology for extremely low
rDS(ON)

• Low gate charge

Applications
• High power and current handling capability
• DC/DC converters

D
D
G
I-PAK G
S
D-PAK (TO-251AA)
TO-252
G D S S
(TO-252)

MOSFET Maximum Ratings TC = 25°C unless otherwise noted

Symbol Parameter Ratings Units
VDSS Drain to Source Voltage 30 V
VGS Gate to Source Voltage ±20 V
Drain Current
Continuous (TC = 25oC, VGS = 10V) (Note 1) 94 A
ID Continuous (TC = 25oC, VGS = 4.5V) (Note 1) 85 A
Continuous (Tamb = 25oC, VGS = 10V, with RθJA = 52oC/W) 17 A
Pulsed Figure 4 A
EAS Single Pulse Avalanche Energy (Note 2) 168 mJ
Power dissipation 80 W
PD
Derate above 25oC 0.53 W/oC
TJ, TSTG Operating and Storage Temperature -55 to 175 oC

Thermal Characteristics
o
RθJC Thermal Resistance Junction to Case TO-252, TO-251 1.88 C/W
o
RθJA Thermal Resistance Junction to Ambient TO-252, TO-251 100 C/W
RθJA Thermal Resistance Junction to Ambient TO-252, 1in2 copper pad area 52 oC/W

©2008 Fairchild Semiconductor Corporation FDD8896 / FDU8896 Rev. 1.2

 FDD8896 / FDU8896
Package Marking and Ordering Information
Device Marking Device Package Reel Size Tape Width Quantity
FDD8896 FDD8896 TO-252AA 13” 16mm 2500 units
FDU8896 FDU8896 TO-251AA Tube N/A 75 units
F

Electrical Characteristics TC = 25°C unless otherwise noted

Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 - - V
VDS = 24V - - 1
IDSS Zero Gate Voltage Drain Current µA
VGS = 0V TC = 150oC - - 250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 1.2 - 2.5 V
ID = 35A, VGS = 10V - 0.0047 0.0057
ID = 35A, VGS = 4.5V - 0.0057 0.0068
rDS(ON) Drain to Source On Resistance Ω
ID = 35A, VGS = 10V,
- 0.0075 0.0092
TJ = 175oC

Dynamic Characteristics
CISS Input Capacitance - 2525 - pF
VDS = 15V, VGS = 0V,
COSS Output Capacitance - 490 - pF
f = 1MHz
CRSS Reverse Transfer Capacitance - 300 - pF
RG Gate Resistance VGS = 0.5V, f = 1MHz - 2.1 - Ω
Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V - 46 60 nC
Qg(5) Total Gate Charge at 5V VGS = 0V to 5V - 24 32 nC
VDD = 15V
Qg(TH) Threshold Gate Charge VGS = 0V to 1V - 2.3 3.0 nC
ID = 35A
Qgs Gate to Source Gate Charge - 6.9 - nC
Ig = 1.0mA
Qgs2 Gate Charge Threshold to Plateau - 4.6 - nC
Qgd Gate to Drain “Miller” Charge - 9.8 - nC

Switching Characteristics (VGS = 10V)

tON Turn-On Time - - 171 ns
td(ON) Turn-On Delay Time - 9 - ns
tr Rise Time VDD = 15V, ID = 35A - 106 - ns
td(OFF) Turn-Off Delay Time VGS = 10V, RGS = 6.2Ω - 53 - ns
tf Fall Time - 41 - ns
tOFF Turn-Off Time - - 143 ns

Drain-Source Diode Characteristics

ISD = 35A - - 1.25 V
VSD Source to Drain Diode Voltage
ISD = 15A - - 1.0 V
trr Reverse Recovery Time ISD = 35A, dISD/dt = 100A/µs - - 27 ns
QRR Reverse Recovered Charge ISD = 35A, dISD/dt = 100A/µs - - 12 nC
Notes:
1: Package current limitation is 35A.
2: Starting TJ = 25°C, L = 0.43mH, IAS = 28A, VDD = 27V, VGS = 10V.

©2008 Fairchild Semiconductor Corporation FDD8896 / FDU8896 Rev. 1.2

 FDD8896 / FDU8896
Typical Characteristics TC = 25°C unless otherwise noted

1.2
100

CURRENT LIMITED
1.0
POWER DISSIPATION MULTIPLIER

BY PACKAGE

ID, DRAIN CURRENT (A)

75
0.8

0.6
50

0.4

25
0.2

0
0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC)
TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs Case Figure 2. Maximum Continuous Drain Current vs
Temperature Case Temperature

2
DUTY CYCLE - DESCENDING ORDER
1 0.5
0.2
0.1
0.05
THERMAL IMPEDANCE

0.02
ZθJC, NORMALIZED

0.01
PDM
0.1

t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
SINGLE PULSE PEAK TJ = PDM x ZθJC x RθJC + TC
0.01
10-5 10-4 10-3 10-2 10-1 100 101
t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance

1000
TC = 25oC
FOR TEMPERATURES
TRANSCONDUCTANCE
MAY LIMIT CURRENT ABOVE 25oC DERATE PEAK
IDM, PEAK CURRENT (A)

IN THIS REGION CURRENT AS FOLLOWS:

VGS = 4.5V
I = I25 175 - TC
150

100

30
10-5 10-4 10-3 10-2 10-1 100 101
t, PULSE WIDTH (s)

Figure 4. Peak Current Capability

©2008 Fairchild Semiconductor Corporation FDD8896 / FDU8896 Rev. 1.2

 FDD8896 / FDU8896
Typical Characteristics TC = 25°C unless otherwise noted

1000 500
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
10µs If R ≠ 0

IAS, AVALANCHE CURRENT (A)

tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100 100
ID, DRAIN CURRENT (A)

100µs
STARTING TJ = 25oC
10
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON) 10
1ms
1
10ms
SINGLE PULSE
TJ = MAX RATED DC
STARTING TJ = 150oC
TC = 25oC
0.1 1
1 10 60 0.01 0.1 1 10 100
VDS, DRAIN TO SOURCE VOLTAGE (V) tAV, TIME IN AVALANCHE (ms)

Figure 5. Forward Bias Safe Operating Area NOTE: Refer to Fairchild Application Notes AN7514 and AN7515
Figure 6. Unclamped Inductive Switching
Capability

100 100
PULSE DURATION = 80µs PULSE DURATION = 80µs VGS = 4V
DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
VDD = 15V
80 80 TC = 25oC
ID, DRAIN CURRENT (A)
ID , DRAIN CURRENT (A)

VGS = 5V
VGS = 3V
60 60

TJ = 25oC VGS = 10V

40 40

20 20
VGS = 2.5V
TJ = 175oC TJ = -55oC

0 0
1.5 2.0 2.5 3.0 3.5 0 0.2 0.4 0.6 0.8
VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)

Figure 7. Transfer Characteristics Figure 8. Saturation Characteristics

14 1.6
PULSE DURATION = 80µs PULSE DURATION = 80µs
ID = 35A DUTY CYCLE = 0.5% MAX DUTY CYCLE = 0.5% MAX
NORMALIZED DRAIN TO SOURCE

12 1.4
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)

ON RESISTANCE

10 1.2

8 1.0

6 0.8
ID = 1A

VGS = 10V, ID = 35A

4 0.6
2 4 6 8 10 -80 -40 0 40 80 120 160 200
VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC)

Figure 9. Drain to Source On Resistance vs Gate Figure 10. Normalized Drain to Source On
Voltage and Drain Current Resistance vs Junction Temperature

©2004 Fairchild Semiconductor Corporation FDD8896 / FDU8896 Rev. 1.2

 FDD8896 / FDU8896
Typical Characteristics TC = 25°C unless otherwise noted

1.2 1.2
VGS = VDS, ID = 250µA ID = 250µA

NORMALIZED DRAIN TO SOURCE

BREAKDOWN VOLTAGE
1.0
THRESHOLD VOLTAGE
NORMALIZED GATE

1.1

0.8

1.0
0.6

0.4 0.9
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC)

Figure 11. Normalized Gate Threshold Voltage vs Figure 12. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature

5000 10
CISS = CGS + CGD VDD = 15V
VGS , GATE TO SOURCE VOLTAGE (V)

8
C, CAPACITANCE (pF)

COSS ≅ CDS + CGD

1000 6

CRSS = CGD
4

WAVEFORMS IN
2 DESCENDING ORDER:
ID = 35A
VGS = 0V, f = 1MHz ID = 5A
100 0
0.1 1 10 30 0 10 20 30 40 50
VDS , DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC)

Figure 13. Capacitance vs Drain to Source Figure 14. Gate Charge Waveforms for Constant
Voltage Gate Current

©2008 Fairchild Semiconductor Corporation FDD8896 / FDU8896 Rev. 1.2

 FDD8896 / FDU8896
Test Circuits and Waveforms

VDS
BVDSS

L tP
VDS

VARY tP TO OBTAIN IAS

+
VDD
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS
0.01Ω 0

tAV

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

VDS
VDD Qg(TOT)

VDS VGS
L
VGS = 10V
VGS Qg(5)
+

VDD Qgs2
VGS = 5V
-

DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs Qgd

Ig(REF)
0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

VDS tON tOFF

td(ON) td(OFF)

RL tr tf
VDS
90% 90%

+
VGS
VDD
10% 10%
- 0

DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2008 Fairchild Semiconductor Corporation FDD8896 / FDU8896 Rev. 1.2

 FDD8896 / FDU8896
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the 125
thermal resistance of the heat dissipating path determines RθJA = 33.32+ 23.84/(0.268+Area) EQ.2
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient RθJA = 33.32+ 154/(1.73+Area) EQ.3
100
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.

RθJA (oC/W)
Equation 1 mathematically represents the relationship and
75
serves as the basis for establishing the rating of the part.

( T JM – TA )
P DM = ----------------------------- (EQ. 1) 50
Rθ JA

In using surface mount devices such as the TO-252 25

package, the environment in which it is applied will have a 0.01 0.1 1 10
significant influence on the part’s current and maximum (0.0645) (0.645) (6.45) (64.5)
power dissipation ratings. Precise determination of PDM is
complex and influenced by many factors: AREA, TOP COPPER AREA in2 (cm2)
Figure 21. Thermal Resistance vs Mounting
1. Mounting pad area onto which the device is attached and Pad Area
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using
Equation 2 or 3. Equation 2 is used for copper area defined
in inches square and equation 3 is for area in centimeters
square. The area, in square inches or square centimeters is
the top copper area including the gate and source pads.

23.84
R θ JA = 33.32 + ------------------------------------- (EQ. 2)
( 0.268 + Area )
Area in Inches Squared

154
R θ JA = 33.32 + ---------------------------------- (EQ. 3)
( 1.73 + Area )
Area in Centimeters Squared

©2008 Fairchild Semiconductor Corporation FDD8896 / FDU8896 Rev. 1.2

 FDD8896 / FDU8896
PSPICE Electrical Model
.SUBCKT FDD8896 2 1 3 ; rev July 2003

Ca 12 8 2.3e-9 LDRAIN
Cb 15 14 2.3e-9 DPLCAP 5 DRAIN
2
Cin 6 8 2.3e-9 10
RLDRAIN
RSLC1
Dbody 7 5 DbodyMOD 51 DBREAK
Dbreak 5 11 DbreakMOD RSLC2
+
Dplcap 10 5 DplcapMOD 5
ESLC 11
51
-
Ebreak 11 7 17 18 32.6 50 +
-
Eds 14 8 5 8 1 RDRAIN 17 DBODY
6 EBREAK 18
Egs 13 8 6 8 1 ESG 8
EVTHRES -
Esg 6 10 6 8 1 + 16
+ 19 - 21
Evthres 6 21 19 8 1 LGATE EVTEMP MWEAK
8
Evtemp 20 6 18 22 1 GATE RGATE +
18 - 6
1 22 MMED
9 20
It 8 17 1 RLGATE MSTRO
LSOURCE
CIN SOURCE
Lgate 1 9 4.6e-9 8 7 3
Ldrain 2 5 1.0e-9
RSOURCE
Lsource 3 7 1.7e-9 RLSOURCE
S1A S2A
RLgate 1 9 46 12 RBREAK
13 14 15
17 18
RLdrain 2 5 10 8 13
RLsource 3 7 17 S1B S2B RVTEMP
13 CB 19
Mmed 16 6 8 8 MmedMOD CA
14 IT -
+ +
Mstro 16 6 8 8 MstroMOD VBAT
EGS 6 EDS 5
Mweak 16 21 8 8 MweakMOD 8 8 +
- - 8
Rbreak 17 18 RbreakMOD 1 22
Rdrain 50 16 RdrainMOD 2.2e-3 RVTHRES
Rgate 9 20 2.1
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
Rsource 8 7 RsourceMOD 2e-3
Rvthres 22 8 RvthresMOD 1
Rvtemp 18 19 RvtempMOD 1
S1a 6 12 13 8 S1AMOD
S1b 13 12 13 8 S1BMOD
S2a 6 15 14 13 S2AMOD
S2b 13 15 14 13 S2BMOD

Vbat 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*500),10))}

.MODEL DbodyMOD D (IS=5E-12 IKF=10 N=1.01 RS=2.6e-3 TRS1=8e-4 TRS2=2e-7

+ CJO=8.8e-10 M=0.57 TT=1e-16 XTI=0.9)
.MODEL DbreakMOD D (RS=8e-2 TRS1=1e-3 TRS2=-8.9e-6)
.MODEL DplcapMOD D (CJO=9.4e-10 IS=1e-30 N=10 M=0.4)

.MODEL MmedMOD NMOS (VTO=1.85 KP=10 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=2.1 T_ABS=25)
.MODEL MstroMOD NMOS (VTO=2.34 KP=350 IS=1e-30 N=10 TOX=1 L=1u W=1u T_ABS=25)
.MODEL MweakMOD NMOS (VTO=1.55 KP=0.05 IS=1e-30 N=10 TOX=1 L=1u W=1u RG=21 RS=0.1 T_ABS=25)

.MODEL RbreakMOD RES (TC1=8.3e-4 TC2=-4e-7)

.MODEL RdrainMOD RES (TC1=1e-4 TC2=8e-6)
.MODEL RSLCMOD RES (TC1=9e-4 TC2=1e-6)
.MODEL RsourceMOD RES (TC1=7.5e-3 TC2=1e-6)
.MODEL RvthresMOD RES (TC1=-1.7e-3 TC2=-8.8e-6)
.MODEL RvtempMOD RES (TC1=-2.6e-3 TC2=2e-7)

.MODEL S1AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-4 VOFF=-3)

.MODEL S1BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-3 VOFF=-4)
.MODEL S2AMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-2 VOFF=-0.5)
.MODEL S2BMOD VSWITCH (RON=1e-5 ROFF=0.1 VON=-0.5 VOFF=-2)
.ENDS

Note: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

©2008 Fairchild Semiconductor Corporation FDD8896 / FDU8896 Rev. 1.2

 FDD8896 / FDU8896
SABER Electrical Model
rev July 2003
template FDD8896 n2,n1,n3 =m_temp
electrical n2,n1,n3
number m_temp=25
{
var i iscl
dp..model dbodymod = (isl=5e-12,ikf=10,nl=1.01,rs=2.6e-3,trs1=8e-4,trs2=2e-7,cjo=8.8e-10,m=0.57,tt=1e-16,xti=0.9)
dp..model dbreakmod = (rs=8e-2,trs1=1e-3,trs2=-8.9e-6)
dp..model dplcapmod = (cjo=9.4e-10,isl=10e-30,nl=10,m=0.4)
m..model mmedmod = (type=_n,vto=1.85,kp=10,is=1e-30, tox=1)
m..model mstrongmod = (type=_n,vto=2.34,kp=350,is=1e-30, tox=1)
m..model mweakmod = (type=_n,vto=1.55,kp=0.05,is=1e-30, tox=1,rs=0.1) LDRAIN
sw_vcsp..model s1amod = (ron=1e-5,roff=0.1,von=-4,voff=-3) DPLCAP 5 DRAIN
sw_vcsp..model s1bmod = (ron=1e-5,roff=0.1,von=-3,voff=-4) 2
10
sw_vcsp..model s2amod = (ron=1e-5,roff=0.1,von=-2,voff=-0.5) RLDRAIN
sw_vcsp..model s2bmod = (ron=1e-5,roff=0.1,von=-0.5,voff=-2) RSLC1
c.ca n12 n8 = 2.3e-9 51
RSLC2
c.cb n15 n14 = 2.3e-9
ISCL
c.cin n6 n8 = 2.3e-9
50 DBREAK
dp.dbody n7 n5 = model=dbodymod -
6 RDRAIN
dp.dbreak n5 n11 = model=dbreakmod ESG 8 11
dp.dplcap n10 n5 = model=dplcapmod EVTHRES DBODY
+ 16
+ 19 - 21
LGATE EVTEMP MWEAK
spe.ebreak n11 n7 n17 n18 = 32.6 GATE 8
RGATE + 6
spe.eds n14 n8 n5 n8 = 1 18 - EBREAK
1 22 MMED +
9 20
spe.egs n13 n8 n6 n8 = 1 MSTRO 17
RLGATE
spe.esg n6 n10 n6 n8 = 1 18 LSOURCE
spe.evthres n6 n21 n19 n8 = 1 CIN - SOURCE
8 7
spe.evtemp n20 n6 n18 n22 = 1 3
RSOURCE
RLSOURCE
i.it n8 n17 = 1
S1A S2A
12 RBREAK
13 14 15
l.lgate n1 n9 = 4.6e-9 8 13
17 18
l.ldrain n2 n5 = 1.0e-9
S1B S2B RVTEMP
l.lsource n3 n7 = 1.7e-9
13 CB 19
CA IT
+ + 14 -
res.rlgate n1 n9 = 46
6 5 VBAT
res.rldrain n2 n5 = 10 EGS EDS +
8 8
res.rlsource n3 n7 = 17 - - 8
22
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u, temp=m_temp RVTHRES
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u, temp=m_temp
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u, temp=m_temp

res.rbreak n17 n18 = 1, tc1=8.3e-4,tc2=-4e-7

res.rdrain n50 n16 = 2.2e-3, tc1=1e-4,tc2=8e-6
res.rgate n9 n20 = 2.1
res.rslc1 n5 n51 = 1e-6, tc1=9e-4,tc2=1e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 2e-3, tc1=7.5e-3,tc2=1e-6
res.rvthres n22 n8 = 1, tc1=-1.7e-3,tc2=-8.8e-6
res.rvtemp n18 n19 = 1, tc1=-2.6e-3,tc2=2e-7
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/500))** 10))

}
}

©2008 Fairchild Semiconductor Corporation FDD8896 / FDU8896 Rev. 1.2

 FDD8896 / FDU8896
PSPICE Thermal Model JUNCTION
th
REV 23 July 2003

FDD8896T

CTHERM1 TH 6 9e-4
CTHERM2 6 5 1e-3
CTHERM3 5 4 2e-3 RTHERM1 CTHERM1
CTHERM4 4 3 3e-3
CTHERM5 3 2 7e-3
CTHERM6 2 TL 8e-2
6
RTHERM1 TH 6 3.0e-2
RTHERM2 6 5 1.0e-1
RTHERM3 5 4 1.8e-1
RTHERM2 CTHERM2
RTHERM4 4 3 2.8e-1
RTHERM5 3 2 4.5e-1
RTHERM6 2 TL 4.6e-1
5
SABER Thermal Model
SABER thermal model FDD8896T
template thermal_model th tl RTHERM3 CTHERM3
thermal_c th, tl
{
ctherm.ctherm1 th 6 =9e-4
4
ctherm.ctherm2 6 5 =1e-3
ctherm.ctherm3 5 4 =2e-3
ctherm.ctherm4 4 3 =3e-3
ctherm.ctherm5 3 2 =7e-3 RTHERM4 CTHERM4
ctherm.ctherm6 2 tl =8e-2

rtherm.rtherm1 th 6 =3.0e-2
rtherm.rtherm2 6 5 =1.0e-1 3
rtherm.rtherm3 5 4 =1.8e-1
rtherm.rtherm4 4 3 =2.8e-1
rtherm.rtherm5 3 2 =4.5e-1
RTHERM5 CTHERM5
rtherm.rtherm6 2 tl =4.6e-1
}

RTHERM6 CTHERM6

tl CASE

©2008 Fairchild Semiconductor Corporation FDD8896 / FDU8896 Rev. 1.2

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