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FDD6635 35V N-Channel PowerTrench® MOSFET
March 2015
FDD6635
35V N-Channel PowerTrench® MOSFET
D
G
G
S
D-PAK
TO-252
(TO-252) S
Thermal Characteristics
RθJC Thermal Resistance, Junction-to-Case (Note 1) 2.7 °C/W
RθJA Thermal Resistance, Junction-to-Ambient (Note 1a) 40 °C/W
RθJA Thermal Resistance, Junction-to-Ambient (Note 1b) 96 °C/W
Off Characteristics(Note 2)
BVDSS Drain–Source Breakdown Voltage VGS = 0 V, ID = 250 μA 35 V
ΔBVDSS Breakdown Voltage Temperature ID = 250 μA, Referenced to 25°C
32 mV/°C
ΔTJ Coefficient
IDSS Zero Gate Voltage Drain Current VDS = 28 V, VGS = 0 V 1 μA
IGSS Gate–Body Leakage VGS = ±20 V, VDS = 0 V ±100 nA
On Characteristics (Note 2)
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250 μA 1 1.9 3 V
ΔVGS(th) Gate Threshold Voltage ID = 250 μA, Referenced to 25°C
–5 mV/°C
ΔTJ Temperature Coefficient
RDS(on) Static Drain–Source VGS = 10 V, ID = 15 A 8.2 10 mΩ
On–Resistance VGS = 4.5 V, ID = 13 A 10.2 13
VGS = 10 V, ID = 15 A, TJ=125°C 12.4 16
gFS Forward Transconductance VDS = 5 V, ID = 15 A 53 S
Dynamic Characteristics
Ciss Input Capacitance 1400 pF
VDS = 20 V, V GS = 0 V,
Coss Output Capacitance 317 pF
f = 1.0 MHz
Crss Reverse Transfer Capacitance 137 pF
RG Gate Resistance VGS = 15 mV, f = 1.0 MHz 1.4 Ω
Notes:
1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of
the drain pins. RθJC is guaranteed by design while RθCA is determined by the user's board design.
2. Pulse Test: Pulse Width < 300μs, Duty Cycle < 2.0%
PD
3. Maximum current is calculated as: R DS(ON)
where PD is maximum power dissipation at TC = 25°C and RDS(on) is at TJ(max) and VGS = 10V. Package current limitation is 21A
4. BV(avalanche) Single-Pulse rating is guaranteed if device is operated within the UIS SOA boundary of the device.
80 2.4
VGS=10V 4.0V
DRAIN-SOURCE ON-RESISTANCE
70 2.2
6.0V 4.5V
ID, DRAIN CURRENT (A)
60 2
RDS(ON), NORMALIZED
VGS = 3.5V
50 3.5V 1.8
40 1.6
4.0V
30 1.4
4.5V
20 1.2 5.0V
3.0V 6.0V
10V
10 1
0 0.8
0 0.5 1 1.5 2 2.5 3 0 10 20 30 40 50 60 70 80
VDS, DRAIN-SOURCE VOLTAGE (V) ID, DRAIN CURRENT (A)
1.8 0.029
ID = 7.5A
DRAIN-SOURCE ON-RESISTANCE
ID = 15A
RDS(ON), ON-RESISTANCE (OHM)
1.4 0.021
TA = 125oC
1.2 0.017
1 0.013
TA = 25oC
0.8 0.009
0.6 0.005
-50 -25 0 25 50 75 100 125 150 2 4 6 8 10
o
TJ, JUNCTION TEMPERATURE ( C) VGS, GATE TO SOURCE VOLTAGE (V)
80 100
VDS = 5V VGS = 0V
25oC
IS, REVERSE DRAIN CURRENT (A)
70
10
TA =-55oC
TA = 125oC
ID, DRAIN CURRENT (A)
60
125oC 1
50
25oC
40 0.1
-55oC
30 0.01
20
0.001
10
0 0.0001
1.5 2 2.5 3 3.5 4 4.5 0 0.2 0.4 0.6 0.8 1 1.2
VGS, GATE TO SOURCE VOLTAGE (V) VSD, BODY DIODE FORWARD VOLTAGE (V)
10 2000
f = 1MHz
ID = 15A VDS = 10V
VGS, GATE-SOURCE VOLTAGE (V)
15V VGS = 0 V
8 1600
CISS
CAPACITANCE (pF)
20V
6 1200
4 800
COSS
2 400
CRSS
0 0
0 5 10 15 20 25 30 0 5 10 15 20 25 30
Qg, GATE CHARGE (nC) VDS, DRAIN TO SOURCE VOLTAGE (V)
1000 100
P(pk), PEAK TRANSIENT POWER (W)
SINGLE PULSE
RDS(ON) LIMIT 100µs RθJA = 96°C/W
100 80
ID, DRAIN CURRENT (A)
TA = 25°C
1ms
10ms
10 100ms 60
1s
10s
DC
1 40
VGS = 10V
SINGLE PULSE
0.1 RθJA = 96oC/W 20
TA = 25oC
0.01 0
0.01 0.1 1 10 100 0.01 0.1 1 10 100 1000
VDS, DRAIN-SOURCE VOLTAGE (V) t1, TIME (sec)
Figure 9. Maximum Safe Operating Area Figure 10. Single Pulse Maximum
Power Dissipation
100 1000
I(pk), PEAK TRANSIENT CURRENT (A)
SINGLE PULSE
I(AS), AVALANCHE CURRENT (A)
RθJA = 96癈 /W
80 TA = 25癈
o
TJ = 25 C
100
60
40
10
20
0 1
0.1 1 10 100 1000 0.001 0.01 0.1 1 10
t1, TIME (sec) tAV, TIME IN AVANCHE(ms)
Figure 11. Single Pulse Maximum Peak Figure 12. Unclamped Inductive Switching
Current Capability
1
r(t), NORMALIZED EFFECTIVE TRANSIENT
D = 0.5
RθJA = 96 °C/W
0.1 0.1
0.05
P(pk)
0.02
t1
0.0
0.01 t2
TJ - TA = P * RθJA(t)
SINGLE PULSE Duty Cycle, D = t1 / t2
0.001
0.001 0.01 0.1 1 10 100 1000
t1, TIME (sec)
L
VDS BVDSS
tP
VGS VDS
RGEN DUT + IAS
VDD
VDD
0V -
VGS tp IAS
vary tP to obtain
required peak IAS 0.01Ω
tAV
Figure 14. Unclamped Inductive Load Test Figure 15. Unclamped Inductive Waveforms
Circuit
+ QG
50kΩ 10V
10V
- 10μF 1μF +
VDD VGS QGS QGD
-
VGS
DUT
Figure 16. Gate Charge Test Circuit Figure 17. Gate Charge Waveform
RL tON
VDS tOFF
td(ON) td(OFF)
VGS + VDS tr tf
90% 90%
RGEN DUT VDD
-
10% 10%
VGS 0V
Pulse Width ≤ 1μs
Duty Cycle ≤ 0.1% 90%
VGS
50% 50%
10%
Pulse Width
0V
Figure 18. Switching Time Test Circuit Figure 19. Switching Time Waveforms
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FDD6635