ISL9N306AP3/ISL9N306AS3ST

February 2002

ISL9N306AP3/ISL9N306AS3ST
N-Channel Logic Level PWM Optimized UltraFET® Trench Power MOSFETs
General Description Features
This device employs a new advanced trench MOSFET • Fast switching
technology and features low gate charge while maintaining
low on-resistance. • rDS(ON) = 0.0052Ω (Typ), VGS = 10V

Optimized for switching applications, this device improves • rDS(ON) = 0.0085Ω (Typ), VGS = 4.5V
the overall efficiency of DC/DC converters and allows
operation to higher switching frequencies. • Qg (Typ) = 30nC, VGS = 5V

Applications • Qgd (Typ) = 11nC

• DC/DC converters • CISS (Typ) = 3400pF

SOURCE
DRAIN DRAIN
(FLANGE) GATE

GATE
G
SOURCE DRAIN
(FLANGE) S

TO-263AB TO-220AB
MOSFET Maximum Ratings TA = 25°C unless otherwise noted
Symbol Parameter Ratings Units
VDSS Drain to Source Voltage 30 V
VGS Gate to Source Voltage ±20 V
Drain Current
Continuous (TC = 25oC, VGS = 10V) 75 A
ID Continuous (TC = 100oC, VGS = 4.5V) 61 A
Continuous (TC = 25oC, VGS = V, RθJC = 43oC/W) 18 A
Pulsed Figure 4 A
Power dissipation 125 W
PD
Derate above 25oC 0.83 W/oC
o
TJ, TSTG Operating and Storage Temperature -55 to 175 C

Thermal Characteristics
o
RθJC Thermal Resistance Junction to Case TO-220, TO-263 1.2 C/W
RθJA Thermal Resistance Junction to Ambient TO-220, TO-263 62 oC/W

RθJA Thermal Resistance Junction to Ambient TO-263, 1in2 copper pad area 43 o
C/W

Package Marking and Ordering Information

Device Marking Device Package Reel Size Tape Width Quantity
N306AS ISL9N306AS3ST TO-263AB 330mm 24mm 800 units
N306AP ISL9N306AP3 TO-220AB Tube N/A 50 units

©2002 Fairchild Semiconductor Corporation Rev. B, February 2002

 ISL9N306AP3/ISL9N306AS3ST
Electrical Characteristics TA = 25°C unless otherwise noted
Symbol Parameter Test Conditions Min Typ Max Units

Off Characteristics
BVDSS Drain to Source Breakdown Voltage ID = 250µA, VGS = 0V 30 - - V
VDS = 25V - - 1
IDSS Zero Gate Voltage Drain Current µA
VGS = 0V TC = 150o - - 250
IGSS Gate to Source Leakage Current VGS = ±20V - - ±100 nA

On Characteristics
VGS(TH) Gate to Source Threshold Voltage VGS = VDS, ID = 250µA 1 - 3 V
ID = 75A, VGS = 10V - 0.0052 0.0060
rDS(ON) Drain to Source On Resistance Ω
ID = 61A, VGS = 4.5V - 0.0085 0.0095

Dynamic Characteristics
CISS Input Capacitance - 3400 - pF
VDS = 15V, VGS = 0V,
COSS Output Capacitance - 650 - pF
f = 1MHz
CRSS Reverse Transfer Capacitance - 300 - pF
Qg(TOT) Total Gate Charge at 10V VGS = 0V to 10V 60 90 nC
Qg(5) Total Gate Charge at 5V VGS = 0V to 5V V = 15V
DD
- 30 45 nC
Qg(TH) Threshold Gate Charge VGS = 0V to 1V ID = 61A - 3.0 4.5 nC
Qgs Gate to Source Gate Charge Ig = 1.0mA - 10 - nC
Qgd Gate to Drain “Miller” Charge - 11 - nC

Switching Characteristics (VGS = 4.5V)

tON Turn-On Time - - 131 ns
td(ON) Turn-On Delay Time - 16 - ns
tr Rise Time VDD = 15V, ID = 18A - 70 - ns
td(OFF) Turn-Off Delay Time VGS = 4.5V, RGS = 4.3Ω - 34 - ns
tf Fall Time - 30 - ns
tOFF Turn-Off Time - - 97 ns

Switching Characteristics (VGS = 10V)

tON Turn-On Time - - 80 ns
td(ON) Turn-On Delay Time - 10 - ns
tr Rise Time VDD = 15V, ID = 18A - 43 - ns
td(OFF) Turn-Off Delay Time VGS = 10V, RGS = 4.3Ω - 62 - ns
tf Fall Time - 29 - ns
tOFF Turn-Off Time - - 137 ns

Unclamped Inductive Switching

tAV Avalanche Time ID = 3.6A, L = 3mH 240 - - µs

Drain-Source Diode Characteristics

ISD = 61A - - 1.25 V
VSD Source to Drain Diode Voltage
ISD = 25A - - 1.0 V
trr Reverse Recovery Time ISD = 61A, dISD/dt = 100A/µs - - 35 ns
QRR Reverse Recovered Charge ISD = 61A, dISD/dt = 100A/µs - - 30 nC

©2002 Fairchild Semiconductor Corporation Rev. B, February 2002

 ISL9N306AP3/ISL9N306AS3ST
Typical Characteristic

1.2 90

1.0
POWER DISSIPATION MULTIPLIER

75
VGS = 10V

ID, DRAIN CURRENT (A)

0.8 60
VGS = 4.5V
0.6 45

0.4 30

0.2 15

0 0
0 25 50 75 100 125 150 175 25 50 75 100 125 150 175
TC , CASE TEMPERATURE (oC) TC, CASE TEMPERATURE (oC)

Figure 1. Normalized Power Dissipation vs Figure 2. Maximum Continuous Drain Current vs

Ambient Temperature Case Temperature

2
DUTY CYCLE - DESCENDING ORDER
0.5
1 0.2
0.1
0.05
THERMAL IMPEDANCE

0.02
ZθJA, NORMALIZED

0.01

PDM
0.1

t1
t2
SINGLE PULSE NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
0.01
10-5 10-4 10-3 10-2 10-1 100 101
t, RECTANGULAR PULSE DURATION (s)

Figure 3. Normalized Maximum Transient Thermal Impedance

2000
TC = 25oC
FOR TEMPERATURES
1000 ABOVE 25oC DERATE PEAK
IDM , PEAK CURRENT (A)

CURRENT AS FOLLOWS:
I = I25 175 - TC
150
VGS = 10V

VGS = 5V

100
TRANSCONDUCTANCE
MAY LIMIT CURRENT
50 IN THIS REGION

10-5 10-4 10-3 10-2 10-1 100 101

t, PULSE WIDTH (s)

Figure 4. Peak Current Capability

©2002 Fairchild Semiconductor Corporation Rev. B, February 2002

 ISL9N306AP3/ISL9N306AS3ST
Typical Characteristic (Continued)

150 150
PULSE DURATION = 80µs TC = 25oC
DUTY CYCLE = 0.5% MAX VGS = 10V
VGS = 4.5V
VDD = 15V

ID, DRAIN CURRENT (A)

ID , DRAIN CURRENT (A)

100 100
VGS = 3.5V

50 50 VGS = 3V
TJ = 175oC

TJ = 25oC
TJ = -55oC PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
0 0
1 2 3 4 5 0 0.5 1.0 1.5 2.0
VGS , GATE TO SOURCE VOLTAGE (V) VDS , DRAIN TO SOURCE VOLTAGE (V)

Figure 5. Transfer Characteristics Figure 6. Saturation Characteristics

25 2.0
PULSE DURATION = 80µs PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX NORMALIZED DRAIN TO SOURCE DUTY CYCLE = 0.5% MAX
TC = 25oC
ID = 61A
rDS(ON), DRAIN TO SOURCE

20
ON RESISTANCE (mΩ)

ON RESISTANCE

1.5

15

1.0
ID = 30A ID = 75A
10

VGS = 10V, ID = 75A

5 0.5

2 4 6 8 10 -80 -40 0 40 80 120 160 200

VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC)

Figure 7. Drain to Source On Resistance vs Gate Figure 8. Normalized Drain to Source On

Voltage and Drain Current Resistance vs Junction Temperature

1.4 1.2
VGS = VDS, ID = 250µA ID = 250µA
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
THRESHOLD VOLTAGE
NORMALIZED GATE

1.0 1.1

0.6 1.0

0.2 0.9
-80 -40 0 40 80 120 160 200 -80 -40 0 40 80 120 160 200
TJ, JUNCTION TEMPERATURE (oC) TJ , JUNCTION TEMPERATURE (oC)

Figure 9. Normalized Gate Threshold Voltage vs Figure 10. Normalized Drain to Source
Junction Temperature Breakdown Voltage vs Junction Temperature

©2002 Fairchild Semiconductor Corporation Rev. B, February 2002

 ISL9N306AP3/ISL9N306AS3ST
Typical Characteristic (Continued)

5000 10
VDD = 15V
CISS = CGS + CGD

VGS , GATE TO SOURCE VOLTAGE (V)

8

COSS ≅ CDS + CGD

C, CAPACITANCE (pF)

1000 6

CRSS = CGD

4
WAVEFORMS IN
DESCENDING ORDER:
2 ID = 61A
ID = 25A
VGS = 0V, f = 1MHz ID = 5A
0
100
0 10 20 30 40 50 60
0.1 1 10 30
VDS , DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC)

Figure 11. Capacitance vs Drain to Source Figure 12. Gate Charge Waveforms for Constant
Voltage Gate Currents

300 500
VGS = 4.5V, VDD = 15V, ID = 18A VGS = 10V, VDD = 15V, ID = 18A

250
400
SWITCHING TIME (ns)

SWITCHING TIME (ns)

200
tf 300
tr
td(OFF)
150

200
100
tf
td(OFF)
100
50 tr
td(ON)
td(ON)
0 0
0 10 20 30 40 50 0 10 20 30 40 50
RGS, GATE TO SOURCE RESISTANCE (Ω) RGS, GATE TO SOURCE RESISTANCE (Ω)

Figure 13. Switching Time vs Gate Resistance Figure 14. Switching Time vs Gate Resistance

Test Circuits and Waveforms

VDS BVDSS

tP
VDS
L
IAS
VARY tP TO OBTAIN VDD
+
REQUIRED PEAK IAS RG
VDD
VGS -
DUT

tP
0V IAS 0
0.01Ω
tAV

Figure 15. Unclamped Energy Test Circuit Figure 16. Unclamped Energy Waveforms

©2002 Fairchild Semiconductor Corporation Rev. B, February 2002

 ISL9N306AP3/ISL9N306AS3ST
Test Circuits and Waveforms (Continued)

VDS
VDD Qg(TOT)
RL
VDS
VGS = 10V

VGS Qg(5)
+

VDD VGS VGS = 5V

-

DUT VGS = 1V

Ig(REF) 0
Qg(TH)
Qgs Qgd

Ig(REF)
0

Figure 17. Gate Charge Test Circuit Figure 18. Gate Charge Waveforms

VDS tON tOFF

td(ON) td(OFF)

RL tr tf
VDS
90% 90%

+
VGS
VDD 10% 10%
- 0

DUT 90%
RGS
VGS 50% 50%
PULSE WIDTH
VGS 10%
0

Figure 19. Switching Time Test Circuit Figure 20. Switching Time Waveforms

©2002 Fairchild Semiconductor Corporation Rev. B, February 2002

 ISL9N306AP3/ISL9N306AS3ST
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the 80
thermal resistance of the heat dissipating path determines RθJA = 26.51+ 19.84/(0.262+Area)
the maximum allowable device power dissipation, PDM, in an
application. Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
60
must be reviewed to ensure that TJM is never exceeded.

RθJA (oC/W)
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.

( T JM – T A )
(EQ. 1) 40
P
DM = ------------------------------
Z
-
θJA

In using surface mount devices such as the TO-263

package, the environment in which it is applied will have a 20
significant influence on the part’s current and maximum 0.1 1 10
power dissipation ratings. Precise determination of PDM is AREA, TOP COPPER AREA (in2)
complex and influenced by many factors: Figure 21. Thermal Resistance vs Mounting
Pad Area
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
3. The use of external heat sinks.
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 21
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.

Displayed on the curve are RθJA values listed in the

Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.

Thermal resistances corresponding to other copper areas

can be obtained from Figure 21 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a coefficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.

19.84
R θJA = 26.51 + ------------------------------------- (EQ. 2)
( 0.262 + A rea)

©2002 Fairchild Semiconductor Corporation Rev. B, February 2002

 ISL9N306AP3/ISL9N306AS3ST
PSPICE Electrical Model
.SUBCKT ISL9N306A 2 1 3 ;rev May 2001
CA 12 8 2.0e-9
CB 15 14 2.3e-9
CIN 6 8 3e-9
LDRAIN
DBODY 7 5 DBODYMOD DPLCAP 5 DRAIN
DBREAK 5 11 DBREAKMOD 2
10
DPLCAP 10 5 DPLCAPMOD RLDRAIN
RSLC1
51 DBREAK
EBREAK 11 7 17 18 35.8 +
RSLC2
EDS 14 8 5 8 1 5
EGS 13 8 6 8 1 ESLC 11
51
ESG 6 10 6 8 1
-
50 +
EVTHRES 6 21 19 8 1 -
RDRAIN 17 DBODY
EVTEMP 20 6 18 22 1 ESG
6 EBREAK 18
8
EVTHRES -
+ 16
IT 8 17 1 + 19 - 21
LGATE MWEAK
EVTEMP 8
LDRAIN 2 5 1.0e-9 GATE RGATE + 6
18 -
1 MMED
LGATE 1 9 4.58e-9 9 20
22
LSOURCE 3 7 1.47e-9 RLGATE MSTRO
LSOURCE
CIN SOURCE
MMED 16 6 8 8 MMEDMOD 8 7 3
MSTRO 16 6 8 8 MSTROMOD
RSOURCE
MWEAK 16 21 8 8 MWEAKMOD RLSOURCE
S1A S2A
RBREAK 17 18 RBREAKMOD 1 12 15
RBREAK
13 14 17 18
RDRAIN 50 16 RDRAINMOD 1e-3 8 13
RGATE 9 20 2.69
S1B S2B RVTEMP
RLDRAIN 2 5 10
13 CB 19
RLGATE 1 9 45.8 CA
14 IT -
RLSOURCE 3 7 14.7 + +
RSLC1 5 51 RSLCMOD 1e-6 6 5 VBAT
EGS EDS +
RSLC2 5 50 1e3 8 8
- - 8
RSOURCE 8 7 RSOURCEMOD 3.5e-3
22
RVTHRES 22 8 RVTHRESMOD 1 RVTHRES
RVTEMP 18 19 RVTEMPMOD 1

S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD

VBAT 22 19 DC 1

ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*275),5))}

.MODEL DBODYMOD D (IS = 3.6e-11 N=1.07 5RS = 3.5e- 3TRS1 = 1e- 3TRS2 = 1e-6 XTI=1. 0CJO = 1.45e- 9TT = 8e-11 M =
0.51)
.MODEL DBREAKMOD D (RS = 1.7e- 1TRS1 = 1e- 3TRS2 = -8.9e-6)
.MODEL DPLCAPMOD D (CJO = 11.5e-1 0IS = 1e-3 0N = 10 M = 0.46)
.MODEL MMEDMOD NMOS (VTO = 1.7 KP = 9 IS=1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 2.69)
.MODEL MSTROMOD NMOS (VTO = 2.1 KP = 100 IS = 1e-30 N= 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.36 KP = 0.05 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 26.9 RS = .1)
.MODEL RBREAKMOD RES (TC1 = 1e- 3TC2 = -7e-7)
.MODEL RDRAINMOD RES (TC1 = 1.2e- 2TC2 = 3.0e-5)
.MODEL RSLCMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2.6e-3 TC2 = -7.5e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.8e- 3TC2 = 1e-6)

.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.0 VOFF= -0.8)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.8 VOFF= -4.0)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.3 VOFF= 0.2)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.2 VOFF= -0.3)

.ENDS

NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank
Wheatley.

©2002 Fairchild Semiconductor Corporation Rev. B, February 2002

 ISL9N306AP3/ISL9N306AS3ST
SABER Electrical Model
REV May 2001
template ISL9N306A n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (isl = 3.6e-11, nl=1.075 , rs = 3.5e-3, trs1 = 1e-3, trs2 = 1e-6, xti=1.0, cjo = 1.45e-9, tt = 8e-11, m = 0.51,)
dp..model dbreakmod = (rs =0.17, trs1 = 1e-3, trs2 = -8.9e-6)
dp..model dplcapmod = (cjo = 11.5e-10, isl=10e-30, nl=10, m=0.46)
m..model mmedmod = (type=_n, vto = 1.7, kp=9, is=1e-30, tox=1)
m..model mstrongmod = (type=_n, vto = 2.1, kp = 100, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.36, kp = 0.05, is = 1e-30, tox = 1, rs=0.1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.0, voff = -0.8)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -0.8, voff = -4.0)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.3, voff = 0.2) LDRAIN
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.2, voff = -0.3) DPLCAP 5 DRAIN
2
10
c.ca n12 n8 = 2.0e-9 RLDRAIN
c.cb n15 n14 = 2.3e-9 RSLC1
c.cin n6 n8 = 3e-9 51
RSLC2
ISCL
dp.dbody n7 n5 = model=dbodymod
dp.dbreak n5 n11 = model=dbreakmod 50 DBREAK
dp.dplcap n10 n5 = model=dplcapmod -
6 RDRAIN
ESG 11
8
i.it n8 n17 = 1 + EVTHRES 16
DBODY
+ 19 - 21
LGATE EVTEMP MWEAK
l.ldrain n2 n5 = 1e-9 8
GATE RGATE +
l.lgate n1 n9 = 4.58e-9 18 - 6
MMED EBREAK
1 22 +
l.lsource n3 n7 = 1.47e-9 9 20
RLGATE MSTRO 17
18
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u CIN -
LSOURCE
SOURCE
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u 8 7 3
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u RSOURCE
RLSOURCE
res.rbreak n17 n18 = 1, tc1 = 1e-3, tc2 = -7e-7 S1A S2A
res.rdrain n50 n16 = 1e-3, tc1 = 1.2e-2, tc2 = 3.0e-5 12 RBREAK
13 14 15
17 18
res.rgate n9 n20 = 2.69 8 13
res.rldrain n2 n5 = 10 S1B S2B RVTEMP
res.rlgate n1 n9 = 45.8 13 CB 19
res.rlsource n3 n7 = 14.7 CA
14 IT -
res.rslc1 n5 n51= 1e-6, tc1 = 1e-3, tc2 =1e-6 + +
6 5 VBAT
res.rslc2 n5 n50 = 1e3 EGS EDS +
8 8
res.rsource n8 n7 = 3.5e-3, tc1 = 1e-3, tc2 =1e-6 - - 8
res.rvtemp n18 n19 = 1, tc1 = -1.8e-3, tc2 = -1e-6 22
res.rvthres n22 n8 = 1, tc1 = -2.6e-3, tc2 = -7.5e-6 RVTHRES

spe.ebreak n11 n7 n17 n18 = 35.8

spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1

sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod

sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod

v.vbat n22 n19 = dc=1

equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e-6/275))** 5))
}
}

©2002 Fairchild Semiconductor Corporation Rev. B, February 2002

 ISL9N306AP3/ISL9N306AS3ST
SPICE Thermal Model JUNCTION
th
REV May 2001

ISL9N306AT

CTHERM1 th 6 2.7e-4
CTHERM2 6 5 3.9e-3
RTHERM1 CTHERM1
CTHERM3 5 4 4.2e-3
CTHERM4 4 3 4.8e-3
CTHERM5 3 2 1.9e-2
CTHERM6 2 tl 5.9e-2 6

RTHERM1 th 6 1.0e-3
RTHERM2 6 5 4.8e-3
RTHERM3 5 4 4.5e-2 RTHERM2 CTHERM2
RTHERM4 4 3 2.6e-1
RTHERM5 3 2 3.1e-1
RTHERM6 2 tl 3.4e-1
5

SABER Thermal Model RTHERM3 CTHERM3

SABER thermal model ISL9N306AT

template thermal_model th tl 4
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 2.7e-4
ctherm.ctherm2 6 5 = 3.9e-3 RTHERM4 CTHERM4
ctherm.ctherm3 5 4 = 4.2e-3
ctherm.ctherm4 4 3 = 4.8e-3
ctherm.ctherm5 3 2 = 1.9e-2
ctherm.ctherm6 2 tl = 5.9e-2 3

rtherm.rtherm1 th 6 = 1.0e-3
rtherm.rtherm2 6 5 = 4.8e-3 RTHERM5 CTHERM5
rtherm.rtherm3 5 4 = 4.5e-2
rtherm.rtherm4 4 3 = 2.6e-1
rtherm.rtherm5 3 2 = 3.1e-1
rtherm.rtherm6 2 tl = 3.4e-1 2
}

RTHERM6 CTHERM6

tl CASE

©2002 Fairchild Semiconductor Corporation Rev. B, February 2002

TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is
not intended to be an exhaustive list of all such trademarks.
ACEx™ FAST  OPTOLOGIC™ SMART START™ VCX™
Bottomless™ FASTr™ OPTOPLANAR™ STAR*POWER™
CoolFET™ FRFET™ PACMAN™ Stealth™
CROSSVOLT™ GlobalOptoisolator™ POP™ SuperSOT™-3
DenseTrench™ GTO™ Power247™ SuperSOT™-6
DOME™ HiSeC™ PowerTrench  SuperSOT™-8
EcoSPARK™ ISOPLANAR™ QFET™ SyncFET™
E2CMOSTM LittleFET™ QS™ TinyLogic™
EnSignaTM MicroFET™ QT Optoelectronics™ TruTranslation™
FACT™ MicroPak™ Quiet Series™ UHC™
FACT Quiet Series™ MICROWIRE™ SILENT SWITCHER  UltraFET 
STAR*POWER is used under license
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FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER

NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD
DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT
OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT
RIGHTS, NOR THE RIGHTS OF OTHERS.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or 2. A critical component is any component of a life
systems which, (a) are intended for surgical implant into support device or system whose failure to perform can
the body, or (b) support or sustain life, or (c) whose be reasonably expected to cause the failure of the life
failure to perform when properly used in accordance support device or system, or to affect its safety or
with instructions for use provided in the labeling, can be effectiveness.
reasonably expected to result in significant injury to the
user.
PRODUCT STATUS DEFINITIONS
Definition of Terms

Datasheet Identification Product Status Definition

Advance Information Formative or This datasheet contains the design specifications for
In Design product development. Specifications may change in
any manner without notice.

Preliminary First Production This datasheet contains preliminary data, and

supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.

No Identification Needed Full Production This datasheet contains final specifications. Fairchild
Semiconductor reserves the right to make changes at
any time without notice in order to improve design.

Obsolete Not In Production This datasheet contains specifications on a product

that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.

Rev. H4
This datasheet has been download from:

www.datasheetcatalog.com

Datasheets for electronics components.