STP40NF10L

N-CHANNEL 100V - 0.028Ω - 40A TO-220

LOW GATE CHARGE STripFET™ POWER MOSFET

TYPE VDSS RDS(on) ID

STP40NF10L 100 V < 0.033 Ω 40 A

■ TYPICAL RDS(on) = 0.028Ω
■ EXCEPTIONAL dv/dt CAPABILITY
■ 100% AVALANCHE TESTED
■ APPLICATION ORIENTED 3
2
CHARACTERIZATION 1

TO-220
DESCRIPTION
This Power Mosfet series realized with STMicro-
electronics unique STripFET process has specifical-
ly been designed to minimize input capacitance and
gate charge. It is therefore suitable as primary INTERNAL SCHEMATIC DIAGRAM
switch in advanced high-efficiency isolated DC-DC
converters for Telecom and Computer application. It
is also intended for any application with low gate
charge drive requirements.

APPLICATIONS
■ HIGH-EFFICIENCY DC-DC CONVERTERS

■ UPS AND MOTOR CONTROL

■ AUTOMOTIVE

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit
VDS Drain-source Voltage (VGS = 0) 100 V
VDGR Drain-gate Voltage (RGS = 20 kΩ) 100 V
VGS Gate- source Voltage ± 17 V
ID Drain Current (continuos) at TC = 25°C 40 A
ID Drain Current (continuos) at TC = 100°C 25 A
IDM (l) Drain Current (pulsed) 160 A
PTOT Total Dissipation at TC = 25°C 150 W
Derating Factor 1 W/°C
EAS (1) Single Pulse Avalanche Energy 430 mJ
Tstg Storage Temperature –65 to 175 °C
Tj Max. Operating Junction Temperature 175 °C
(●) Pulse width limited by safe operating area
(1) Starting T j = 25°C, I D = 20A, VDD = 40V

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STP40NF10L

THERMAL DATA
Rthj-case Thermal Resistance Junction-case Max 1 °C/W
Rthj-amb Thermal Resistance Junction-ambient Max 62.5 °C/W
Tl Maximum Lead Temperature For Soldering Purpose 300 °C

ELECTRICAL CHARACTERISTICS (TCASE = 25 °C UNLESS OTHERWISE SPECIFIED)

OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
V(BR)DSS Drain-source ID = 250 µA, VGS = 0 100 V
Breakdown Voltage
IDSS Zero Gate Voltage VDS = Max Rating 1 µA
Drain Current (VGS = 0)
VDS = Max Rating, TC = 125 °C 10 µA
IGSS Gate-body Leakage VGS = ± 17V ±100 nA
Current (VDS = 0)

ON (1)
Symbol Parameter Test Conditions Min. Typ. Max. Unit
VGS(th) Gate Threshold Voltage VDS = VGS, ID = 250µA 1 1.7 2.5 V
RDS(on) Static Drain-source On VGS = 10V, ID = 20 A 0.028 0.033 Ω
Resistance
VGS = 5V, ID = 20 A 0.030 0.036 Ω

DYNAMIC
Symbol Parameter Test Conditions Min. Typ. Max. Unit
gfs (1) Forward Transconductance VDS = 15V, ID = 20 A 25 S
Ciss Input Capacitance VDS = 25V, f = 1 MHz, VGS = 0 2300 pF
Coss Output Capacitance 290 pF
Crss Reverse Transfer 125 pF
Capacitance

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 STP40NF10L

ELECTRICAL CHARACTERISTICS (CONTINUED)

SWITCHING ON
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(on) Turn-on Delay Time VDD = 50 V, ID = 20 A 25 ns
RG = 4.7Ω VGS = 4.5V
tr Rise Time (see test circuit, Figure 3) 82 ns

Qg Total Gate Charge VDD = 80V, ID =40A,VGS = 5V 46 64 nC

Qgs Gate-Source Charge 12 nC
Qgd Gate-Drain Charge 22 nC

SWITCHING OFF
Symbol Parameter Test Conditions Min. Typ. Max. Unit
td(off) Turn-off-Delay Time VDD = 50 V, ID = 20 A, 64 ns
tf Fall Time RG = 4.7Ω, VGS = 4.5V 24 ns
(see test circuit, Figure 3)
td(off) Off-voltage Rise Time Vclamp =80V, ID = 40 A 51 ns
tf Fall Time RG = 4.7Ω, VGS = 4.5V 29 ns
tc Cross-over Time (see test circuit, Figure 3) 53 ns

SOURCE DRAIN DIODE

Symbol Parameter Test Conditions Min. Typ. Max. Unit
ISD Source-drain Current 40 A
ISDM (1) Source-drain Current (pulsed) 160 A
VSD (2) Forward On Voltage ISD = 40 A, VGS = 0 1.3 V
trr Reverse Recovery Time ISD = 40 A, di/dt = 100A/µs, 110 ns
Qrr Reverse Recovery Charge VDD = 30V, Tj = 150°C 467 nC
IRRM Reverse Recovery Current (see test circuit, Figure 5) 8 A
Note: 1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %.
2. Pulse width limited by safe operating area.

Safe Operating Area Thermal Impedance

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STP40NF10L

Output Characteristics Transfer Characteristics

Transconductance Static Drain-source On Resistance

Gate Charge vs Gate-source Voltage Capacitance Variations

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 STP40NF10L

Normalized Gate Threshold Voltage vs Normalized On Resistance vs Temperature

Temperature

Source-drain Diode Forward Characteristics Normalized Drain-Source Breakdown vs

Temperature

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STP40NF10L

Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform

Fig. 3: Switching Times Test Circuit For Fig. 4: Gate Charge test Circuit
Resistive Load

Fig. 5: Test Circuit For Inductive Load Switching

And Diode Recovery Times

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 STP40NF10L

TO-220 MECHANICAL DATA

mm inch
DIM.
MIN. TYP. MAX. MIN. TYP. MAX.
A 4.40 4.60 0.173 0.181
C 1.23 1.32 0.048 0.051
D 2.40 2.72 0.094 0.107
D1 1.27 0.050
E 0.49 0.70 0.019 0.027
F 0.61 0.88 0.024 0.034
F1 1.14 1.70 0.044 0.067
F2 1.14 1.70 0.044 0.067
G 4.95 5.15 0.194 0.203
G1 2.4 2.7 0.094 0.106
H2 10.0 10.40 0.393 0.409
L2 16.4 0.645
L4 13.0 14.0 0.511 0.551
L5 2.65 2.95 0.104 0.116
L6 15.25 15.75 0.600 0.620
L7 6.2 6.6 0.244 0.260
L9 3.5 3.93 0.137 0.154
DIA. 3.75 3.85 0.147 0.151

E
A

D
C

D1

L2
F1

G1

H2
G

Dia.
F
F2

L5
L9
L7
L6 L4
P011C

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STP40NF10L

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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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