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    ES333 Tut5

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    AJAY MEENA 17110007
    1) The Wakeup Interrupt Controller handles waking the CPU from low power modes and affects interrupt handling by prioritizing wakeup events. 2) Level-sensitive interrupts trigger on a signal level while pulse/edge interrupts trigger on a signal transition. Level interrupts can cause priority inversion issues. 3) An interrupt becomes "pending" when its enable bit is set and the interrupt condition is met. 4) Interrupt processing involves saving context, switching to handler mode using a different stack, loading the PC with the handler address, and starting code execution.

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    ES333 Tut5

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    AJAY MEENA 17110007
    96 views2 pages
    1) The Wakeup Interrupt Controller handles waking the CPU from low power modes and affects interrupt handling by prioritizing wakeup events. 2) Level-sensitive interrupts trigger on a signal level while pulse/edge interrupts trigger on a signal transition. Level interrupts can cause priority inversion issues. 3) An interrupt becomes "pending" when its enable bit is set and the interrupt condition is met. 4) Interrupt processing involves saving context, switching to handler mode using a different stack, loading the PC with the handler address, and starting code execution.

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    1) The Wakeup Interrupt Controller handles waking the CPU from low power modes and affects interrupt handling by prioritizing wakeup events. 2) Level-sensitive interrupts trigger on a signal level while pulse/edge interrupts trigger on a signal transition. Level interrupts can cause priority inversion issues. 3) An interrupt becomes "pending" when its enable bit is set and the interrupt condition is met. 4) Interrupt processing involves saving context, switching to handler mode using a different stack, loading the PC with the handler address, and starting code execution.

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    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
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    96 views2 pages

    ES333 Tut5

    Uploaded by

    AJAY MEENA 17110007
    1) The Wakeup Interrupt Controller handles waking the CPU from low power modes and affects interrupt handling by prioritizing wakeup events. 2) Level-sensitive interrupts trigger on a signal level while pulse/edge interrupts trigger on a signal transition. Level interrupts can cause priority inversion issues. 3) An interrupt becomes "pending" when its enable bit is set and the interrupt condition is met. 4) Interrupt processing involves saving context, switching to handler mode using a different stack, loading the PC with the handler address, and starting code execution.

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    of 2

    ES 333 Microprocessors and Embedded Systems

    Tutorial - 5
    Tutorial on Interrupts
    12.4.2019
    Reference Manual:
    http://infocenter.arm.com/help/topic/com.arm.doc.dui0497a/DUI0497A_cortex_m0_r0p0
    _generic_ug.pdf

    1. Mention the function of Wakeup Interrupt Controller and how does it affect how
    interrupts are handled in ARM.
    2. Compare level and pulse (or edge) sensitive interrupts. What are the issues with level-
    sensitive interrupts?
    3. When does an interrupt become “pending?”
    4. Interrupt processing happens in the following steps:

    i. Finish current instruction (except for lengthy instructions)


    ii. Push context (8 32-bit words) onto current stack (MSP or PSP)
    a. Context:
    ____________________________________________________________
    iii. Switch to _______ mode, use _____ stack pointer.
    iv. Load PC with address of __________________.
    v. Load ____ with EXC_RETURN code
    vi. Load IPSR with exception number
    vii. Start executing code of exception handler

    5. What happens if the (asynchronous) interrupt occurs when LDM (or MULS) instruction
    was being executed?

    6. What value is stored in the LR register when the processor enters in to the handler
    mode?

    7. We would like to configure a KL25Z MCU so that if interrupts IRQ0, IRQ10 and
    IRQ31 are requested simultaneously, the CPU responds by servicing IRQ10 first, then
    IRQ0, and finally IRQ31. Write the C code using CMSIS functions to configure the
    MCU.

    8. We wish to enable IRQ13 but disable IRQ24. What value needs to be loaded into which
    register bits, and what is the CMSIS code call to accomplish the same?

    9. Consider the code below. The code below clears the status flags for all bits in Port D’s
    interrupt status flag register. Under what circumstances might this lead to incorrect
    system operation.
    void PORTD_IRQHandler(void) {

    // Read switches

    if ((PORTD->ISFR & MASK(SW1_POS))) {


    if (SWITCH_PRESSED(SW1_POS)) { // flash white
    g_flash_LED = 1;
    } else {
    g_flash_LED = 0;
    }
    }

    if ((PORTD->ISFR & MASK(SW2_POS))) {


    if (SWITCH_PRESSED(SW2_POS)) { // short delays
    g_w_delay = 200;
    g_RGB_delay = 1000;
    } else {
    g_w_delay = 400;
    g_RGB_delay = 4000;
    }

    // clear status flags


    PORTD->ISFR = 0xffffffff;
    }

    10. [To be submitted online, will be graded] Consider the schematic shown below.

    Write a code which executes an ISR when the switch is pressed. In the main program
    all the LED blinks together, but in ISR LEDs follow a pattern: R-> G-> B . Write
    both main and ISR.

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