RN SHETTY TRUST

RNS INSTITUTE OF TECHNOLOGY

(AICTE Approved, VTU Affiliated and NAAC ‘A’ Accredited)
(UG programs - CSE, ECE, ISE, EIE and EEE have been accredited by NBA
For the Academic Years 2018-19, 2019-20 and 2020-21)
Channasandra, Dr.Vishnuvardhan Road, Bangalore 560098

Subject: ARM Microcontroller and Embedded Systems (17EC62)

Semester: 6TH

MODULE 3
Embedded System Components: Embedded Vs General computing system,
Classification of Embedded systems, Major applications and purpose of ES. Core of an
Embedded System including all types of processor/controller, Memory, Sensors,
Actuators, LED, 7 segment LED display, Optocoupler, relay, Piezo buzzer, Push
button switch, Communication Interface (onboard and external types), Embedded
firmware, Other system components. (Text 2: All the Topics from Ch-1 and Ch-2,
excluding 2.3.3.4 (stepper motor), 2.3.3.8 (keyboard) and 2.3.3.9 (PPI) sections).

“life is an embedded system designed by God and our brains are the neural
networks surrounded by neurons each neuron has its individual function but they
are controlled by microcontroller IC's called our minds :)”

Text Books:
1. Shibu K V, “Introduction to Embedded Systems”, Tata McGraw Hill
Education Private Limited, 2009.
By,
Geetha G
Asst Professor, ECE
RNSIT
The Typical Embedded System

Fig 1: Elements of an Embedded System

 A typical embedded system as shown in Fig 1, contains a single chip controller, which acts as the
master brain of the system.
 The controller can be a Microprocessor (e.g. Intel 8085) or a microcontroller (e.g. Atmel
AT89C51) or a Field Programmable Gate Array (FPGA) device (e.g. Xilinx Spartan) or a
Digital Signal Processor (DSP) (e.g. Blackfin® Processors from Analog Devices) or an
Application Specific Integrated Circuit (ASIC)/Application Specific Standard Product (ASSP)
(ex: ADE7760 Single Phase Energy Metering IC from Analog Devices for energy metering
applications).
 Embedded hardware/software systems are basically designed to regulate a physical variable or
to manipulate the state of some devices by sending some control signals to the actuators or
devices connected to the o/p ports of the system in response to the input signals provided by the
end users or sensors which are connected to the input ports.
 Hence an embedded system can be viewed as a reactive system.
 The control is achieved by processing the information coming from the sensors and user
interfaces and controlling some actuators that regulate the physical variable.
 Key boards, push button switches etc are examples for common user interface input devices
whereas LEDs, liquid crystal displays, piezoelectric buzzers, etc are examples for common user
interface output devices for a typical embedded system.
 It should be noted that it is not necessary that all embedded systems should incorporate these 1/O
user interfaces.
 It solely depends on the type of the application for which the embedded system is designed.
 For example, if the embedded system is designed for any handheld application, such as a mobile
handset application, then the system should contain user interfaces like a keyboard for performing
input operations and display unit for providing users the status of various activities in progress.
 Some embedded systems do not require any manual intervention for their operation.
 They automatically sense the variations in the input parameters in accordance with the changes in
the real world, to which they are interacting through the sensors which are connected to the input
port of the system.
 The sensor information is passed to the processor after signal conditioning and digitization.
 Upon receiving the sensor data this processor or brain of the embedded system performs some
pre-defined operations with the help of the firmware embedded in the system and sends some
actuating signals to the actuator connected to the output port of the embedded system, which in
turn acts on the controlling variable to bring the controlled variable to the desired level to make
the embedded system work in the desired manner.
 The Memory of the system is responsible for holding the control algorithm and other important
configuration details.
 For most of embedded systems, the memory for storing the algorithm or configuration data is of
fixed type, which is a kind of Read Only Memory (ROM) and it is not available for the end user
for modifications, which means the memory is protected from unwanted user interaction by
implementing some kind of memory protection mechanism.
 The most common types of memories used in embedded systems for control algorithm storage
are OTP, PROM, UVEPROM, EEPROM and FLASH.
 Depending on the control application, the memory size may vary from a few bytes to megabytes.
 Sometimes the system requires temporary memory for performing arithmetic operations or
control algorithm execution and this type of memory is known as working memory.
 Random Access Memory (RAM) is used in most of the systems as the working memory.
 Various types of RAM like SRAM, DRAM and NVRAM are used for this purpose.
 The size of the RAM also varies from a few bytes to kilobytes or megabytes depending on the
application.
 The details given under the section “Memory” will give you a more detailed description of the
working memory.
 An embedded system without a control algorithm implemented memory is just like a new born
baby.
 It is having all the peripherals but is not capable of making any decision depending on the
situational as well as real world changes.
 The only difference is that the memory of a new born baby is self-adaptive, meaning that the
baby will try to learn from the surroundings and from the mistakes committed.
 For embedded systems it is the responsibility of the designer to impart intelligence to the system.
 In a controller-based embedded system, the controller may contain internal memory for storing
the control algorithm and it may be an EEPROM or FLASH memory varying from a few
kilobytes to megabytes.
 Such controllers are called controllers with on-chip ROM, e. g. Atmel AT89C51.
 Some controllers may not contain on-chip memory and they require an external (off-chip)
memory for holding the control algorithm, e. g. Intel 8031AH.
3.1 CORE OF THE EMBEDDED SYSTEM
 Embedded systems are domain and application specific and are built around a central core.
 The core of the embedded system falls into any one of the following categories:
1. General Purpose and Domain Specific Processor
1.1 Microprocessors
1.2 Microcontrollers
1.3 Digital Signal Processors (DSPs)
2. Application Specific Integrated Circuits (ASICs)
3. Programmable Logic Devices (PLDs)
4. Commercial off-the-shelf Components (COTS)
 If any of the embedded system is examined, will find that it is built around any of the core units
mentioned above.

3.1.1 General Purpose and Domain Specific Processors

 Almost 80% of the embedded systems are processor/controller based.
 The processor may be a microprocessor or a microcontroller or a Digital Signal Processor,
depending on the domain and application.
 Most of the embedded systems in the industrial control and monitoring applications make use of
the commonly available microprocessors or microcontrollers whereas domains which require
signal processing such as speech coding, speech recognition, etc make use of special kind of
Digital Signal Processors supplied by manufacturers like, Analog Devices, Texas Instruments,
etc.

3.1.1.1 Microprocessors
 Microprocessor is a silicon chip representing a Central Processing Unit (CPU), which is
capable of performing arithmetic as well as logical operations according to a predefined set of
instructions, which is specific to the manufacturer.
 In general the CPU contains the Arithmetic and Logic Unit (ALU), Control Unit and working
registers.
 A microprocessor is a dependent unit and it requires the combination of other hardware like
memory, timer unit, and interrupt controller, etc., for proper functioning.
 Intel claims the credit for developing the first microprocessor unit i.e Intel 4004, 4 bit processor
which was released in November 1971.
- It featured 1K data memory, a 12 bit program counter and 4K program memory, sixteen 4bit
general purpose registers and 46 instructions.
- It ran at a clock speed of 740 kHz. It was designed for olden day’s calculators.
 In 1972, Intel 4040 was released
- 14 more instructions were added to the 4004 instruction set and the program space is
upgraded to 8K.
- Also interrupt capabilities were added to it
 It was quickly replaced in April 1972 by Intel 8008 which was similar to Intel 4040, the only
difference was that its program counter was 14 bits wide and the 8008 served as a terminal
controller.
 In April 1974 Intel launched the first 8 bit processor, the Intel 8080, with 16 bit address bus and
program counter and seven 8 bit registers (A-E,H,L: BC, DE, and HL pairs formed the 16bit
register for this processor).
- Intel 8080 was the most commonly used processors for industrial control and other embedded
applications in the 1975s.
- Since the processor required other hardware components as mentioned earlier for its proper
functioning, the systems made out of it were bulky and were lacking compactness.
 Immediately after the release of Intel 8080, Motorola also entered the market with their
processor, Motorola 6800 with a different architecture and instruction set compared to 8080.
 In 1976 Intel came up with the upgraded version of 8080 Intel 8085, with two newly added
instructions, three interrupt pins and serial I/O.
- Clock generator and bus controller circuits were built-in and the power supply part was
modified to a single +5 V supply.
 In July 1976 Zilog entered the microprocessor market with its Z80 processor as competitor to
Intel.
- Actually it was designed by an ex-intel designer, Frederico Faggin and it was an improved
version of Intel’s 8080 processor, maintaining the original 8080 architecture and instruction
set with an 8 bit data bus and a 16 bit address bus and was capable of executing all
instructions of 8080.
- It included 80 more new instructions and it brought out the concept of register banking by
doubling the register set. Z80 also included two sets of index registers for flexible design.
 Technical advances in the field of semiconductor industry brought a new dimension to the
microprocessor market and twentieth century witnessed a fast growth in processor technology.
 16, 32 and 64 bit processors came into the place of conventional 8 bit processors.
 The initial 2 MHz clock is now an old story.
 Today processors with clock speeds up to 2.4 GHz are available in the market.
 More and more competitors entered into the processor market offering high speed, high
performance and low cost processors for customer design needs.
 Intel, AMD, Freescale, IBM, TI, Cyrix, Hitachi, NBC, LSI Logic etc are the key players in the
processor market.
 Intel still leads the market with cutting edge technologies in the processor industry.
 Different instruction set and system architecture are available for the design of a microprocessor.
 Harvard and Von-Neumann are the two common system architectures for processor design.
 Processors based on Harvard architecture contains separate buses for program memory and data
memory, whereas processors based on Von-Neumann architecture shares a single system bus for
program and data memory.
 Reduced Instruction Set Computing (RISC) and Complex Instruction Set Computing (CISC) are
the two common Instruction Set Architectures (ISA) available for processor design.

3.1.1.2 General Purpose Processor (GPP) vs. Application-Specific Instruction Set

Processor (ASIP)
 A General Purpose Processor or GPP is a processor designed for general computational tasks.
 The processor running inside laptops or desktops (Pentium MAME Athlon, etc.) is a typical
example for general purpose processor.
 They are produced in large volumes and targeting the general market.
 Due to the high volume production, the per unit cost for a chip is low compared to ASIC or other
specific ICs.
 A typical general purpose processor contains an Arithmetic and Logic Unit (ALU) and Control
Unit (CU).
 On the other hand, Application Specific Instruction Set Processors (ASIPs) are processors with
architecture and instruction set optimized to specific-domain/application requirements like
network processing, automotive, telecom, media applications, Digital Signal Processing, control
applications, etc.
 ASIPs fill the architectural spectrum between GPP and ASICs.
 The need for an ASIP arises when the traditional General Purpose Processor are unable to meet
the increasing application needs.
 Most of the embedded systems are built around Application Specific Instruction Set Processors.
 Ex of ASIP: Some microcontrollers (like automotive AVR, USB AVR from Atmel), system on
chips, Digital Signal Processors etc.
 ASIPs incorporate a processor and on-chip peripherals, demanded by the application
requirement, program and data memory.

3.1.1. 3 Microcontrollers
 A Microcontroller is a highly integrated chip that contains a CPU, scratch pad RAM, special and
general purpose register arrays, on chip ROM/FLASH memory for program storage, timer and
interrupt control units and dedicated I/O ports.
 Microcontrollers can be considered as a super set of microprocessors.
 Since a microcontroller contains all the necessary functional blocks for independent working,
they found greater place in the embedded domain in place of microprocessors.
 Apart from this, they are cheap, cost effective and are readily available in the market.
 Texas Instrument’s TMS 1000 is considered as the world’s first microcontroller.
 We cannot say it as a fully functional microcontroller when we compare it with modern
microcontrollers.
 TI followed Intel’s 4004/4040, 4 bit processor design and added some amount of RAM, program
storage memory (ROM) and support on a single chip, there by eliminated the requirement of
multiple hardware chips for self-functioning.
 Provision to add custom instructions to the CPU was another innovative feature of TMS 1000.
 TMS 1000 was released in 1974.
 In 1977 Intel entered the microcontroller market with a family of controllers coming under one
umbrella named MCS-48TM family.
- The processors came under this family were 8038HL, 8039HL, 8040AHL, 8048H, 8049H
and 8050AH. Intel 8048 is recognized as Intel’s first microcontroller and it was the most
prominent member in the MCS-48TMT family.
- It was used in the original IBM PC keyboard.
 The inspiration behind 8048 was Fairchild’s F8 microprocessor and Intel’s goal of developing a
low cost and small size processor.
- The design of 8048 adopted a true Harvard architecture where program and data memory
shared the same address bus and is differentiated by the related control signals.
 Eventually Intel came out with its most fruitful design in the 8bit microcontroller domain-the
8051 family and its derivatives.
- It is the most popular and powerful 8 bit microcontroller ever built.
- It was developed in the 1980s and was put under the family MCS-51.
- Almost 75% of the microcontroller used in the embedded domain were 8051 family based
controllers during the 1980-90s.
- 8051 processor cores are used in more than 100 devices by more than 20 independent
manufacturers like Maxim, Philips, Atmel, etc under the license from Intel.
- Due to the low cost, wide availability, memory efficient instruction set, mature development
tools and Boolean processing or bit manipulation operation capability, 8051 family
derivative microcontrollers are much used in high-volume consumer electronic devices,
entertainment industry and other gadgets where cost-cutting is essential.
 Another important family of microcontrollers used in industrial control and embedded
applications is the PIC family micro controllers from Microchip Technologies.
- It is a high performance RISC microcontroller complementing the CISC (Complex Instruction
Set Computing) features of 8051.
- The terms RISC and CISC will be explained in detail in a separate heading.
 Some embedded system applications require only 8 bit controllers whereas some embedded
applications requiring superior performance and computational needs demand l6/32bit
microcontrollers.
 Infineon, Freescale, Philips, Atmel, Maxim, Microchip etc are the key suppliers of 16bit
microcontrollers.
 Philips tried to extend the 8051 family microcontrollers to use for 16 bit applications by
developing the Philips XA (extended Architecture) microcontroller series.
 8 bit microcontrollers are commonly used in embedded systems where the processing power is
not a big constraint.
 The companies tried to add more and more functionalities like built in SPI, I2C serial buses,
USB controller, ADC, Networking capability etc to 8051.
 So the competitive market is driving towards a one-stop solution chip in microcontroller domain.
 High processing speed microcontroller families like ARM11 series are also available in the
market, which provides solution to applications requiring hardware acceleration and high
processing capability.
 Freescale, NBC, Zilog, Hitachi, Mitsubishi, Infineon, ST Micro Electronics, National, Texas
Instruments, Toshiba, Philips, Microchip, Analog Devices, Daewoo, Intel, Maxim, Sharp, Silicon
Laboratories, TDK, Triscend, Winbond, Atmel, etc. are the key players in the microcontroller
market.
 Of these Atmel has got special significance.
 They are the manufacturers of a variety of Flash memory based microcontrollers.
 They also provide In-System Programmability for the controller.
 The Flash memory technique helps in fast reprogramming of the chip and thereby reduces the
product development time.
 Atmel also provides another special family of microcontroller called AVR, an 8 bit RISC Flash
microcontroller and fast enough to execute powerful instructions in a single clock cycle and
provide the latitude you need to optimize power consumption.
 The instruction set architecture of a microcontroller can be either RISC or CISC.
 Microcontrollers are designed for either general purpose application requirement or domain
specific application requirement.
 Example for a general purpose microcontroller: The Intel 8051 microcontroller
 Example for ASIP: Automotive AVR microcontroller family from Atmel Corporation.

3.1.1.4 Microprocessor vs Microcontroller

The following table summarizes the differences between a microcontroller and microprocessor.
Microprocessor Microcontroller

A silicon chip representing a Central A microcontroller is a highly integrated chip

Processing Unit (CPU), which is capable of that contains a CPU, scratch pad RAM,
performing arithmetic as well as logical Special and General purpose Register Arrays,
operations according to a pre-defined set of On Chip ROM/FLASH memory for program
Instructions storage, Timer and Interrupt control units and
dedicated I/O ports
It is a dependent unit. It requires the It is a self contained unit and it doesn’t require
combination of other chips like Timers, external Interrupt Controller, Timer, UART
Program and data memory chips, Interrupt etc for its functioning
controllers etc for functioning
Most of the time general purpose in design Mostly application oriented or domain
and operation specific
Doesn’t contain a built in I/O port. The I/O Most of the processors contain multiple built-
Port functionality needs to be implemented in I/O ports which can be operated as a single
with the help of external Programmable 8 or 16 or 32 bit Port or as individual port
Peripheral Interface Chips like 8255 pins
Targeted for high end marketwhere Targeted for embedded market where
performance is important performance is not so critical (At present this
demarcation is invalid)
Limited power saving options compared to Includes lot of power saving features
microcontrollers

3.1.1.5 RISC vs. CISC Processors/Controllers

 The term RISC stands for Reduced Instruction Set Computing.
 As the name implies, all RISC processors/controllers possess lesser number of instructions,
typically in the range of 30 to 40.
 CISC stands for Complex Instruction Set Computing.
 - From the definition itself it is clear that the instruction set is complex and instructions are
high in number.
 From a programmers point of View RISC processors are comfortable since s/he needs to learn
only a few instructions, whereas for a CISC processor s/he needs to learn more number of
instructions and should understand the context of usage of each instruction.
 For a programmer following C coding it doesn’t matter since the cross-compiler is responsible for
the conversion of the high level language instructions to machine dependent code).
 Example for a RISC processor: Atmel AVR microcontroller,its instruction set contain only 32
instructions.
 Example for a CISC controller: The original version of 8051 microcontroller (e.g. AT89C51), its
instruction set contains 255 instructions.
 There are some other factors like pipelining features, instruction set type etc for determining the
RISC/CISC criteria.
 Some of the important criteria are listed below:

RISC CISC
Lesser no. of instructions Greater no. of Instructions
Instruction Pipelining and increased execution Generally no instruction pipelining feature
speed
Orthogonal Instruction Set (Allows each Non Orthogonal Instruction Set (All
instruction to operate on any register and use instructions are not allowed to operate on any
any addressing mode) register and use any addressing mode. It is
instruction specific)
Operations are performed on registers only, the Operations are performed on registers or
only memory operations are load and store memory depending on the instruction
Large number of registers are available Limited no. of general purpose registers
Programmer needs to write more code to Instructions are like macros in C language. A
execute a task since the instructions are simpler programmer can achieve the desired
ones functionality with a single instruction which in
turn provides the effect of using more simpler
single instructions in RISC
Single, Fixed length Instructions Variable length Instructions
Less Silicon usage and pin count More silicon usage since more additional
decoder logic is required to implement the
complex instruction decoding.
With Harvard Architecture Can be Harvard or Von-Neumann Architecture

3.1.1.7 Harvard vs. Von-Neumann Processor/Controller Architecture

 The terms Harvard and Von-Neumann refers to the processor architecture design.
 Microprocessors/controllers based on the Von-Neumann architecture shares a single common bus
for fetching both instructions and data.
- Program instructions and data are stored in a common main memory.
 - Von-Neumann architecture based processors/controllers first fetch an instruction and then
fetch the data to support the instruction from code memory.
- The two separate fetches slows down the controller’s operation.
- Von-Neumann architecture is also referred as Princeton architecture, since it was developed
by the Princeton University.
 Microprocessors/controllers based on the Harvard architecture will have separate data bus and
instruction bus.
- This allows the data transfer and program fetching to occur simultaneously on both buses.
- With Harvard architecture, the data memory can be read and written while the program
memory is being accessed.
- These separated data memory and code memory buses allow one instruction to execute while
the next instruction is fetched (“pre-fetching”).
- The pre-fetch theoretically allows much faster execution than Von-Neumann architecture.
- Since some additional hardware logic is required for the generation of control signals for this
type of operation it adds silicon complexity to the system.
 Fig 2 explains the Harvard and Von-Neumann architecture concept.

I/O CPU Memory

Program
CPU Data Memory
Memory

Single shared Bus

Fig 2: Von-Neumann and Harvard architecture concept
The following table highlights the differences between Harvard and Von-Neumann architecture.
Harvard Architecture Von-Neumann Architecture

Separate buses for Instruction and Data Single shared bus for Instruction and Data
fetching fetching
Easier to Pipeline, so high performance can Low performance Compared to Harvard
be achieved Architecture
Comparatively high cost Cheaper
No memory alignment problems Allows self modifying codes
Since data memory and program memory Since data memory and program memory
are stored physically in different locations, are stored physically in same chip, chances
no chances for accidental corruption of for accidental corruption of program
program memory memory

3.1.1.8 Big-Endian vs. Little-Endian Processors/Controllers

 Endianness specifies the order in which the data is stored in the memory by processor
operations in a multi byte system (Processors whose word size is greater than one byte).
 Suppose the word length is two byte then data can be stored in memory in two different ways:
 Little-endian means the lower-order byte of the data is stored in memory at the lowest address,
and the higher-order byte at the highest address.
 For example, a 4 byte long integer Byte3 Byte2 Byte1 Byte0 will be stored in the memory as
shown in Fig 3.

Base Address + 0 Byte 0 Byte 0 0x20000 (Base Address)

Base Address + 1 Byte 1 Byte 1 0x20001 (Base Address + 1)

Base Address + 2 Byte 2 Byte 2 0x20002 (Base Address + 2)

Base Address + 3 Byte 3 Byte 3 0x20003 (Base Address + 3)

Fig 3: Little-endian Operation

 Big-endian means the higher-order byte of the data is stored in memory at the lowest address,
and the lower-order byte at the highest address.
 For example, a 4 byte long integer Byte3 Byte2 Byte1 Byte0 will be stored in the memory as
shown in Fig 4.
Base Address + 0 Byte 3 Byte 3 0x20000 (Base Address)

Base Address + 1 Byte 2 Byte 2 0x20001 (Base Address + 1)

Base Address + 2 Byte 1 Byte 1 0x20002 (Base Address + 2)

Base Address + 3 Byte 0 Byte 0 0x20003 (Base Address + 3)

Fig 4: Big-endian Operation

3.1.1.9 Load Store Operation and Instruction Pipelining

 As mentioned earlier, the RISC processor instruction set is orthogonal, meaning it operates on
registers.
 The memory access related operations are performed by the special instructions load and store.
 If the operand is specified as memory location, the content of it is loaded to a register using the
load instruction.
 The instruction ‘Store’ stores data from a specified register to a specified memory location.
2

R1 R2 R3
1 3 3 1
load R1, x
load R2, y 2
x 00 add R3, R1, R2 3
y 7F ALU 3
store R3, z 4
z 23

4
Fig 5: Load Store Operation
 Suppose x, y and z are memory locations and to add the contents of x and y and store the result
in location z.
 Under the load store architecture the same is achieved with 4 instructions as shown in Fig 5.
 The first instruction load R1, x loads the register R1 with the content of memory location x, the
second instruction load R2, y loads the register R2 with the content of memory location y.
 The instruction add R3, R1, R2 adds the content of registers R1 and R2 and stores the result in
register R3.
 The next instruction store R3, z stores the content of register R3 in memory location z.
 The conventional instruction execution by the processor follows the fetch-decode-execute
sequence.
 Where the fetch part fetches the instruction from program memory or code memory and the
decode part decodes the instruction to generate the necessary control signals.
 The execute stage reads the operands, perform ALU operations and stores the result.
 In conventional program execution, the fetch and decode operations are performed in sequence.
 For simplicity let’s consider decode and execution together.
 During the decode operation the memory address bus is available and if it is possible to
effectively utilize it for an instruction fetch, the processing speed can be increased.
 In its simplest form instruction Pipelining refers to the overlapped execution of instruction.
 Under normal program execution flow it is meaningful to fetch the next instruction to execute,
while decoding and execution of the current instruction is in progress.
 If the current instruction in progress is a program control flow transfer instruction like jump or
call instruction, there is no meaning in fetching the instruction following the current instruction.
 In such cases the instruction fetched is flushed and a new instruction fetch is performed to fetch
the instruction.
Clock Pulses Clock Pulses Clock Pulses

Machine Cycle 1 Machine Cycle 2 Machine Cycle 3

Fetch (PC)
Execute (PC - 1) Fetch (PC+1)
Execute (PC) Fetch (PC+2)
PC : Program Counter Execute (PC+1)
Fig 6: The Single stage pipelining concept

 Whenever the current instruction is executing the program counter will be loaded with the
address of the next instruction.
 In case of jump or branch instruction, the new location is known only after completion of the
jump or branch instruction.
 Depending on the stages involved in an instruction (fetch, read register and decode. execute
instruction, access an operand in data memory, write back the result to register etc.), there can be
multiple levels of instruction pipelining.
 Fig 6 illustrates the concept of Instruction pipelining for single stage pipelining.
3.1.2 Application Specific Integrated Circuits (ASICs)
 Application Specific Integrated Circuit (ASIC) is a microchip designed to perform a specific or
unique application.
 It is used as replacement to conventional general purpose logic chips.
 It integrates several functions into a single chip and there by reduces the system development
cost.
 Most of the ASICs are proprietary products.
 As a single chip, ASIC consumes a very small area in the total system and there by helps in the
design of smaller systems with high capabilities/functionalities.
 ASICs can be pre-fabricated for a special application or it can be custom fabricated by using the
components from a re-usable building block library of components for a particular customer
application, ASIC based systems are profitable only for large volume commercial productions.
 Fabrication of ASICs requires a non-refundable initial investment for the process technology
and configuration expenses.
 This investment is known as Non-Recurring Engineering Charge (NRE) and it is a one-time
investment.
 If the Non-Recurring Engineering Charges (NRE) is borne by a third party and the Application
Specific Integrated Circuit (ASIC) is made openly available in the market, the ASIC is referred as
Application Specific Standard Product (ASSP).
 The ASSP is marketed to multiple customers just as a general-purpose product is, but to a smaller
number of customers since it is for a specific application.
 Ex for ASSP: The ADE7760 Energy Meter ASIC developed by Analog Devices for Energy
metering applications.

3.1.3 Programmable Logic Devices

 Logic devices provide specific functions, including device-to-device interfacing, data
communication, signal processing, data display, timing and control operations, and almost every
other function a system must perform.
 Logic devices can be classified into two broad categories fixed and programmable.
 As the name indicates, the circuits in a fixed logic device are permanent, they perform one
function or set of functions-once manufactured, they cannot be changed.
 On the other hand, Programmable Logic Devices (PLDs) offer customers a wide range of logic
capacity, features, speed, and voltage characteristics-and these devices can be re-configured to
perform any number of functions at any time.
 With programmable logic devices, designers use inexpensive software tools to quickly develop,
simulate, and test their designs.
 Then, a design can be quickly programmed into a device, and immediately tested in a live
circuit.
 The PLD that is used for this prototyping is the exact same PLD that will be used in the final
production of a piece of end equipment, such as a network router, a DSL modem, a DVD player,
or automotive navigation systems.
 There are no NRE costs and the final design is completed much faster than that of a custom, fixed
logic device.
 Another key benefit of using PLDs is that during the design phase customers can change the
circuitry as often as they want until the design operates to their satisfaction.
 That’s because PLDs are based on re-writable memory technology to change the design, the
device is simply reprogrammed.
 Once the design is final, customers can go into immediate production by simply programming as
many PLDs as they need with the final software design file.

Advantages of PLD
Programmable Logic Devices offer a number of important advantages over fixed logic devices,
including:

PLDs offer customers much more flexibility during the design cycle because design
iterations are simply a matter of changing the programming file and the results of design changes
can be seen immediately in working parts.

PLDs do not require long lead times for prototypes or production parts-the PLDs are
already on a distributor’s shelf and ready for shipment.

PLDs do not require customers to pay for large NRE costs and purchase expensive mask
sets + PLD suppliers incur those costs when they design their programmable devices and are able
to amortize those costs over the multi-year lifespan of a given line of PLDs.

PLDs allow customers to order just the number of parts they need, when they need them,
allowing them to control inventory. Customers who use fixed logic devices often end up with
excess inventory which must be scrapped, or if demand for their product surges, they may be
caught short of parts and face production delays.

PLDs can be reprogrammed even after a piece of equipment is shipped to a customer. In
fact, thanks to programmable logic devices, a number of equipment manufacturers now tout the
ability to add new features or upgrade products that already are in the field. To do this, they
simply upload a new programming file to the PLD, via the Internet, creating new hardware logic
in the system.

 Over the last few years programmable logic suppliers have made such phenomenal technical
advances that PLDs are now seen as the logic solution of choice from many designers.
 One reason for this is that PLD suppliers such as Xilinx are “fabless” companies instead of
owning chip manufacturing foundries, Xilinx outsource that job to partners like Toshiba and
UMC, whose chief occupation is making chips.
 This strategy allows Xilinx to focus on designing new product architectures, software tools, and
intellectual property cores while having access to the most advanced semiconductor process
technologies.
 Advanced process technologies help PLDs in a number of key areas like faster performance,
integration of more features, reduced power consumption, and lower cost.
 FPGAs are especially popular for prototyping ASIC designs where the designer can test his
design by downloading the design file into an FPGA device.
 Once the design is set, hardwired chips are produced for faster performance.
 Just a few years ago, for example, the largest FPGA was measured in tens of thousands of system
gates and operated at 40 MHz.
 Older FPGAs also were relatively expensive, costing often more than $150 for the most advanced
parts at the time.
 Today, however, FPGAs with advanced features offer millions of gates of logic capacity, operate
at 300 MHz, can cost less than $10, and offer a new level of integrated functions such as
processors and memory.

3.1.3.1 CPLDs and FPGAs

 The two major types of programmable logic devices are Field Programmable Gate Arrays
(FPGAs) and Complex Programmable Logic Devices (CPLDs).
 Of the two, FPGAs offer the highest amount of logic density, the most features, and the highest
performance.
 The largest FPGA now shipping, part of the Xilinx Virtex TM line of devices, provides eight
million system gates.
 These advanced devices also offer features such as built-in hardwired processors (such as the
IBM power PC), substantial amounts of memory, clock management systems, and support for
many of the latest, very fast device-to-device signaling technologies.
 FPGAs are used in a wide variety of applications ranging from data processing and storage, to
instrumentation, telecommunications and Digital Signal Processing.
 CPLDs, by contrast, offer much smaller amounts of logic-up to about 10, 000 gates.
 But CPLDs offer very predictable timing characteristics and are therefore ideal or critical control
applications.
 CPLDs such as Xilinx Cool Runner TM series also require extremely low amounts of power and
are very inexpensive, making them ideal for cost-sensitive, battery-operated, portable applications
such as mobile phones and digital handheld assistants. (Refer presentation slides for differences)

3.1.4 Commercial Off-the-Shelf Components (COTS)

 Commercial Off-the-Shelf (COTS) product is one which is used ‘as-is’.
 COTS products are designed in such a way to provide easy integration and interoperability with
existing system components.
 The COTS component itself may be developed around a general purpose or domain specific
processor or an Application Specific Integrated circuit or a Programmable Logic Device.
 Typical examples of COTS hardware unit are remote controlled toy car control units including the
circuitry part, high performance, high frequency microwave electronics (2-200 GHz), high
bandwidth analog-to-digital converters, devices and components for operation at very high
temperatures, electro-optic IR imaging arrays, UV/IR detectors, etc.
 The major advantage of using COTS is that they are readily available in the market, are cheap
and a developer can cut down his/her development time to a great extent.
 This in turn reduces the time to market of embedded systems.
 The TCP/IP plug-in module available from various 1% manufactures like ‘WIZnet’, ‘Freescale’,
‘Dynalog’, etc are very good examples of COTS product.
 Everything will be readily supplied by the COTS manufacturer.
 What you need is to do is identify the COTS for your system and give the plug-in option on your
board according to the hardware COTS.
 Though multiple vendors supply COTS for the same application, the major problem faced by the
end user is that there are no operational and manufacturing standards.
 A Commercial off-the-shelf (COTS) component manufactured by a vendor need not have hardware
plug-in and firmware interface compatibility with one manufactured by a second vendor for the
same application.
 This restricts the end-user to stick to a particular vendor for a particular COTS.
 This greatly affects the product design.
 The major drawback of using COTS components in embedded design is that the manufacturer of
the COTS component may withdraw the product or discontinue the production of the COTS at
any time if a rapid change in technology occurs, and this will adversely affect a commercial
manufacturer of the embedded system which makes use of the specific COTS product.

2.2 MEMORY
 Memory is an important part of a processor/controller based embedded systems.
 Some of the processors/controllers contain built in memory and this memory is referred as on-
chip memory.
 Others do not contain any memory inside the chip and requires external memory to be connected
with the controller/processor to store the control algorithm.
 It is called off-chip memory.
 Also some working memory is required for holding data temporarily during certain operations.
 This section deals with the different types of memory used in embedded system applications.

2.2.1 Program Storage Memory (ROM)

 The program memory or code storage of an embedded system stores the program instructions
and it can be classified into different types as per the block diagram representation given in Fig.

FLASH CODE NVRAM

MEMORY(ROM)

PROM (OTP) Masked ROM EPROM EEPROM

(MROM)

Fig 7: Classification of Program Memory (ROM)

 The code memory retains its contents even after the power to it is turned off.
 It is generally known as non-volatile storage memory.
 Depending on the fabrication, erasing and programming techniques they are classified into the
following types.
3.2.1.1 Masked ROM (MROM)
 Masked ROM is a one-time programmable device.
 Masked ROM makes use of the hardwired technology for storing data.
 The device is factory programmed by masking and metallization process at the time of
production itself, according to the data provided by the end user, the primary advantage of this is
low cost for high volume production.
 They are the least expensive type of solid state memory.
 Different mechanisms are used for the masking process of the ROM, like:

1. Creation of an enhancement or depletion mode transistor through channel implant.

2. By creating the memory cell either using a standard transistor or a high threshold transistor. In the
high threshold mode, the supply voltage required to turn ON the transistor is above the normal ROM
IC operating voltage. This ensures that the transistor is always off and the memory cell stores always
logic 0.
 Masked ROM is a good candidate for storing the embedded firmware for low cost embedded
devices.
 Once the design is proven and the firmware requirements are tested and frozen, the binary data
(The firmware cross compiled/assembled to target processor specific machine code)
corresponding to it can be given to the MROM fabricator.
 The limitation with MROM based firmware storage is the inability to modify the device firmware
against firmware upgrades.
 Since the MROM is permanent in bit storage, it is not possible to alter the bit information

3.2.1.2 Programmable Read Only Memory (PROM) / (OTP)

 Unlike Masked ROM Memory, One Time Programmable Memory (OTP) or PROM is not pre-
programmed by the manufacturer.
 The end user is responsible for programming these devices.
 This memory has nichrome or polysilicon wires arranged in a matrix.
 These wires can be functionally viewed as fuses.
 It is programmed by: PROM programmer which selectively bums the fuses according to the bit
pattern to be stored.
 Fuses which are not blown/burned represents a logic “1” whereas fuses which are blown/burned
represents a logic “0”.
 The default state is logic “1”.
 OTP is widely used for commercial production of embedded systems whose proto-typed versions
are proven and the code is finalized.
 It is a low cost solution for commercial production.
 OTPs cannot be reprogrammed.

3.2.1.3 Erasable Programmable Read Only Memory (EPROM)

 OTPs are not useful and worth for development purpose.
 During the development phase the code is subject to continuous changes and using an OTP each
time to load the code is not economical.
 Erasable Programmable Read Only Memory (EPROM) gives the flexibility to reprogram the
same chip.
 EPROM stores the bit information by charging the floating gate of an FET.
 Bit information is stored using an EPROM programmer, which applies high voltage to charge
the floating gate.
 EPROM contains a quartz crystal window for erasing the stored information.
 If the window is exposed to ultraviolet rays for a fixed duration, the entire memory will be
erased.
 Even though the EPROM chip is flexible in terms of re-programmability, it needs to be taken out
of the circuit board and put in a UV eraser device for 20 to 30 minutes.
 So it is a tedious and time-consuming process.

3.2.1.4 Electrically Erasable Programmable Read Only Memory (EEPROM)

 As the name indicates, the information contained in the EEPROM memory can be altered by
using electrical signals at the register/Byte level.
 They can be erased and reprogrammed in-circuit.
 These chips include a chip erase mode and in this mode they can be erased in a few milliseconds.
 It provides greater flexibility for system design.
 The only limitation is their capacity is limited when compared with the standard ROM (A few
kilobytes).

3.2.1.5 FLASH
 FLASH is the latest ROM technology and is the most popular ROM technology used in today’s
embedded designs.
 FLASH memory is a variation of EEPROM technology.
 It combines the re-programmability of EEPROM and the high capacity of standard ROM.
 FLASH memory is organized as sectors (blocks) or pages.
 FLASH memory stores information in an array of floating gate MOSFET transistors.
 The erasing of memory can be done at sector level or page level without affecting the other
sectors or pages.
 Each sector/page should be erased before re-programming.
 The typical erasable capacity of FLASH is 1000 cycles.
 W27C512 from WINBOND is an example of 64KB FLASH memory.

3.2.1.6 NVRAM
 Non-volatile RAM is a random access memory with battery backup.
 It contains static RAM based memory and a minute battery for providing supply to the memory
in the absence of external power supply.
 The memory and battery are packed together in a single package.
 The life span of NVRAM is expected to be around 10 years.
 DS-644 from Maxim/Dallas is an example of 32KB NVRAM.
3.2.2 Read-Write Memory/ Random Access Memory (RAM)
 RAM is the data memory or working memory of the controller/processor.
 Controller/processor can read from it and write to it.
 RAM is volatile, meaning when the power is turned off, all the contents are destroyed.
 RAM is a direct access memory, meaning we can access the desired memory location, directly
without the need for traversing through the entire memory locations to reach the desired memory
position.
 This is in contrast to the Sequential Access Memory (SAM), where the desired memory location
is accessed by either traversing through the entire memory or through a ‘seek’ method.
 Examples of sequential access memory: Magnetic tapes, CD ROMS etc.
 RAM generally falls into three categories: Static RAM (SRAM), dynamic RAM (DRAM) and
non-volatile RAM (NVRAM).

Fig 8: Classification of working memory (RAM)

3.2.2.1 Static RAM (SRAM)

 Static RAM stores data in the form of voltage.
 They are made up of flip-flops.
 Static RAM is the fastest form of RAM available.
 In typical implementation, an SRAM cell (bit) is realized using six transistors (or 6 MOSFETs).
 Four of the transistors are used for building the latch (fIip-flop) part of the memory cell and two
for controlling the access.
 SRAM is fast in operation due to its resistive networking and switching capabilities.
 In its simplest representation and SRAM cell can be visualized as shown in Fig 9.

Fig 9: SRAM cell implementation

 This implementation in its simpler form can be visualized as two cross coupled inverters with
read/ write control through transistors.
 The four transistors in the middle form the cross-coupled inverters.
 This can be visualized as shown in Fig 9.
 From the SRAM implementation diagram, it is clear that access to the memory cell is controlled
by the Word Line, which controls the access transistors (MOSFETs) M5 and M6.
 The access transistors control the connection to bit lines B & B\.
 In order to write a value to the memory cell, apply the desired value to the bit control lines (For
writing 1, make B = 1 and B =0; for writing 0, make B = 0 and B\ =1) and assert the Word Line
(Make Word line high).
 This operation latches the bit written in the flip-flop.
 For reading the content of the memory cell, assert both B and B\ bit lines to l and set the Word
line to 1.
 The major limitations of SRAM are low capacity and high cost.
 Since a minimum of six transistors are required to build a single memory cell, imagine how many
memory cells we can fabricate on a silicon wafer.

3.2.2.2 Dynamic RAM (DRAM)

 Dynamic RAM stores data in the form of charge.
 They are made up of MOS transistor and a capacitor.
 The advantages of DRAM are its high density and low cost compared to SRAM.
 The disadvantage is that since the information is stored as charge it gets leaked off with time and
to prevent this they need to be refreshed periodically.
 Special Circuits called DRAM controllers are used for the refreshing operation.
 The refresh operation is done periodically in milli-seconds interval.
 Fig 10 illustrates the typical implementation of a DRAM cell.

Fig 10: DRAM cell implementations

 The MOSFET acts as the gate for the incoming and outgoing data whereas the capacitor acts as
the bit storage unit.
 Table given below summarizes the relative merits and demerits of SRAM and DRAM
technology.
 SRAM Cell DRAM Cell

Made up of 6 CMOS transistors (MOSFET) Made up of a MOSFET and a capacitor

Doesn’t require refreshing Requires refreshing

Low capacity (Less dense) High capacity (Highly dense)

More expensive Less expensive

Fast in operation. Typical access time is10 ns. Slow in operation due to
refresh requirements. Typical access time is 60 ns.
Write operation is faster than read operation.

3.2.2.3 NVRAM
 Non-volatile RAM is a random access memory with battery backup.
 It contains static RAM based memory and a minute battery for providing supply to the memory
in the absence of external power supply.
 The memory and battery are packed together in a single package.
 The life span of NVRAM is expected to be around 10 years.
 DS-1744 from Maxim/Dallas is an example of 32KB NVRAM.

3.3 SENSORS AND ACTUATORS

 At the very beginning of this chapter it is already mentioned that an embedded system is in
constant interaction with the Real world and the controlling/monitoring functions executed by
the embedded system is achieved in accordance with the changes happening to the Real world.
 The changes in system environment or variables are detected by the sensors connected to the
input port of the embedded system.
 If the embedded system is designed for any controlling purpose, the system will produce some
changes in the controlling variable to bring the controlled variable to the desired value.
 It is achieved through an actuator connected to the output port of the embedded system.
 If the embedded system is designed for monitoring purpose only, then there is no need for
including an actuator in the system.
 For example, take the case of an ECG machine.
- It is designed to monitor the heart beat status of a patient and it cannot impose a control over
the patient’s heart beat and its order.
- The sensors used here are the different electrode sets connected to the body of the patient.
- The variations are captured and presented to the user (may be a doctor) through a visual
display or some printed chart.

3.3.1 Sensors
 Sensor is a transducer device that converts energy from one form to another for any measurement
or control purpose.
 It is an input device.
 The “Smart” running shoe example given in Chapter 1, has the sensor which measures the
distance between the cushion and magnet in the smart running shoe is a magnetic Hall Effect
sensor.

3.3.2 Actuators
 Actuator is a form of transducer device (mechanical or electrical) which converts signals to
corresponding physical action (motion).
 Actuator acts as an output device.
 In “Smart” running shoe example given in Chapter 1, the actuator was used for adjusting the
position of the cushioning element is a micro stepper motor.

3.3.3 The I/O Subsystem

 I/O subsystem of the embedded system facilitates the interaction of the embedded system with
the external world.
 As mentioned earlier the interaction happens through the sensors and actuators connected to the
input and output ports respectively of the embedded system.
 The sensors may not be directly interfaced to the input ports, instead they may be interfaced
through signal conditioning and translating systems like ADC, Optocoupler, etc.
 This section illustrates some of the sensors and actuators used in embedded systems and the I/O
systems to facilitate the interaction of embedded systems with external world.

3.3.3.1 Light Emitting Diode (LED)

 Light Emitting Diode (LED) is an important output device for visual indication in any embedded
system.
 LED can be used as an indicator for the status of various signal or situations.
 Typical examples are indicating the presence of power conditions like ‘Device ON’ Battery low’
or ‘Charging of battery’ for a battery operated hand held embedded devices.
 Light Emitting Diode is a PN junction diode and it contains an anode and a cathode.
 For proper functioning of the LED, the anode of it should be connected to +ve terminal of the
supply voltage and cathode to the -ve terminal of supply voltage.
 The current flowing through the LED must be limited to a value below the maximum current that
it can conduct.
 A resistor is used in series between the power supply and the LED GND to limit the current
through the LED.
 The ideal LED interfacing circuit is shown in Fig 11.

Fig 11: LED interfacing

 LED’s can be interfaced to the port pin of a processor/controller in two ways.
 In the first method, the anode is directly connected to the port pin and the port pin drives the
LED.
 In this approach the port pin ‘sources’ current to the LED when the port pin is at logic High
(Logic ‘1’).
 In the second method, the cathode of the LED is connected to the port pin of the
processor/controller and the anode to the supply voltage through a current limiting resistor.
 The LED is turned on when the port pin is at logic Low (Logic ‘0’).
 Here the port pin ‘sinks’ current.
 If the LED is directly connected to the port pin, depending on the maximum current that a port
pin can source, the brightness of LED may not be to the required level.
 In the second approach, the current is directly sourced by the power supply and the port pin acts
as sink for current. Here we will get the required brightness for the LED.

3.3.3.2 7-Segment LED Display

 The 7-segment LED display is an output device for displaying alpha numeric characters.
 It contains 8 Light Emitting Diodes (LED) segments arranged in a special form.
 Out of the 8 LED segments, 7 are used for displaying alpha numeric characters used for
representing ‘decimal point’ in number display.
 Figure explains the arrangement of LED segments in a 7 segment LED display.
 The LED segments are named A to G and the decimal point LED segment is named as DP.
 The LED segments A to G and DP should be lit accordingly to display numbers and characters.
 Ex: for displaying the number 4, the segments F, G, B and C are lit.
 For displaying 3, the segments A, B, C, D, G and DP are lit.
 For displaying the character ‘D’, the segments B, C, D, E and G are lit.
 All these 8 LED segments need to be connected to one port of the processor/controller for
displaying alpha numeric digits.
 The 7-segment LED displays are available in two different configurations, namely Common
Anode and Common Cathode.
 In the common anode configuration, the anodes of the 8 segments are connected commonly
whereas in the common cathode configuration, the 8 LED segments share a common cathode
line.

Fig 12: common anode and cathode configurations of a 7-segment LED Display

 Fig 12 illustrates the Common Anode and Cathode configurations.

 Based on the configuration of the 7-segment LED unit, the LED segment’s anode or cathode is
connected to the port of the processor/controller in the order ‘A’ segment to the least significant
port pin and DP segment to the most significant port pin.
 The current flow through each of the LED segments should be limited to the maximum value
supported by the LED display unit.
 The typical value for the current fall within the range of 20mA.
 The current through each segment can be limited by connecting a current limiting resistor to the
anode or cathode of each segment.
 The value for the current limiting resistors can be calculated using the current value from the
electrical parameter listing of the LED display.
 For common cathode configurations, the anode of each LED segment is connected to the port
pins of the port to which the display is interfaced.
 The anode of the common anode LED display is connected to the 5V supply voltage through a
current limiting resistor and the cathode of each LED segment is connected to the respective port
pin line.
 For an LED segment to light in the common anode LED configuration, the port pin to which the
cathode of the LED segment is connected should be set at logic 0.
 7-Segment LED display is a popular choice for low cost.
 LED embedded applications like public telephone call monitoring I/O Interface devices, point of
sale terminals etc.

3.3.3.3 Opto-coupler
 Opto-coupler is a solid state device to isolate two parts of a circuit.
 Optocoupler combines an LED and a photo-transistor in a single housing (package).
 Fig 13 shows Optocoupler device illustrates the functioning of an Optocoupler device.

Fig 13: An optocoupler device

 In electronic circuits, an Optocoupler is used for suppressing interference in data

communication, circuit isolation, high voltage separation, simultaneous separation and signal
intensification etc.
 Optocouplers can be used in either input circuits or in output circuits.
 Fig 14 illustrates the usage of optocoupler in input circuit and output circuit of an embedded
system with a micro-controller as the system core.
 Fig 14: Optocoupler in Input and Output Circuit

 Optocoupler is available as IC from different semiconductor manufacturers.

 Example for optocoupler IC: MCT2M IC from Fair child semiconductor.

3.3.3.5 Relay
 Relay is an electro-mechanical device.
 In embedded application, the relay unit acts as dynamic path selectors for signals and power.
 The relay unit contains a relay coil made up of insulated wire on a metal core and metal
armature with one or more contacts.
 ‘Relay’ works on electromagnetic principle.
 When a voltage is applied to the relay coil, current flows through the coil, which in turn generates
a magnetic field.
 The magnetic field attracts the armature core and moves the contact point.
 The movement of the contact point changes the power/signal flow path.
 Relays are available in different configurations.
 Fig 15 given below illustrates the widely used relay configurations for embedded applications.

Fig 15: Relay Configurations

 The Single Pole Single Throw configuration has only one path for information flow.
 The path is either open or closed in normal condition.
 For normally Open Single Pole Single Throw relay, the circuit is normally open and it becomes
closed when the relay is energized.
 For normally closed Single Pole Single Throw configuration, the circuit is normally closed and it
becomes open when the relay is energized.
 For Single Pole Double Throw Relay, there are two paths for information flow and they are
selected by energizing or de-energizing the relay.

Transistor based Relay driving circuit

 Relay driving circuit using transistors is as given in the Fig 16.
 A free-wheeling diode is used for free-wheeling the voltage produced in the opposite direction
when the relay coil is de-energized.
 The freewheeling diode is essential for protecting the relay and the transistor.
 Most of the industrial relays are bulky and requires high voltage to operate.
 Special relays called Reed relays are available for embedded application requiring switching of
low voltage DC signals.

Vcc

Freewheeling Diode

Relay Coil
Load
Port Pin

Relay Unit

Fig 16: Transistor based Relay driving circuit

3. 3.6 Piezo Buzzer

 Piezo buzzer is a piezoelectric device for generating audio indications in embedded application.
 A piezoelectric buzzer contains a piezoelectric diaphragm which produces audible sound in
response to the voltage applied to it.
 Piezoelectric buzzers are available in two types ‘self-driving’ and ‘external driving’.
 The self-driving circuit contains all the necessary components to generate sound at a predefined
tone.
 It will generate a tone on applying the voltage.
 External driving Piezo buzzers supports the generation of different tones.
 The tone can be varied by applying a variable pulse train to the piezoelectric buzzer.
 A Piezo buzzer can be directly interfaced to the port pin of the processor/control.
 Depending on the driving current requirements, the Piezo buzzer can also be interfaced using a
transistor based driver circuit as in the case of a relay.

3.3.7 Push Button Switch

 It is an input device.
 Push button switch comes in two configurations, namely ‘Push to Make’ and ‘Push to Break’.
 In the ‘Push to Make’ configuration, the switch is normally in the open state and it makes a
circuit contact when it is pushed or pressed.
 In the ‘Push to Break ‘configuration, the switch is normally in the closed state and it breaks the
circuit contact when it is pushed or pressed.
 The push button stays in the ‘closed’ (For Push to Make type) or ‘open’ (For Push to Break type)
state as long as it is kept in the pushed state and it breaks/makes the circuit connection when it is
released.
 The Push button is normally connected to the port pin of the host processor/controller.
 Depending on the way in which the push button interfaced to the controller, it can generate either
a ‘HIGH’ pulse or a ‘LOW’ pulse.
 Fig 17 illustrates how the push button can be used for generating ‘LOW’ and ‘HIGH’ pulses.

Fig 17: Push botton switch

3.4 COMMUNICATION INTERFACE

 Communication interface is essential for communicating with various subsystems of the
embedded system and with the external world.
 For an embedded product, the communication interface can be viewed in two different
perspectives; namely Device/board level communication interface (On-board Communication
Interface) and Product level communication interface (External Communication Interface).
 Embedded product is a combination of different types of components (chip devices) arranged on
a Printed Circuit Board (PCB).
 The communication channel which interconnects the various components within an embedded
product is referred as device/board level communication interface (on-board communication
interface).
 Serial interfaces like I2C, SPI, UART, l-Wire, etc. and parallel bus interface are examples of
On-board Communication Interface.
 Some embedded systems are self-contained units and they don’t require any interaction and data
transfer with other sub-systems or external world.
 On the other hand, certain embedded systems may be a part of the large distributed system and
they require interaction and data transfer between various devices and sub-modules.
 The external communication interface can be a wired media or a wireless media and it can be a
serial or a parallel interface.
 Examples for wireless communication interface: Infrared (IR), Bluetooth (BT), Wireless LAN
(Wi-Fi), Radio Frequency waves (RF), GPRS etc.
 Examples for wired interfaces: RS-232C/RS-422/RS-485, USB, Ethernet IEEE 1394 port,
Parallel port, CF-II interface, SDIO, PCMCIA etc.
 It is not mandatory that an embedded system should contain an external communication interface.
 Example for embedded system with external communication interface: Mobile communication
equipment.

3.4.1 On-board Communication Interfaces

 On-board Communication Interface refers to the different communication channels/buses for
interconnecting the various integrated circuits and other peripherals within the embedded system.
 The following section gives an overview of the various interfaces for on-board communication.

3.4.1.1 Inter Integrated Circuit (12C) Bus

 The Inter Integrated Circuit Bus (I2C-Pronounced ‘I square C‘) is a synchronous, bi-directional,
half duplex, (one-directional communication at a given point of time) two wire serial interface
bus.
 The concept of 12C bus was developed by Philips semiconductors in the early 1980s.
 The original intention of I2C was to provide an easy way of connection between a
microprocessor/microcontroller system and the peripheral chips in television sets.
 The I2C bus comprise of two bus lines. Namely, Serial Clock SCL and Serial Data SDA.
 SCL line is responsible for generating synchronization clock pulses and SDA is responsible for
transmitting the serial data across devices.
 I2C bus is a shared bus system to which many number of I2C devices can be connected.
 Devices connected to the 12C bus can act as either 'Master’ device or ‘Slave’ device.
 The ‘Master' device is responsible for controlling the communication by initiating/terminating
data transfer.
- Sending data and generating necessary synchronization clock pulses.
 ‘Slave’ devices wait for the commands from the master and respond upon receiving the
command, ‘Master’ and ‘Slave’ devices can act as either transmitter or receiver.
SCL SDA Vcc
2.2K

SDA
2.2K
Port Pins SCL
Slave 1
SCL I2C Device
Master SDA (Eg: Serial
(Microprocessor/ EEPROM)
Controller)

SCL Slave 2
SDA I2C Device

I2C Bus

Fig 18: I2C Bus Interfacing

 Regardless whether a master is acting as transmitter or receiver, the synchronization clock signal
is generated by the ‘Master’ device only.
 I2C supports multi masters on the same bus.
 The following bus interface diagram shown in Fig 18 illustrates the connection of master and
slave devices on the 12C bus.
 The 12C bus interface is built around an input buffer and an open drain or collector transistor.
 When the bus is in the idle state, the open drain/collector transistor will be in the floating state
and the output lines (SDA and SCL) switch to the High Impedance state.
 For proper operation of the bus, both the bus lines should be pulled to the supply voltage (+5V
for TTL family and +3.3V for CMOS family devices) using pull-up resistors.
 The typical value of resistors used in pull-up is 2.2K.
 With pull-up resistors, the output lines of the bus in the idle state will be ‘HIGH’.
 The address of a I2C device is assigned by hardwiring the address lines of the device to the
desired logic level.
 The address to various I2C devices in an embedded device is assigned and hardwired at the time
of designing the embedded hardware.
 The sequence of operations for communicating with a 12C slave device is listed below:
1. The master device pulls the clock line (SCL) of the bus to ‘HIGH’
2. The master device pulls the data line (SDA) ‘LOW’, when the SCL line is at logic ‘HIGH’
(This is the ‘Start’ condition for data transfer)
3. The master device sends the address (7 bit or 10 bit wide) of the ‘slave’ device to which it
wants to communicate, over the SDA line. Clock pulses are generated at the SCL line for
synchronizing the bit reception by the slave device. The MSB of the data is always
transmitted first. The data in the bus is valid during the ‘HIGH’ period of the clock signal
4. The master device sends the Read or Write bit (Bit value = 1 Read operation; Bit value 0
Write Operation) according to the requirement.
5. The master device waits for the acknowledgement bit from the slave device whose address is
sent on the bus along with the Read/Write operation command. Slave devices connected to
the bus compares the address received with the address assigned to them.
6. The slave device with the address requested by the master device responds by sending an
acknowledge bit (Bit value = 1) over the SDA line.
7. Upon receiving the acknowledge bit, the Master device sends the 8bit data to the slave device
over SDA line, if the requested operation is ‘Write to device‘. If the requested operation is
‘Read from device', the slave device sends data to the master over the SDA line.
8. The master device waits for the acknowledgement bit from the device upon byte transfer
complete for a write operation and sends an acknowledge bit to the Slave device for a read
operation
9. The master device terminates the transfer by pulling the SDA line ‘High’ when the clock line
SCL is at logic ‘High’ (Indicating the ‘STOP’ condition)
 I2C bus supports three different data rates.
 They are: i) Standard mode (Data rate up to 100 kbps)
ii) Fast mode (Data rate up to 400 kbps)
 iii) High Speed mode (Data rate up to 3.4 Mbps).
 The first generation 12C devices were designed to support data rates only up to 100kbps.
 The new generation 12C devices are designed to operate at data rates up to 3.4Mbits/sec.

3.4.1.2 Serial peripheral Interface (SPI)

 The Serial Peripheral Interface Bus (SPI) is a synchronous, bi-directional full duplex, four-wire
serial interface bus.
 The concept of SPI was introduced by Motorola.
 SPI is a single master multi-slave system.
 It is possible to have a system where more than one SPI device can be master, provided the
condition only one master device is active at any given point of time is satisfied.
 The SPT bus interfacing is as shown in Fig 19.
 SPI requires four signal lines for communication. They are:
Master Out Slave in (MOSI): Signal line carrying the data from master to slave device. It is also
known as Slave Input/Slave Data in (SI/SDI)
Master in Slave out (MISO): Signal line carrying the data from slave to master device. It is also
known as Slave Output (SO/SDO)
Serial Clock (SCLK): Signal line carrying the clock signals
Slave Select (SS): Signal line for slave device select. It is an active low signal
 The master device is responsible for generating the clock signal.
 It selects the required slave device by asserting the corresponding slave device’s slave select
signal ‘LOW’.
 The data out line (MISO) of all the slave devices when not selected floats at high impedance
state.
 The serial data transmission through SPI bus is fully configurable.
MOSI SCL MISO

MISO
SCL
MOSI MOSI Slave 1
SCL SPI Device
Master
MISO (Eg: Serial
(Microprocessor/
SS\ EEPROM)
Controller)
SS1\
SS2\
MOSI
Slave 2
SCL
SPI Device
MISO
(Eg: LCD)
SS\

SPI Bus

Fig 19: SPI bus Interfacing

 SPI devices contain a certain set of registers for holding these configurations.
 The serial peripheral control register holds the various configuration parameters like master
slave selection for the device, baud rate selection for communication, clock signal control etc.
 The status register holds the status of various conditions for transmission and reception.
 The bus interface diagram shown in Fig 19 illustrates the connection of master and slave devices
on the SPI bus.
 SP1 works on the principle of ‘Shift Register’.
 The master and slave devices contain a special shift register for the data to transmit or receive.
 The size of the shift register is device dependent.
 Normally it is a multiple of 8.
 During transmission from the master to slave, the data in the master’s shift register is shined out
to the MOSI pin and it enters the shift register of the slave device through the MOSI pin of the
slave device.
 At the same time the shifted out data bit from the slave device’s shift register enters the shift
register of the master device through MlSO pin.
 In summary, the shift registers of ‘master’ and ‘slave’ devices form a circular buffer.
 For some devices, the decision on whether the LS/MS bit of data needs to be sent out first is
configurable through configuration register (e.g. LSBF bit of the SP1 control register for
Motorola’s 68HC12 controller).
 When compared to 12C, SPI bus is most suitable for applications requiring transfer of data in
‘streams'.
 The only limitation is SPI doesn’t support an acknowledgement mechanism.

3.4.1.3 Universal Asynchronous Receiver Transmitter (UART)

 Universal Asynchronous Receiver Transmitter (UART) based data transmission is an
asynchronous form of serial data transmission.
 UART based serial data transmission doesn’t require a clock signal to synchronize the
transmitting end and receiving end for transmission.
 Instead it relies upon the pre-defined agreement between the transmitting device and receiving
device.
 The serial communication settings (Baud rate, number of bits per byte, parity, number of start
bits and stop bit and flow control) for both transmitter and receiver should be set as identical.
 The start and stop of communication is indicated through inserting special bits in the data stream.
 While sending a byte of data, a start bit is added first and a stop bit is added at the end of the bit
stream.
 The least significant bit of the data byte follows the ‘start’ bit.
 The ‘start’ bit informs the receiver that a data byte is about to arrive.
 The receiver device starts polling its received line’ as per the baud rate settings.
 If the baud rate is ‘x’ bits per second, the time slot available for one bit is l/x seconds.
 The receiver unit polls the receiver line at exactly half of the time slot available for the bit.
 If parity is enabled for communication, the UART of the transmitting device adds a parity bit (bit
value is l for odd number of l’s in the transmitted bit stream and 0 for even number of is the
 UART of the receiving device calculates the parity of the bits received and compares it with the
received parity bit for error checking.
 The UART of the receiving device discards the ‘Start’, ‘Stop’ and ‘Parity' the received serial bit
data to a word.
 For proper communication, the ‘Transmit line’ of the sending device should be connected to the
‘Receive line’ of the receiving device. Fig 20 illustrates the same.

TXD TXD
UART UART
RXD RXD

TXD: Transmitter Line

RXD: Receiver Line

Fig 20: UART interfacing

 In addition to the serial data line function, UART provides hardware handshake receiver
support for controlling the serial data now.
 UART chips are available from different semiconductor manufacturers.
 National Semiconductor’s 8250 UART chip is considered as the standard setting UART.
 It was used in the original IBM PC.
 Now a day’s most of the microprocessors/controllers are available with integrated UART
functionality and they provide built-in instruction support for serial data transmission and
reception.

3.4.1.4 1–Wire Interface

 1-wire interface is an asynchronous, half-duplex communication protocol developed by Maxim
Dallas Semiconductor (https: //www.maxim-ic.com).
Vcc

4.7K

DQ Slave 1
Port Pin
1-Wire Device
(Eg: DS2760 Battery
GND
monitor IC )
Master
(Microprocessor/
Controller) DQ Slave 2
1-Wire Device
(Eg: DS2431 1024
GND GND
Bit EEPROM )

Fig 21: 1 wire interfacing

 It is also known as Dallas 1-Wire® protocol.
 It makes use of only a single signal line (wire) called DQ for communication and follows the
master-slave communication model.
 One of the key feature of l-wire bus is that it allows power to be sent along the signal wire as
well.
 The I2C slave devices incorporate internal capacitor (typically of the order of 800 pF) to power
the device from the signal line.
 The l-wire interface supports a Single master and one or more slave devices on the bus.
 The bus interface diagram shown in Fig 21 illustrates the connection of master and slave devices
on the l-wire bus.
 Every l-wire device contains a globally unique 64bit identification number stored within it.
 The unique identification number can be used for addressing individual devices present on the
bus in case there are multiple slave devices connected to the 1-wire bus.
 The identifier has three parts: an 8bit family code, a 48bit serial number and 8 bit CRC
computed from the first 56 bits.
 The sequence of operation for communicating with a 1-wire slave device is listed below:
1. The master device sends a ‘Reset’ pulse on the l-wire bus.
2. The slave device(s) present on the bus respond with 3 ‘Presence’ pulse.
3. The master device sends a ROM command (Net Address Command followed by the 64bit
address of the device). This addresses the slave device(s) to which it wants to initiate a
communication.
4. The master device sends a read/write function command to read/write the internal memory or
register of the slave device.
5. The master initiates a Read data/Write data from the device or to the device
 All communication over the l-wire bus is master initiated.
 The communication over the l-wire bus is divided into timeslots of 60μs.
 The ‘Reset’ pulse occupies 8 time slots.
 For starting a communication, the master asserts the reset pulse by pulling the 1-wire bus ‘LOW’
for at least 8 time slots ‘slave’ device is present on the bus and is ready for communication it
should respond to the master with a ‘Presence’ pulse, within 60μs of the release of the ‘Reset’
pulse by the master.
 The slave device(s) responds with a ‘Presence’ pulse by pulling the l-wire bus ‘LOW’ for a
minimum of 1 time slot (60μs).
 For writing a bit value of 1 on the l-wire bus, the bus master pulls the bus for l to l5 bus and then
releases the bus for the rest of the time slot.
 A bit value of ‘0’ is written on the bus by master pulling the bus for a minimum of 1 time slot
(60μs) and a maximum of 2 time slots (120μs).
 To Read a bit from the slave device, the master pulls the bus ‘LOW’ for l to 15μs.
 If the slave wants to send a bit value ‘1’, in response to the read request from the master, it
simply releases the bus for the rest of the time slot.
 If the slave wants to send a bit value ‘0’, it pulls the bus ‘LOW’ for the rest of the time slot.
3.4.1.5 Parallel Interface
 The on-board parallel interface is normally used for communicating with peripheral devices
which are memory mapped to the host of the system.
 The host processor/controller of the embedded system contains a parallel bus and the device
which supports parallel bus can directly connect to this bus system.
 The communication through the parallel bus is controlled by the control signal interface
between the device and the host.
 The bus interface diagram shown in Fig 22 illustrates the interfacing of devices through parallel
interface.


D0 to Data Bus
Dx-1 Peripheral Device
RD\ RD\ (Eg: ADC)
WR\ WR\
Host Control Signals CS\
(Microprocessor/
Controller) Chip Select

A0 to Address Bus Address De-coder

Ay-1 Circuit

x: Data bus width

y: Address Bus width

Fig 22: Interfacing of devices through parallel interface

 The ‘Control Signals’ for communication includes ‘Read/ Write’ signal and device select signal.
 The device normally contains a device select line and the device becomes active only when this
line is asserted by the host processor.
 The direction of data transfer (Host to Device or Device to Host) can be controlled through the
control signal lines for ‘Read’ and ‘Write’.
 Only the host processor has control over the ‘Read’ and ‘Write’ control signals.
 The device is normally memory mapped to the host processor and a range of address is assigned
to it.
 An address decoder circuit is used for generating the chip select signal for the device.
 When the address selected by the processor is within the range assigned for the device, the
decoder circuit activates the chip select line and thereby the device becomes active.
 The processor then can read or write from or to the device by asserting the corresponding control
line (RD and WR respectively).
 Strict timing characteristics are followed for parallel communication.
 As mentioned earlier, parallel communication is host processor initiated.
 If a device wants to initiate the communication, it can inform the same to the processor through
interrupts.
 For this, the interrupt line of the device is connected to the interrupt line of the processor and the
corresponding interrupt is enabled in the host processor.
 The width of the parallel interface is determined by the data bus width of the host processor.
 It can be 4bit, 8bit, 16bit, 32bit or 64bit etc.
 The bus width supported by the device should be same as that of the host processor.

3.4.2 External Communication Interfaces

 The External Communication Interface refers to the different communication channels/buses used
by the embedded system to communicate with the external world.
 The following section gives an overview of the various interfaces for external communication.

3.4.2.1 RS-232 & RS 485

 RS-232 C (Recommended Standard number 232, revision C from the Electronic Industry
Association) is a legacy, full duplex, wired, asynchronous serial communication interface.
 The RS-232 interface is developed by the Electronics Industries Association (EIA) during the
early 1960s.
 RS-232 extends the UART communication signals for external data communication.
 UART uses the standard TTL/CMOS logic (Logic ‘High’ corresponds to bit value 1 and Logic
‘Low‘ corresponds to hit value 0) for bit transmission whereas RS-232 follows the EIA standard
for bit transmission.
 As per the BIA standard, a logic ‘0’ is represented with voltage between +3 and +25V and a logic
‘l’ is represented with voltage between -3 and -25V.
 In EIA standard, logic ‘0’ is known as ‘Space’ and logic ‘1’ as ‘Mark’.
 The RS-232 interface defines various handshaking and control signals for communication apart
from the ‘Transmit’ and ‘Receive' signal lines for data communication.
 RS-232 supports two different types of connectors, namely; DB-9: 9-Pin connector and DB-25:
25-Pin connector.
 Fig 23 illustrates the connector details for DB-9 and DB-25.

Fig 23: DB 9 and DB 25 connectors

 RS-232 is a point-to-point communication interface and the devices involved in RS-232
communication are called “Data Terminal Equipment (DTE)” and “Data Communication
Equipment (DCE)”.
 If no data flow control is required, only TXD and RXD signal lines and ground line (GND) are
required for data transmission and reception.
 The RXD pin of DCE should be connected to the TXD pin of DTE and vice versa for proper data
transmission.
 If hardware data flow control is required for serial transmission, various control signal lines of the
RS-232 connection are used appropriately.
 The control signals are implemented mainly for modem communication and some of them may
not be relevant for other type of devices.
 The Request To Send (RTS) and Clear To Send (CTS) signals co-ordinate the communication
between DTE and DCE.
 Whenever the DTE has a Data To Send, it activates the RTS line and if the DCE is ready to
accept the data, it activates the CTS line.
 The Data Terminal Ready (DTR) signal is activated by DTE when it is ready to accept data.
 The Data Set Ready (DSR) is activated by DCE when it is ready for establishing a
communication link.
 DTR should be in the activated state before the activation of DSR.
 The Data Carrier Detect (DCD) control signal is used by the DCE to indicate the DTE that a
good signal is being received.
 Ring Indicator (RI) is a modem specific signal line for indicating an incoming call on the
telephone line.
 The 25 pin DB connector contains two sets of signal lines for transmit, receive and control lines.
 Now a days DB-25 connector is obsolete and most of the desktop systems are available with DB
9 connectors only.
 As per the EIA standard RS 232 C supports baud rates up to 20Kbps (Upper limit 19.2 Kbps)
The commonly used baud rates by devices are 300bps, l200bps, 2400bps, 9600bps, 11.52Kbps
and 19.2Kbps.
 9600bps is the popular baud rate setting used for PC communication.
 The maximum operating distance supported by RS-232 is 50 feet at the highest supported
baudrate.
 Embedded devices contain a UART for serial communication and they generate signal levels
conforming to TTL CMOS logic.
 A level translator IC like MAX 232 from Maxim Dallas semiconductor is used for converting the
signal lines from the UART to RS-232 signal lines for communication.
 On the receiving side the received data is converted back to digital logic level by a converter IC.
 Convener chips contain converters for both transmitter and receiver.
 Though RS-232 was the most popular communication interface during the olden days, the
advent of other communication techniques like Bluetooth, USB, Fire wire etc are pushing down
RS-232 from the scenes.
 Still RS-232 is popular in certain legacy industrial applications.
 RS-232 supports only point-to-point communication and not suitable for multi-drop
communication.
 It uses single ended data transfer technique for signal transmission and there by more susceptible
to noise and it greatly reduces the operating distance.
 RS-422 is another serial interface standard from EIA for differential data communication.
 It supports data rates up to 100 Kbps and distance up to 400 ft.
 The same RS-232 connector is used at the device end and an RS-232 to RS-422 converter is
plugged in the transmission line.
 At the receiver end the conversion from RS-422 to RS-232 is performed.
 RS-422 supports multi-drop communication with one transmitter device and receiver devices up
to 10.
 RS-485 is the enhanced version of RS-422 and it supports multi-drop communication with up to
32 transmitting devices (drivers) and 32 receiving devices on the bus.
 The communication between devices in the bus uses the ‘addressing’ mechanism to identify
slave devices.

3.4.2.2 Universal Serial Bus (USB)

 Universal Serial Bus (USB) is a wired high speed serial bus for data communication.
 The first version of USB (USB 1.0) was released in 1995 and was created by the USB core group
members consisting of Intel, Microsoft, IBM, Compaq, Digital and Northern Telecom.
 The USB communication system follows a star topology with a USB host at the center and one or
more USB peripheral devices/USB hosts connected to it.
 A USB host can support connections up to 127, including slave peripheral devices and other USB
hosts.
 Fig 24 illustrates the star topology for USB device connection.

Peripheral
Device 2

Peripheral USB Host Peripheral

Device 1 (Hub) Device 3

USB Host
(Hub)

Peripheral Peripheral
Device 4 Device 5

Fig 24: USB Device Connection Topology

 USB transmits data in packet format.
 Each data packet has a standard format.
 The USB communication is a host initiated one.
 The USB host contains a host controller which is responsible for controlling the data
communication, including establishing connectivity with USB slave devices, packetizing and
formatting the data.
 There are different standards for implementing the USB Host Control interface, namely Open
Host Control Interface (OHCI) and Universal Host Control Interface (UHCI).
 USB uses differential signals for data transmission.
 It improves the noise immunity.
 USB interface has the ability to supply power to the connecting devices.
 Two connection lines (Ground and Power) of the USB interface are dedicated for carrying power.
 It can supply power up to 500 mA at 5 V.
 It is sufficient to operate low power devices.
 Mini and Micro USB connectors are available for small form factor devices like portable media
players.
 The pin details for connectors are listed below:

Pin No: Pin Name Description

1 VBUS Carries power (5V)
2 D- Differential data carrier line
3 D+ Differential data carrier line
4 GND Ground signal line

 Each USB device contains a Product ID (PID) and a Vendor ID (VID).

 The PID and VID are embedded into the USB chip by the USB device manufacturer.
 The VID for a device is supplied by the USB standards forum.
 PID and VID are essential for loading the drivers corresponding to a USB device for
communication.
 USB supports four different types of data transfers namely Control, Bulk, Isochronous and
Interrupt.
 Control transfer is used by USB system software to query, configure and issue commands to the
USB device.
 Bulk transfer is used for sending a block of data to a device.
- It supports error checking and correction.
- Ex: Transferring data to a printer
 Isochronous data transfer is used for real-time data communication.
- In Isochronous transfer, data is transmitted as streams in real-time.
- Isochronous transfer doesn’t support error checking and re-transmission of data in case of any
transmission loss.
- All streaming devices like audio devices and medical equipment for data collection make use
of the isochronous transfer.
 Interrupt transfer is used for transferring small amount of data.
 - Interrupt transfer mechanism makes use of polling technique to see whether the USB device
has any data to send.
- The frequency of polling is determined by the USB device and it varies from 1 to 255
milliseconds.
- Uses interrupt transfer devices like Mouse and Keyboard, which transmits fewer amounts of
data.
 USB.ORG (www.usb.org) is the standards body for defining and controlling the standards for
USB communication.
 Presently USB supports four different data rates namely Low Speed (1.5Mbps), Full Speed
(l2Mbps), High Speed (480Mbps) and Super Speed (4.8Gbps).
 The Low Speed and Full Speed specifications are defined by USB 1.0 and the High Speed
specification is defined by USB 2.0.
 USB 3.0 defines the specifications for Super Speed.
 USB 3.0 is expected to be in action by year 2009.
 There is a move happening towards wireless USB for data transmission using Ultra Wide Band
(UWB) technology.
 Some laptops are already available in the market with wireless USB support.

3.4.2.3 IEEE 1394 (Fire wire)

 IEEE 1394 is a wired, isochronous, high speed, serial communication bus.
 It is also known as High Performance Serial Bus (HPSB).
 The research on 1394 was started by Apple Inc. in 1985 and the standard for this was coined by
IEEE.
 The implementation of it is available from various players with different names.
 Apple Inc.’s (www.apple.com) implementation of 1394 protocol is popularly known as Firewire.
 iLINK is the 1394 implementation from Sony Corporation and Lynx is the implementation from
Texas Instruments.
 1394 supports peer-to-peer connection and point-to-multipoint communication allowing 63
devices to be connected on the bus in a tree topology.
 1394 is a wired serial interface and it can support a cable length of up to 15 feet for
interconnection.
 The 1394 standard has evolved a lot from the first version IEEE 1394-1995 released in 1995 to
the recent version IEEE 1394-2008 released in June 2008.
 The 1394 standard supports a data rate of 400 to 3200Mbits.
 The IEEE 1394 uses differential data transfer (The information is sent using differential signals
through a pair of twisted cables).
 It increases the noise immunity and the interface cable supports 3 types of connectors, namely;
4-pin connector, 6-pin connector (alpha connector) and 9 pin connector (beta connector).
 The 6 and 9 pin connectors carry power also to support external devices.
 It can supply unregulated power in the range of 24 to 30V.
 The table given below illustrates the pin details for 4, 6 and 9 pin connectors.
 Pin Pin No: Pin No: Pin No: Description
Name (4 Pin (6 Pin (9 Pin
Connector) Connector) Connector)
Power 1 8 Unregulated DC supply. 24 to 30V

Signal 2 6 Ground connection

Ground

TPB- 1 3 1 Differential Signal line for Signal Line B

TPB+ 2 4 2 Differential Signal line for Signal Line B

TPA- 3 5 3 Differential Signal line for Signal Line A

TPA+ 4 6 4 Differential Signal line for Signal Line A

TPA(S) 5 Shield for the differential signal line A.

Normally grounded

TPB(S) 9 Shield for the differential signal line B.

Normally grounded

NC 7 No connection

 There are two differential data transfer lines A and B per connector.
 In a 1394 cable, normally the differential lines of A are connected to B (TPA+ to TPB+ and TPA-
to TPB~) and vice versa.
 1394 is a popular communication interface for connecting embedded devices like Digital Camera,
Camcorder, and Scanners to desktop computers for data transfer and storage.
 Unlike USB interface (Except USB OTG), IEEE 1394 doesn‘t require a host for communicating
between devices.
 For example, you can directly connect a scanner with a printer for printing.
 The data rate supported by 1394 is far higher than the one supported by USB 2.0 interface.
 The 1394 hardware implementation is much costlier than USB implementation.

3.4.2.4 IrDA (Infrared)

 Infrared (IrDA) is a serial, half duplex, line of sight based wireless technology for data
communication between devices.
 It is in use from the olden days of communication and you may be very familiar with it.
 The remote control of your TV, VCD player etc works on infrared data communication principle.
Infrared communication technique uses infrared waves of the electromagnetic spectrum for
transmitting the data.
 IrDA supports point-point and point-to-multipoint communication, provided all devices involved
in the communication are within the line of sight.
 The typical communication range for IrDA lies in the range 10 cm to 1 m.
 The range can be increased by increasing the transmitting power of the IR device.
 IR supports data rates ranging from 9600bps to 16Mbps.
 Depending on the speed of data transmission IR is classified into Serial IR (SIR), Medium IR
(MIR), Fast IR (FIR), Very Fast IR (VFIR) and Ultra-Fast IR (UFIR).
 SIR supports transmission rates ranging from 9600bps to 115.2kbps.
 MIR supports data rates of 0.576Mbps and 1.152Mbps.
 FIR supports data rates up to 4Mbps.
 VFIR is designed to support high data rates up to 16Mbps.
 The UFIR specs are under development and it is targeting a data rate up to l00Mbps.
 IrDA communication involves a transmitter unit for transmitting the data over IR and a receiver
for receiving the data.
 Infrared Light Emitting Diode (LED) is the IR source for transmitter and at the receiving end
a photodiode acts as the receiver.
 Both transmitter and receiver unit will be present in each device supporting IrDA communication
for bidirectional data transfer.
 Such IR units are known as ‘Transceiver’.
 Certain devices like a TV remote control always require unidirectional communication and so
they contain either the transmitter or receiver unit (The remote control unit contains the transmit.
per unit and TV contains the receiver unit).
 ‘Infrared Data Association’ (IrDA https://www.irda.org/) is the regulatory body responsible for
defining and licensing the specifications for IR data communication.
 IrDA communication has two essential parts a physical link part and a protocol part.
 The physical link is responsible for the physical transmission of data between devices supporting
IR communication and protocol part is responsible for defining the rules of communication.
 The physical link works on the wireless principle making use of Infrared for communication.
 The IrDA specifications include the standard for both physical link and protocol layer.
 The IrDA control protocol contains implementations for Physical Layer (PHY), Media Access
Control (MAC) and Logical Link Control (LLC).
 The Physical Layer defines the physical characteristics of communication like range, data rates,
power etc.
 IrDA is a popular interface for file exchange and data transfer in low cost devices.
 IrDA was the prominent communication channel in mobile phones before Bluetooth’s existence.
 Even now most of the mobile phone devices support IrDA.

3.4.2.5 Bluetooth (BT)

 Bluetooth is a low cost, low power, short range wireless technology for data and voice
communication.
 Bluetooth was first proposed by ‘Ericsson’ in 1994.
 Bluetooth operates at 2.4GHz of the Radio Frequency spectrum and uses the Frequency Hopping
Spread Spectrum (FHSS) technique for communication.
 Literally it supports a data rate of up to 1Mbps and a range of approximately 30 feet for data
communication.
 Like IrDA, Bluetooth communication also has two essential parts; a physical link part and a
protocol part.
 The physical link is responsible for the physical transmission of data between devices supporting
Bluetooth communication and protocol part is responsible for defining the rules of
communication.
 The physical link works on the wireless principle making use of RF waves for communication.
 Bluetooth enabled devices essentially contain a Bluetooth wireless radio for the transmission and
reception of data.
 The rules governing the Bluetooth communication is implemented in the ‘Bluetooth protocol
stack’.
 The Bluetooth communication IC holds the stack.
 Each Bluetooth device will have a 48 bit unique identification number.
 Bluetooth communication follows packet based data transfer.
 Bluetooth supports point-to-point (device to device) and point-to-multipoint (device to multiple
device broadcasting) wireless communication.
 The point-to-point communication follows the master slave relationship.
 A Bluetooth device can function as either master or slave.
 When a network is formed with one Bluetooth device as master and more than one device as
slaves, it is called a Piconet.
 A Piconet supports a maximum of seven slave devices.
 Bluetooth is the favourite choice for short range data communication in handheld embedded
devices.
 Bluetooth technology is very popular among cell phone users as they are the easiest
communication channel for transferring ringtones, music files, pictures, media files, etc. between
neighboring Bluetooth enabled phones.
 The Bluetooth standard specifies the minimum requirements that a Bluetooth device must
support for a specific usage scenario.
 The Generic Access Profile (GAP) defines the requirements for detecting a Bluetooth device and
establishing a connection with it.
- All other specific usage profiles are based on GAP.
 Serial Port Profile (SPP) for serial data communication, File Transfer Profile (FTP) for file
transfer between devices, Human Interface Device (HID) for supporting human interface devices
like keyboard and mouse are examples for Bluetooth profiles.
 The specifications for Bluetooth communication is defined and licensed by the standards body
‘Bluetooth Special interest Group (SIG)’.
 For more information, please visit the website www.bluetooth.org.

3.4.2.6 WI-FI
 Wi-Fi or Wireless Fidelity is the popular wireless communication technique for networked
communication of devices.
 Wi-Fi follows the IEEE 802.11 standard.
 Wi-Fi 1s intended for network communication and it supports Internet Protocol (IP) based
communication.
 It is essential to have device identities in a multipoint communication to address specific devices
for data communication.
 In an IP based communication each device is identified by an IP address, which is unique to
each device on the network.
 Wi-Fi based communications require an intermediate agent called Wi-Fi router/Wireless Access
point to manage the communications.
 The Wi-Fi router is responsible for restricting the access to a network, assigning IP address to
devices on the network, routing data packets to the intended devices on the network.
 Wi-Fi enabled devices contain a wireless adaptor for transmitting and receiving data in the form
of radio signals through an antenna.
 The hardware part of it is known as Wi-Fi Radio.
 Wi-Fi operates at 2.4GHz or 5GHz of radio spectrum and they co-exist with other ISM band
devices like Bluetooth.
 Fig 25 illustrates the typical interfacing of devices in a Wi-Fi network.
Wi-Fi Router

Device 1
Device 2 Device 3

Fig 25: WI FI network

 For communicating with devices over a Wi-Fi network, the device when its Wi-Fi radio is turned
ON, searches the available Wi-Fi network in its vicinity and lists out the Service Set Identifier
(SSID) of the available networks.
 If the network is security enabled, a password may be required to connect to a particular SSID.
 Wi-Fi employs different security mechanisms like Wired Equivalency Privacy (WEP) Wireless
Protected Access (WPA), etc. for securing the data communication.
 Wi-Fi supports data rates upto 150Mbps (Growing towards higher rates as technology
progresses) depending on the standards (802.11a/b/g/n) and access/modulation method.
 Depending on the type of antenna and usage location (indoor/outdoor), Wi-Fi offers a range of
100 to 300 feet.

3.4.2.7 ZigBee
 ZigBee is a low power, low cost, wireless network communication protocol based on the IEEE
802.15.4-2006 standard.
 ZigBee is targeted for low power, low data rate and secure applications for Wireless Personal
Area Networking (WPAN).
 The ZigBee specifications support a robust mesh network containing multiple nodes.
 This networking strategy makes the network reliable by permitting messages to travel through a
number of different paths to get from one node to another.
 ZigBee operates worldwide at the unlicensed bands of Radio spectrum, mainly at 2.400 to 2.484
GHZ, 902 to 928 MHz and 868.0 to 868.6MHz.
 ZigBee Supports an operating distance of up to 100 meters and a data rate of 20 to 250kbps.
ZED ZED

ZED

ZR ZC ZR

ZED ZED

Fig 26: Zigbee network model

 ZigBee Coordinator (ZC)/Network Coordinator: The ZigBee coordinator acts as the root of
the ZigBee network.
- The ZC is responsible for initiating the ZigBee network and it has the capability to Store
information about the network.
 ZigBee Router (ZR)/Full function Device (FFD): Responsible for passing information from
device to another device or to another ZR.
 ZigBee End Device (ZED)/Reduced Function Device (RFD): End device containing ZigBee
functionality for data communication.
- It can talk only with a ZR or ZC and doesn’t have the capability to act as a mediator for
transferring data from one device to another.
 ZigBee is primarily targeting application areas like Home & Industrial Automation, Energy
Management, Home control/security, Medical/Patient tracking, Logistics & Asset tracking and
sensor networks & active RFID.
 Automatic Meter Reading (AMR), smoke and detectors, wireless telemetry, HVAC control,
heating control, Lighting controls, Environmental controls, etc are examples for applications
which can make use of the ZigBee technology.

3.4.2.8 General Packet Radio Service (GPRS)

 It is a communication technique for transferring data over a mobile communication network like
GSM.
 Data is sent as packets. The transmitting device splits the data into several related packets. At
the receiving end the data is re-constructed by combining the received data packets.
 Supports maximum transfer rate of 171.2kbps.
 The radio channel is concurrently shared between several users instead of dedicating a radio
channel to a cell phone user.
 The GPRS communication divides the channel into 8 timeslots and transmits data over the
available channel
 GPRS supports Internet Protocol (IP), Point to Point Protocol (PPP) and X.25 protocols for
communication.
 GPRS is mainly used by mobile enabled embedded devices for data communication. The device
should support the necessary GPRS hardware like GPRS modem and GPRS radio
 GPRS is an old technology and it is being replaced by new generation data communication
techniques like EDGE, High Speed Downlink Packet Access (HSDPA) etc which offers higher
bandwidths for communication

3.5 EMBEDDED FIRMWARE

 Embedded firmware refers to the control algorithm (Program instructions) and or the
configuration settings that an embedded system developer dumps into the code (Program)
memory of the embedded system.
 It is an un-avoidable part of an embedded system. There are various methods available for
developing the embedded firmware.
 They are listed below.
1. Write the program in high level languages like Embedded C/C++ using an Integrated
Development Environment. The IDE will contain an editor, compiler, linker, debugger,
simulator, etc.
- IDEs are different for different family of processors/controllers.
- For example, Keil micro vision 3 IDE is used for all family members of 8051 microcontroller,
since it contains the generic 8051 compiler C51.
2. Write the program in Assembly language using the instructions supported by your
application’s target processor controller.
- The instruction set for each family of processor/controller is different and the program written
in either of the methods given above should be converted into a processor understandable
machine code before loading it into the program memory.
- The process of converting the program written in either a high level language or
processor/controller specific Assembly code to machine readable binary code is called HEX
File Creation.
- The methods used for HEX File Creation is different depending on the programming
techniques used.
- If the program is written in Embedded C/C++ using an IDE, the cross compiler included in
the IDE converts it into corresponding processor/controller understandable ‘HEX File’.
- If you are following the Assembly language based programming technique (method 2), you
can use the utilities supplied by the processor/controller vendors to convert the source code
into HEX File.
- Also third party tools are available, which may be of free of cost, for this conversion.
 For a beginner in the embedded software field, it is strongly recommended to use the high level
language based development technique.
 The reasons for this being writing codes in a high level language is easy, the code written in
high level language is highly portable which means you can use the same code to run on
different processor/controller with little or less modification.
 The only thing you need to do is re-compile the program with the required processor’s IDE, after
replacing the include files for that particular processor.
 Also the programs written in high level languages are not developer dependent.
 Any skilled programmer can trace out the functionalities of the program by just having a look
at the program.
 It will be much easier if the source code contains necessary comments and documentation lines.
 It is very easy to debug and the overall system development time will be reduced to a greater
extent.
 The embedded software development process in assembly language is tedious and time
consuming.
 The developer needs to know about all the instruction sets of the processor/controller or at least
it should carry an instruction set reference manual with her/him.
 A programmer using assembly language technique writes the program according to his/her view
and taste.
 Often he/she may be writing a method or functionality which can be achieved through a single
instruction as an experienced person’s point of view, by two or three instructions in his/her own
style.
 So the program will be highly dependent on the developer.
 It is very difficult for a second person to understand the code written in Assembly even if it is
well documented.
 Two types of control algorithm design exist in embedded firmware development.
 The first type of control algorithm development is known as the infinite loop or ‘super loop’
based approach, where the control flow runs from top to bottom and then jumps back to the top of
the program in a conventional procedure.
- It is similar to the while (1) { }; based technique in C.
 The second method deals with splitting the functions to be executed into tasks and running these
tasks using a scheduler which is part of a General Purpose or Real Time Embedded Operating
System (GPOS/RTOS).

3.6 OTHER SYSTEM COMPONENTS

 The other system components refer to the components/circuits/ICs which are necessary for the
proper functioning of the embedded system.
 Some of these circuits may be essential for the proper functioning of the processor/controller and
firmware execution.
 Watchdog timer, Reset IC (or passive circuit), brown-out protection 1C (or passive circuit) etc
are examples of circuits/1Cs which are essential for the proper functioning of the
processor/controllers.
 Some of the controllers or SOC’s integrate these components within a single IC and doesn’t
require such components externally connected to the chip for proper functioning.
 Depending on the system requirement, the embedded system may include other integrated circuits
for performing specific functions, level translator ICs for interfacing circuits with different logic
levels, etc.
 The following section explains the essential circuits for the proper functioning of the
processor/controller of the embedded system.

3.6.1 Reset Circuit

 The reset circuit is essential to ensure that the device is not operating at a voltage level where
the device is not guaranteed to operate, during system power ON.
 The reset signal brings the internal registers and the different hardware systems of the
processor/controller to a known state and starts the firmware execution from the reset vector
(Normally from vector address 0x0000 for conventional processors/controllers. The reset vector
can be relocated to an address for processors/controllers supporting bootloader).
 The reset signal can be either active high (The processor undergoes reset when the reset pin of
the processor is at logic high) or active low (The processor undergoes reset when the reset pin of
the processor is at logic low).
 Since the processor operation is synchronized to a clock signal, the reset pulse should be wide
enough to give time for the clock oscillator to stabilize before the internal reset state starts.
 The reset signal to the processor can be applied at power ON through an external passive reset
circuit comprising a Capacitor and Resistor or through a standard Reset IC like MAX810 from
Maxim Dallas.
 Select the reset IC based on the type of reset signal and logic level (CMOS/TTL) supported by
the processor/controller in use.
 Some microprocessors/controllers contain built-in internal reset circuitry and they receive
external reset circuitry.
 Fig 27 illustrates a Resistor capacitor based passive reset circuit for active high and low
configuration:

Fig 27: RC based Reset Circuit

3.6.2 Brown-out Protection Circuit

 Brown-out protection circuit prevents the processor/controller from unexpected program
execution behavior when the supply voltage to the processor/controller falls below a specified
voltage.
 It is essential for battery powered devices since there are greater chances for the battery voltage
to drop below the required threshold.
 The processor behavior may not be predictable if the supply voltage falls below the
recommended operating voltage.
 It may lead to situations like data corruption.
 A brown-out protection circuit holds the processor/controller in reset state, when the operating
voltage falls below the threshold, until it rises above the threshold voltage.
 Certain processors/controllers support built in brown-out protection circuit which monitors the
supply voltage internally.
 If the processor/controller doesn’t integrate a built-in brown-out protection circuit, the same can
be implemented using external passive circuits or supervisor ICs.
 Fig 28 illustrates a brown-out circuit implementation using Zener diode and transistor for
processor/controller with active low Reset Logic.
 The Zener diode Dz and transistor Q forms the heart of this circuit.
 The transistor conducts always when the supply voltage Vcc is greater than that of the sum of
VBE and Vz (Zener voltage).
 The transistor stops conducting when the supply voltage falls below the sum of VBE and Vz.
 Select the Zener diode with required voltage for setting the low threshold value for Vcc.
 The values of R1, R2, and R3 can be selected based on the electrical characteristics of the
transistor in use.
 Microprocessor Supervisor like D81232 from Maxim Dallas also provides Brown-out protection.

Vcc

R1

V BE
R2
Q

Reset Pulse
DZ Active Low
Vz

R3

GND

Fig 28: Brownout protection circuit with active low outpu

3.6.3 Oscillator Unit

 A microprocessor/microcontroller is a digital device made up of digital combinational and
sequential circuits.
 The instruction execution of a microprocessor/controller occurs in sync with a clock signal.
 It is analogous to the heartbeat of a living being which synchronizes the execution of life.
 For a living being the heart is responsible for the generation of the beat whereas the oscillator unit
of the embedded system is responsible for generating the precise clock for the processor.
 Certain processors/controllers integrated a built-in oscillator unit and simply require an external
ceramic resonator/quartz crystal for producing the necessary clock signals.
 Quartz crystals and ceramic resonators are equivalent in operation, however they possess
physical difference.
 A quartz crystal is normally mounted in a hermetically sealed meal case with two leads
protruding out of the case Certain devices may not contain a built-in oscillator unit and require
the clock pulses to be generated and supplied externally.
 Quartz crystal Oscillators are available in the form chips and they can be used for generating
the clock pulses in such a cases.
 The Speed of operation of a processor is primarily dependent on the clock frequency.
 However we cannot increase the clock frequency blindly for increasing the speed of execution.
 The logical circuits lying inside the processor always have an upper threshold value for the
maximum clock at which the system can run, beyond which the system becomes unstable and
non-functional.
 The total system power consumption is directly proportional to the clock frequency.
 The power consumption increases with increase in clock frequency.
 The accuracy of program execution depends on the accuracy of the clock signal.
 The accuracy of the crystal oscillator or ceramic resonator is normally expressed in terms of +/-
ppm (Parts per million).
 Fig 29 illustrates the usage of quartz crystal/ceramic resonator and external oscillator chip for
clock generation.

Microcontroller Microprocessor
C : Capacitor
Y : Resonator

Crystal Oscillator
Oscillator
Unit
Quartz Crystal Clock Input Pin
Resonator C C
Y Oscillator
Unit

Fig 29: Oscillator circuitry using quartz crystal and quartz crystal oscillator
3.6.4. Real-Time Clock (RTC)
 Real-Time Clock (RTC) is a system component responsible for keeping track of time.
 RTC holds information like current time (In hours, minutes and seconds) in 12 hour/24 hour
format, date, month, year, day of the week etc and supplies timing reference to the system.
 RTC is intended to function even in the absence of power.
 RTCs are available in the form of Integrated Circuits from different semiconductor manufacturers
like Maxim/Dallas, ST Microelectronics etc.
 The RTC chip contains a microchip for holding the time and date related information and
backup battery cell for functioning in the absence of power, in a single 1C package.
 The RTC Chip is interfaced to the processor or controller of the embedded system.
 For Operating System based embedded devices, a timing reference is essential for synchronizing
the operations of the OS kernel.
 The RTC can interrupt the OS kernel by asserting the interrupt line of the processor/controller
to which the RTC interrupt line is connected.
 The OS kernel identifies the interrupt in terms of the Interrupt Request (IRQ) number
generated by an interrupt controller.
 One IRQ can be assigned to the RTC interrupt and the kernel can perform necessary Operations
like system date/time updating, managing software timers etc when an RTC timer tick interrupt
occurs.
 The RTC can be configured to interrupt the processor at predefined intervals or to interrupt the
processor when the RTC register reaches a specified value (used as alarm interrupt).

3.6.5 Watchdog Timer

 In desktop Windows systems, if we feel our application is behaving in an abnormal way or if the
system hangs up, we have the ‘Ctrl + Alt + Del’ to come out of the situation.
 What if it happens to our embedded system? Do we really have a ‘Ctrl + Alt + Del’ to take
control of the situation?
 Of course not, but we have a watchdog to monitor the firmware execution and reset the system
processor/microcontroller when the program execution hangs up.
 A watchdog timer, or simply a watchdog, is a hardware timer for monitoring the firmware
execution.
 Depending on the internal implementation, the watchdog timer increments or decrements a
free running counter with each clock pulse and generates a reset signal to reset the processor
if the count reaches zero for a down counting watchdog, or the highest count value for an up
counting watchdog.
 If the watchdog counter is in the enabled state, the firmware can write a zero (for upcounting
watchdog implementation) to it before starting the execution of a piece of code (subroutine or
portion of code which is susceptible to execution hang up) and the watchdog will start counting.
 If the firmware execution doesn’t complete due to malfunctioning, within the time required by
the watchdog to reach the maximum count, the counter will generate a reset pulse and this will
reset the processor to the watchdog timer register.
 Most of the processors implement watchdog as a built-in component and provides status
register to control the watchdog timer (like enabling and disabling watchdog functioning) and
watchdog timer register for writing the count value.
 If the processor/controller doesn’t contain a built in watchdog timer, the same can be
implemented using an external watchdog timer IC circuit.
 The external watchdog timer uses hardware logic for enabling/disabling, resetting the watchdog
count etc instead of the firmware based ‘writing’ to the status and watchdog timer register.
 The Microprocessor supervisor IC DS 1232 integrates a hardware watchdog timer in it.
 In modern systems running on embedded operating systems, the watchdog can be implemented
in such a way that when a watchdog timeout occurs, an interrupt is generated instead of resetting
the processor.
 The interrupt handler for this handles the situation in an appropriate fashion.
 Fig 30 illustrates the implementation of an external watchdog timer based microprocessor
supervisor circuit for a small scale embedded system.
 Fig 30: Watchdog timer for firmware execution supervision

3.7 PCB AND PASSIVE COMPONENTS

 Printed Circuit Board (PCB) is the backbone of every embedded system.

 After finalizing the component and the inter-connection among them, a schematic design is
created and according to the schematic PCB is fabricated.
 PCB acts as a platform for mounting all the necessary components as per the design
requirement. Also it acts as a platform for testing the embedded firmware.
 Apart from the above-mentioned important subsystems of an embedded system, some passive
electronic components like resistor, capacitor, diodes, etc can be seen on the board in Fig 31.
 They are the co-workers of various chips contained in embedded hardware.
 They are very essential for the proper functioning of embedded system.
 For example for providing a regulated ripple-free supply voltage to the system, a regulator IC
and spike suppressor filter capacitors are very essential.

Fig 31: PCB

QUESTION BANK
1. Explain the 6 purposes of embedded systems with an example for each. (4)
2. Differentiate between (i) General Computing Systems and Embedded Systems and (ii) RISC
and CISC architectures. (4)
3. Explain the 3 classifications of embedded systems based on complexity and performance. (6)
4. Mention the applications of embedded systems with an example for each. (4)
5. Explain the functions of opto coupler and SPI bus with diagrams. (3)
6. Write a note on embedded firmware (4)
7. Explain SRAM design and features with a diagram. (6)
8. Mention the role of watch dog timer in embedded system with relevant examples. (5)
9. Discuss the I2C communication interface with neat diagram. (5)
10. Elaborate the working of SPI bus with a neat interfacing diagram. (6)
11. Compare PLD, ASIC and COTS. (5)
12. Explain the working of a relay driver with a diagram. (4)
13. Explain operation of UART. Compare UART and USB. (4)
14. Compare serial and parallel communication. (4)
15. List various purposes of an embedded systems. (3)
16. Write a note on 1-wire bus .Explain its advantage and disadvantages.(4)
17. Write a note on embedded firmware. (5)
18. Explain the significance of reset and brown out protection circuits and their applications in
embedded system. (5)