•

~:-:~~~ RT Personal Computer Technology

Form No. SA23-1057

Foreword Copyright

IBM RT Personal Computer Technology is a A variety of structures and levels of detail ©Copyright International Business Machines
collection of papers by the developers of the may exist in the papers because they were Corporation, 1986. Inquiries related to
RT PC. These papers describe the innovative written as technical articles by different permission to republish an article in full or in
aspects of the RT PC-what we set out to specialists. In order to preserve their part should be directed to the IBM
build, how we built it, and how it works today. authenticity and vitality, the papers have not Corporation, IBM Austin, 854/003, 11400
The papers were written by technical been revised for consistency of style or Burnet Road, Austin, TX 78758.
professionals for readers who are conversant method of presentation. These papers will not
with the vocabulary and concepts of be updated to incorporate future Copies of this book, SA23-1 057, can be
computers and programming. developments. obtained from the local IBM branch office.
IBM employees can order copies from
This book is a one-time statement by the This book is the work of many hands, but Mechanicsburg.
developers for historical and background special acknowledgment is due to Bert Buller
purposes. Although there are several of the Hardware Architecture Group for Cover: An IBM RT Personal Computer Model
overview articles that describe how the coordinating the engineering articles, and to 10 with a larger and somewhat faster
various components work together, the Herb Michaelson, Publications Consultant, for ancestor in the background-an IBM System!
emphasis is on the novel parts of the RT PC shaping both the book and the individuai 370 Model 158 MP.
system. IBM RT Personal Computer articles.
Technology is intended to supply the reader
with an understanding of the things that make Frank Waters, Editor
the RT PC unique, not to provide detailed
descriptions of all of the elements of the
RT PC system.

The papers in this book are not intended to

replace IBM publications in describing the
capabilities of the system components and
how to use them. Keep in mind that the
papers are for general technical
communication purposes; they do not
represent an IBM warranty or commitment to
specific capabilities in the referenced
products.
Preface

Introducing a new architecture to the • a resource manager to provide virtual The development of the RT PC system has
computer marketplace is never done casually. machine, storage, and 1/0 functions and to been a mUlti-location effort. We have
The cost and effort of transition from one ensure data integrity and processing incorporated architectural advances from
architecture to another must be justified by continuity, Yorktown Heights, technology innovations
substantial advantages. It is always tempting from Burlington, graphics peripherals and
to apply advances in technology to improving • a multitasking, multiuser operating system applications from Kingston, and engineering
the performance of existing architectures. that can be tailored to make the RT PC and programming developments from Austin.
Ultimately, however, refinement is subject to suitable for a variety of user requirements, The RT PC has been the work of hundreds of
the law of diminishing returns. Continuing individuals, both within and outside of IBM.
advancement requires fundamental changes. • a coprocessor feature that allows users to The articles in this book describe some of
run programs written for the IBM PC their contributions. I want to convey to
The hardware and software architectures that without interfering with the normal everyone involved my gratitude for their
were originally created for personal operation of the RT PC, efforts and my respect for their
computers had to accommodate the speed accomplishments.
and size constraints of the processors and • and a wide variety of displays, printers,
storage devices that were available at the communications adapters, and processing W. Frank King
time. Techniques that were known to be features, Group Director of Advanced Engineering
effective on mainframes and minicomputers Systems Development
were simply too costly to implement on • in a box that fits on or under a desk. Engineering Systems Products
personal computers. Our intent in designing independent Business Unit
the RT PC has been to use recent With the RT PC, the architectural
technological and architectural advances to sophistication of the personal computer has
avoid the structural limitations of earlier caught up with that of the mainframe.
designs. Perhaps more important, we have laid a
foundation for more efficient exploitation of
The IBM RT PC is a new synthesis of future advances in both hardware and
computer concepts. It combines: software technology. The open-ended ness of
the resource manager and operating system
• A very fast Reduced Instruction Set 32-bit at all levels means that we can easily take
processor for efficient execution of advantage of new applications, devices, and
programs compiled from a higher-level communications techniques.
language,

Ii
 --
- --
---
RT Personal Computer Technology ~ : :i~~
IBM Product Design and Development
®

Engineering Systems Products

Contents

IBM RT PC Architecture and Design Decisions G. Glenn Henry 2

Hardware Description P.O. Hester, J.T. Hollaway, and F.T. May 6

Processor Card D.E. Waldecker, K.G. Wilcox, J.R. Barr, 12

W.T. Glover, C.G. Wright, H. Hoffman

System Memory Cards Ronald E. Rowland 18

Floating Point Accelerator Scott M. Smith 21

System Board and I/O Channel for the IBM RT PC Sheldon L. Phelps and John D. Upton 26
System

IBM RT PC Displays and Adapters Joe C. St. Clair 31

Use of Artificial Intelligence to Diagnose Nancy A. Burns and C. Edward Williams 35

Hardware

Manufacturing Innovations to Increase Quality Charles W. Bartlett, A.V. Burghart, 40

and Reduce Cost George M. Yanker

ROMP/MMU Technology Introduction D.E. Waldecker and P.Y. Woon 44

The IBM RT PC ROMP and Memory Management P.O. Hester, Richard O. Simpson, 48
Unit Architecture Albert Chang

ROMP/MMU Implementation D.E. Waldecker, C.G. Wright, 57

M.S. Schmookler, T.G. Whiteside,
R.D. Groves, C.P. Freeman, A. Torres

iii
ROMP/MMU Circuit Technology and Chip Design Raymond A. DuPont, Ed Seewann, 66
Peter McCormick, Charles K. Erdelyi,
Mukesh P. Patel, P.T. Patel

Software Development Tools for ROMP Alan MacKay and Ahmed Chi bib 72

Compiling for the RT PC ROMP M.E. Hopkins 76

Advanced Interactive Executive (AIXTM) Larry Loucks 83

Operating System Structure

Restructuring the AIX User Interface P.J. Kilpatrick and Carolyn Greene 88

Configuration Methods for a Personal Computer Shirley Lerom, Lee Terrell, and Hira Advani 91
System

IBM RT PC AIX Kernel - Modifications and Larry Loucks 96

Extensions

Extendable High-Level AIX User Interface Tom Murphy and Dick Verburg 110

Extended File Management for AIX John M. Bissell 114

The Virtual Resource Manager Thomas G. Lang, Mark S. Greenberg, and 119
Charles H. Sauer

Design of the IBM RT PC Virtual Memory Manager J.C. O'Quin, J.T. O'Quin, Mark D. Rogers, 126
T.A. Smith

The IBM RT PC Subroutine Linkage Convention J.C.O'Quin 131

Implementation of a Virtual Terminal Subsystem D.C. Baker, G.A. Flurry, K.D. Nguyen 134

Use of a Coprocessor for Emulating the PC AT John W. Irwin 137

Coprocessor Software Support Rajan Krishnamurty and Terry Mothersole 142

PC DOS Emulation in the AIX Environment Leonard F. Brissette, Roy A. Clauson, 147
Jack E. Olson

Authors 149

iv
Reader's Guide

The IBM RT Personal Computer Technology Overview Articles Operating System Modifications and
book is divided into four parts. The first Henry 2 Extensions
describes the main hardware elements of the Hester et al. 6 Loucks 83
RT PC system. The second section discusses Waldecker and Woon 44 Loucks 96
the RT PC's 32-bit microprocessor. The third Loucks 83 Bissell 114
section covers the RT PC software and the O'Quin 131
fourth the PC AT coprocessor and AIX's PC Major Hardware Components
DOS emulation functions. Waldecker et al. 12 Virtual Resource Manager
Rowland 18 Lang et al. 119
A reader's guide, for a topical approach to Smith 21 O'Quin et al. 126
this book, is as follows: Phelps and Upton 26 Baker et al. 134
St. Clair 31 Brissette et al. 147

RT PC Microprocessor PC AT Coprocessor
Waldecker and Woon 44 Irwin 137
Hester et al. 48 Krishnamurty and Mothersole 142
Waldecker et al. 57
DuPont et al. 66

User Interface
Kilpatrick and Greene 88
Lerom et al. 91
Murphy and Verburg 110
Brissette et al. 131

1
IBM RT PC Architecture and Design Decisions

G. Glenn Henry

Introduction In addition to these technical objectives, there

Ported Applications / New Applications
The architect of a new system must start by were a number of important practical
making a series of high-level decisions about requirements relative to producing a Application
D I t
lEt d d 0
x en e
r : PC C
pera Ing . ..
the hardware and software structure. These successful product: e~~ ?pmen I System Functions I ompatlblhty
__ .£~h~S_ _ _ .1. _______ ..1 ________
early choices shape all of the ultimate details
of the product. An understanding of the • Easy portability of existing IBM and non- Base Operating System

"reasons why" is important to the person IBM applications

who is trying the understand the resulting VRM
system. In this paper, I will give a very • Easy migration of users and their
general overview of the structure of the RT applications and data from existing systems Processor and Memory
PC AT Coprocessor
PC and explain the rationale for each of the Management Unit
major decisions that dictated that structure. • The ability to take advantage of I/O
attachments and devices used on other I/O Channel and Devices
Product Objectives systems
The original objective of the project that
Figure 1 Logical Structure of the RT PC
resulted in the RT PC was to build a high- • Straightforward ways for other IBM and
function workstation with capabilities far non-IBM development areas to add and
beyond those of personal computers. modify system functions (Le., an "open" interfaces that are compatible with other
Specifically required were: system). systems, and IBM-exclusive technology. It is
this combination of appioaches that allows
• A high-performance 32-bit processor These challenging and, in some cases, the RT PC to meet its sometimes conflicting
conflicting objectives, when combined with objectives.
• Large amounts of primary and secondary available technology, shaped the system
storage design as described in the following sections. I/O Channel and Devices
The I/O structure chosen for the RT PC was
• High-function virtual storage capabilities System Structure basically the PC AT 16-bit I/O Channel, with
Figure 1 shows the logical structure resulting some performance improvements. This choice
• High-function APA display devices from the objectives and design systems. makes it possible to use most of the existing
PC AT I/O attachment cards, while providing
• A full-function, multi-tasking operating Figure 2 provides a more detailed look at the acceptable levels of I/O performance with
system structure of the RT PC from a physical native RT PC I/O devices. While providing
viewpoint. As you will see, the specifics of the compatibility with the PC AT, the RT PC I/O
• A high degree of usability system components reflect "something old, channel provides more usable capacity to I/O
something new, something borrowed, and devices, since processor RAM is not
• A flexible, extendable, and open something Blue." The RT PC includes proven connected to the I/O channel and the RT PC
architecture. technologies and functions, innovations,

2
 Applications preponderance of code expected to be hardware of the machine. The VRM presents
Application Development Products
executed on the RT PC was anticipated to operating systems with a Virtual Machine
be generated by compilers), Interface (VMI) that not only conceals the
AIX Kernel
complexities of virtual memory management
VRM
• on a single chip for a low-cost, high- and numerous I/O device types, but provides
performance solution, the operating system with a significantly more
Processor MMU powerful set of functions than are available
System RAM • with an associated MMU chip providing on the bare machine. It is therefore not
advanced virtual storage capabilities, accurate to think of the VRM as a pure
hypervisor, like VM/370. The VMI is, in effect,
• and finally, there was no vendor a higher-level machine to which guest
PC AT
microprocessor available with the full set of operating systems can be converted. We
Disk Coprocessor these capabilities. considered the VRM necessary because:

The IBM ROMP is a single-chip derivative of • The operating system base that we wanted
Display Other I/O
the 801 processor project of IBM Research to use for the RT PC was not built to run
and thus benefits from the processor on a computer with virtual memory, did not
Figure 2 Physical Structure of the RT PC architecture analysis and advanced compiler provide real-time I/O capabilities, and didn't
architecture design activities associated with provide dynamic install and configuration
I/O Channel Controller includes performance- the 801. In addition, the IBM ROMP has functions. We decided to provide these
assist features such as 32-bit "assembly" special features such as "Load Multiple" and important functions "under" the operating
burst transfer. "Store Multiple" that extend the RISC system, as opposed to making extensive
architecture approach to provide increased modifications to the kernel of the existing
Processor and MMU efficiency and performance in a operating system. For example, the VRM
The most critical choice was obviously that of microprocessor implementation. provides a very fast preemptive interrupt-
the processor and associated Memory based I/O structure, virtual storage
Management Unit (MMU). In spite of the The virtual storage functions provided by the management functions, and dynamic
obvious implications of the objective to ease MMU chip are very powerful. For example, loading and binding of I/O device drivers.
migration of existing applications, we chose a the 32-bit processor address is extended to a This allows, for example, the operating
new processor-the IBM Research/OPD 40-bit virtual address with a high- system kernel to be paged and complex,
Microprocessor (ROMP). performance, hardware-managed "inverted" multi-tasking I/O device drivers to be
page table translation approach. This implemented.
The major reasons for choosing the IBM significantly reduces the size of the page
ROMP were: tables for the large virtual address space • We wanted to achieve a higher degree of
while providing very fast virtual-to-physical program isolation from the hardware details
• It provides a full 32-bit architecture, address translation. Even today, I do not than is possible with the current personal
know of another M MU that provides this level computer operating systems. That is, the
• with high performance (approximately 2 of function and performance. VRM resembles BIOS on the IBM PC, but it
MIPs), provides a much higher level of hardware
Virtual Resource Manager independence. For example, generic device
• using a Reduced Instruction Set Computer When designing the software structure for the classes are supported at the VMI, allowing
(RISC) architecture making it particularly RT PC, we decided to build a Virtual high levels of device transparency and I/O
suitable as a target for compilers (the Resource Manager (VRM) to control the real redirection.

3
• We wanted to allow hardware coprocessors functional power to the individual user, system utility functions such as "cp" to
to execute concurrently with ROMP without provides multi-user capabilities where needed, transparently operate on composite data
making major changes to the existing base is open-ended, and has a large user and management objects consisting of an index
and with minimal overhead for resource application base. We concluded that AT&T's file and a data file)
allocation and management (see PC System V suited our purposes better than
Compatibility, below). alternative UNIXes because of the larger • Extensions to exploit use of the powerful
number of applications that had been built to virtual storage support; in particular,
• We needed to isolate the development of run on that base, as well as for a variety of mapped file support which allows an
the RT PC software from changing practical reasons. application to "map" a file into a 256
hardware characteristics during the megabyte virtual address space, and
development process. While this was an In choosing UNIX, however, we accepted the access it with loads and stores, versus
"internal" IBM requirement, the success of need to make significant extensions and reads and writes (a derivative is used by
the VRM in meeting this goal validates its enhancements to meet the needs of our the system to provide mapped text segment
architecture and implementation features expected customers and target applications. support, allowing paging "in place").
relative to providing high levels of hardware This is, of course, the classical trade-off
transparency to the user software. between choosing an existing software • Enhanced signals to allow flexible
system for its pragmatic characteristics exception-condition handling
Consistent with the objectives for a flexible versus developing a new system with
and open system, the VRM provides complete (hopefully) fewer deficiencies but limited • A variety of floating point support functions
facilities for the user to implement and install applications and user familiarity. We chose to
code in the VRM. That is, the detailed start with UNIX and fix the deficiencies while • Simplified installation and configuration
hardware structure is isolated from software retaining upward compatibility for all UNIX processes.
in the preponderance of cases where that is System V interfaces.
desirable, but conversely, all hardware details PC Compatibility
are available to user functions that require Some of the major enhancements made were: In addition to UNIX application portability, our
them. original objective of eaSing user and
• A Usability package to provide easier application migration required a high level of
Operating System and Extensions access to the capabilities of the UNIX compatibility with the IBM PC family. This was
As the base for the RT PC's Advanced command language and to simplify the provided by:
Interactive Executive (AIX1) operating system, implementation of full-screen dialogs
we chose AT&T's UNIX2 System V3 • We • An IBM PC AT hardware coprocessor that
chose UNIX because it provides considerable • Multiple, full-screen virtual terminal support includes an Intel 80286 along with
to permit a single user to run several associated hardware to provide a high level
1 "Aix" is a trademark of International Business Machines
interactive applications concurrently! time- of PC AT hardware compatibility
Corporation. sharing the console display
• An IBM PC DOS "shell" on the AIX
2Trademark of AT&T Bell Laboratories. • Enhanced console support including Operating System allowing DOS command
extended ANSI 3.64 controls, color support, syntax and semantics to be used to invoke
3The UNIX component of AIX was developed by IBM and
INTERACTIVE Systems Corporation. The UNIX sound support, and mouse support AIX functions
component is based on INTERACTIVE's IN/ix, which is
based in turn on UNIX System V, as licensed by AT&T • An indexed data management access • IBM PC compatibility modes in the RT PC
Bell Laboratories. (lN/ix is a registered trademark of method that is integrated into the base BASIC and Pascal compilers, providing IBM
INTERACTIVE Systems Corporation.)
UNIX file system structure (this allows UNIX PC BASIC and Pascal-compatible functions

4
• IBM PC diskette access utilities and access • and many base operating system
methods. extensions: message services, shared
segment manager, etc.
One of our key technical decisions relative to
compatibility was to allow the PC AT The Result
coprocessor to execute PC programs We believe the design choices presented here
concurrently with ROMP programs, sharing and the specific designs highlighted in the
system resources such as main storage and following papers allow the IBM RT PC to
the system console. This unique capability is meet its original objectives. Further, these
provided by a combination of the coprocessor directions provide the architectural and design
hardware card and the VRM, which manages base for improvement with minimal disruption
the allocation and sharing of resources in as technology progresses.
such a way that the coprocessor's concurrent
execution is transparent to the operating
system and application programs. For
example, the VRM allocates the console
keyboard to either the coprocessor or the
ROMP and monitors keystrokes for a "hot
key" sequence signalling a need to switch to
the other processor. In a similar fashion,
other system resources are managed so that
the coprocessor applications seem to execute
in a virtual terminal just as the ROMP
applications do.

Application Development Facilities

For the initial release of the RT PC, we
placed a high priority on providing function to
facilitate application development. We
extended the already rich UNIX application
development support functions with:

• a host-compatible SQl data base manager

providing both an API and a full-screen
user interface,

• a FORTRAN compiler, BASIC compiler and

interpreter, and Pascal compiler (in addition
to the C compiler and assembler included in
the base operating system),

• a "net BIOS" set of facilities for access to

the IBM PC Network,

5
Hardware Description

P.O. Hester, J.T. Hollaway, and F.T. May

Introduction • The initial product offering should clearly The new IBM-designed ROMP 32-bit
demonstrate the long-range potential of the microprocessor and its corresponding
Design Philosophy design. Memory Management Unit (MMU) are
The IBM RT PC system hardware was packaged on a processor card which comes
designed with the following basic philosophy Hardware Summary with each model. There is also a separate 32-
in mind. The RT PC workstations have consoles that bit slot for an optional floating point
contain the electronics, storage devices and accelerator card. Two other dedicated slots
• A new family of workstation systems should power supply. They cable attach to the are provided for system memory cards.
be based on the most recent advances in display, keyboard and other optional devices
microcomputer technology. to meet the configuration requirements for the The unique ability to execute both IBM PC
customer's applications. The IBM RT PC is and IBM PC AT programs concurrently with
• An architecture should be established to available in two basic packages: the IBM native RT PC programs is provided by an
ensure: 6150 is a floor-standing unit and the IBM optional coprocessor card which plugs into
6151 is a desk-top console similar in size to one of the I/O slots. Other coprocessor
- The effective integration of a 32-bit the IBM PC AT. The 6150 Model 25 provides options provide for faster performance with
virtual memory microprocessor with the maximum extendability, but most options additional PC AT memory cards and a math
existing and new 8-bit and 16-bit I/O are available on all models. coprocessor chip.
adapters
The workstations have a wide range of The system memory is packaged on
- The effective addition of I/O devices and standard and optional hardware components. 1- and 2-megaoyte cards which piug into two
adapters as technology trends progress Data storage is provided on 5-1/4-inch hard dedicated memory slots and provide
disks and diskettes. A large system board is expansion of models up to 3 and 4
- The attachment of coprocessors for used to package the base electronics and megabytes. The hardware architecture allows
compatibility and performance card slots in each model. A number of cards for addressing up to 16 megabytes of real
enhancements and adapters have been designed specifically memory.
for the RT PC, and the I/O channel slots are
- The ability to incorporate user-installable designed so that many existing IBM PC and A wide variety of display subsystem options is
performance enhancements over the life PC AT cards can also be used. Operator available. In addition to existing IBM PC
of the product input can be made with a 101-key keyboard displays and adapters, three new offerings
and an optional two-button mouse or tablet are available with monochrome and color APA
• A strong relationship should be maintained pointing device. features. Also, computer-aided design
with the IBM Personal Computers. applications can be run using a serial link
In addition to the standard I/O channel slots adapter card attached to an IBM 5085
• The product should allow customer setup on the system board, there are unique slots Graphics Workstation in a host-based
and service. for each of the 32-bit system components. network.

6
Hardware Architecture 32-bit system Standard PC I/O
components ~ features
The RT PC system combines a 32-bit
microprocessor (ROMP) and Memory I System board

Management Unit (MMU) with a standard RS-232 ! I

0
ASYNC Serial*
16-bit I/O channel. The system is partitioned I
so that the 32-bit system components operate RS-232 :, Serial*
independently from the 16-bit I/O channel. ASYNC I
This approach provides both high- I Native I/O
performance, 32-bit processing and Keyboard ! KBD RTC/timer
Native serial ports Model 6150 only

I Native I/O
compatibility with standard 16-bit I/O I t--- Dedicated microprocessor for:
Speaker SPKR DMA
adapters. The RT PC hardware structure is I
~
Keyboard
shown in Figure 1. Mouse/tablet -. Mouse Interrupts Mouse
Tablet
IL ______ -, I/O bus DMA, interrupts
Floating
The RT PC utilizes the IBM-developed ROMP I Real time clock, timer
point
accelerator
, Floating point card:
microprocessor and corresponding MMU I 32081 FPA
packaged on a processor card which plugs I 200 KWIPS
into the system board. The ROMP implements Processor Processor card:
bus I 170 nsec cycle
a Reduced Instruction Set Computer (RISC) 32-bit
(32-bit) I 1.5 - 2 + MIPS
I
architecture with 118 instructions, 16 32-bit micro-
I
40-bit virtual address
processor 24-bit real address
general-purpose registers, and a full 32-bit I 32-bit 10CC interface
data flow for both addresses and data. Most I/O

register-to-register operations execute in one

~ 10CC '--- Channel t---
10CC:
Generates I/O bus

170-nanosecond cycle. Performance is r- Interface Control I - -

(IOCC)
Native I/O control
Address mapping logic
typically 1.5 to 2.1 MIPs, depending on the Memory I * I/O Channel:
Management I PC PC-AT
instruction mix. Unit I
I
l PC
Independent from memory bus
2M Bytes/sec to system memory
The MMU implements a "single level store" Processor I 4M Bytes/sec to channel memory

address translation architecture which

converts the 32-bit system address to a 40-bit Memory
card I
,
,
I
I AT*
* = Model 6150 only
PC AT coprocessor card:
PC-XT Performance w/system memory
(1 terabyte) virtual address for translation.
control ~

I
I AT
0.8X PC-AT Performance w/channel memory
Concurrent operation
Internal translation buffers within the MMU
Memory,
I I AT
Memory:
convert the 40-bit virtual address to a 24-bit , I/O 23.5M Bytes/sec BW
(16 megabyte) real address. Hardware is also
bus
(32-bit) I
Channel
(16-bit)
l AT
150/300 nsec RAM
IPL r---- , 256K technology
provided in the MMU to automatically reload ROM
I
I AT
SEC/OED ECC
Max. addressing 16MB
the translation buffers from main memory
page tables as required. The MMU also
I
I
I AT
contains the ECC logic for system memory, I
System ,
and some of the control logic for system memory 12MB ECC 11
I I
memory and the IPL and power-on self test I
ROM. 1MB ECC
f..-
2
,
I
Details of the ROMP microprocessor and
MMU architecture are described by Hester, et Figure 1 RT PC System Architecture

7
al.[1]. Chip implementation details are ROMP. Multiple floating point register sets as compatible as possible with the PC AT 1/0
described by Waldecker, et al.[2]. are provided for rapid context switching. channel. In addition, new features such as
Performance is approximately 200,000 burst and buffered DMA and shareable
Both the ROMP microprocessor and the Whetstone instructions per second. Various interrupts were added to improve the channel
MMU are custom designed VLSI components aspects of the FPA are covered by Smith [4]. performance and usability. The IBM 6151
using an IBM 2 micron NMOS process. Both provides one 8-bit PC slot and five 16-bit PC
components are packaged in a pin grid array Two dedicated slots are provided for system AT slots. The IBM 6150 provides two 8-bit PC
package on a 36-millimeter ceramic substrate. memory, which attaches to the processor slots and six 16-bit PC AT slots. Timing and
The ROMP contains approximately 45,000 card through the memory channel. The performance of the 1/0 channel are the same
devices on a 7.65 x 7.65 millimeter chip, with memory channel consists of an independent in all models. Phelps and Upton [6] discuss
the MMU containing approximately 62,000 40-bit data bus and 24-bit address bus. The various characteristics of the RT PC 1/0
devices on a 9.0 x 9.0 millimeter chip. data bus includes 32 bits of data and 8 bits of channel.
error correcting code (ECC). The RT PC ECC
In addition to the ROMP and MMU, the allows automatic detection and correction of In addition to the channel conversion
processor card (see Waldecker, et al. [3]) all single-bit system memory errors, and functions, the system board contains a
contains logic to adapt the 32-bit packet- detection of all double-bit errors. The 24-bit programmable translation control facility to
switching microprocessor channel to an address bus is capable of addressing up to support accesses from adapters on the 1/0
asynchronous 32-bit processor channel 16 megabytes of system memory. channel to system memory. A separate
connected to the optional floating point dedicated microprocessor is provided to
accelerator card and the system board 1/0 Standard 256K RAM technology is used on handle the keyboard, speaker, mouse, and
Channel Converter (IOCC). A dedicated the system memory cards, with a minimal tablet interface. The IBM 6150 also includes
memory channel is also generated from the amount of support logic. All memory timing, two built-in RS-232 serial ports with DMA
MMU for connection to the system memory control, and ECC functions are provided by capability for attaching terminals, printers, or
cards. Five IBM technology bipolar gate the processor card. System memory is two- other 1/0 devices.
arrays of approximately 300 gates each and way interleaved on each memory card, with
vendor TTL logic are used for interfacing to one bank containing only even addresses and The optional Intel 80286 based coprocessor
the processor channel and memory channel. the other bank containing only odd card plugs into an 1/0 channel slot and
addresses. This interleaving technique, provides compatibility with PC and PC AT
Clock generation for the microprocessor, combined with 150-nanosecond access time programs. In addition to the 80286 and
memory management unit, and system RAMs, provides a system memory bandwidth optional 80287 math coprocessor, this card
memory is provided on the processor card. of 23.5 megabytes per second (4 bytes every contains control logic that intercepts 80286
Independent clock generation is provided on 170 nanoseconds). Details of the memory accesses to selected 1/0 addresses. A
the system board for 1/0 channel timing. This cards are described by Rowland [5]. combination of this logic and system software
makes it possible for higher performance allows sharing of system 1/0 adapters such
processor cards and system memory cards to The system board contains all of the channel as displays, keyboards, and files. Alternately,
be supported as technology permits, without conversion functions to adapt the 32-bit system software can program this logic to
affecting 1/0 channel timing. ROMP Storage Channel (RSC) to a PC allow direct coprocessor access to private 1/0
AT-like 1/0 channel. 1/0 channel support adapters. Appropriate mapping is also
The optional Floating Point Accelerator (FPA) functions such as an interrupt controller, DMA provided by system software that allows PC
card attaches to the 32-bit processor channel controller, and real time clock and timer are applications written for the PC monochrome
and provides improved performance for also provided on the system board. Timings, or color adapter to run on an RT PC using a
floating point applications. This card utilizes a address assignments, interrupt assignments, native APA display. Operation of the
National Semiconductor NS32081 Floating DMA assignments, and related functions of coprocessor card is described by Irwin [7].
Point Unit and operates independently of the the RT PC 1/0 channel were designed to be

8
PC programs for the coprocessor can be The capacity of the files to make available in provided as the applications evolve. The
stored either in system memory or in the models also varied as the project RT PC can meet the needs of a wide variety
dedicated, I/O channel-attached memory. advanced. Files as small as 10 to 20 of users, so their display needs are expected
Coprocessor performance is typically that of a megabytes were seriously considered, but the to be diverse.
PC when executing programs in system final system design point required the larger
memory and about 80 percent that of a PC capacities of 40 and 70 megabytes. The The RT PC system provides for the
AT when using I/O channel-attached memory. combination of these larger files, and the attachment of existing adapters and displays
option to have a model with three files, of the IBM PC products. Specific IBM PC
I/O Devices substantially expanded the range of potential displays which have been tested for
The selection of I/O devices was made by applications that can be adapted to the announcement are the Monochrome Display
considering technology trends, the product. and the Enhanced Color Display with their
requirements of evolving applications, system respective adapters.
performance, and physical power and Another example of the flexibility of the
packaging constraints. The generic set of design approach to the file area is illustrated The new displays and adapters provide direct
devices required for electronic workstations is by the fact that the disks and diskettes are processor access to a 1024 x 512 bit map
well established in the industry. There are a attached by the use of the IBM PC AT Fixed- with a display viewing area of 720 x 512
number of vendors that specialize in each of Disk and Diskette Drive Adapter, an existing PELs. Hardware assist provides for text and
these devices and are very competitive in card in the IBM PC product family. graphics alignment to the PEL level. This
advancing the state of the art in their design point was determined to be a good
respective areas of the industry. The An external streaming tape drive and a trade-off between cost and total screen PELs
architecture of the RT PC system allowed the separate adapter card that attaches to the for both monochrome and color applications.
designers to select the preferred devices to RT PC I/O channel are available as an option.
meet the anticipated marketing opportunities The streaming tape unit provides a capacity A higher function monochrome display
as the project proceeded and the of 55 megabytes using a standard 1/4-inch subsystem provides a larger viewing area of
requirements changed. A few examples are tape cartridge. 1024 x 768 PELs and extensive hardware
outlined below. assist for high-speed vector-to-raster
Display Subsystems conversion from a vector list buffer. This
Hard File Subsystem The display subsystem is generally the most design point is also considered to be a good
The major decision in the selection of hard obvious I/O device to the users of electronic trade-off between cost and total screen PELs.
files was to use the 5-1/4-inch form factor. workstations. The characteristics of the
The size of the desk-top and floor-standing display are described by the parameters of A full 1024 x 1024 color display with existing
consoles is most directly affected by the size size, number of picture elements (PELs), PEL advanced computer-aided design, CAD,
of the files. The technology was moving density, monochrome and color, and applications is provided by the ability to use a
toward 5-1/4-inch files even though the 8-inch front-of-screen performance. Substantial cost serial link adapter card to attach the RT PC
files were still improving in capacity and cost. differences exist among these parameters. system to an IBM 5085 Graphics Workstation
The main reservation in the selection of these The applications selected by the users in a host-based network.
files was the average access time, which is in determine which of these parameters affect
the range of 40 milliseconds versus 25 to 30 their choice of display subsystem. Details of Mechanical And Electrical Packaging
milliseconds for 8-inch files. Transfer rates the various displays and adapters are Two different physical packages were
are the same, at 5 megabits per second. described by St. Clair [8]. selected for the RT PC system. The IBM 6151
System performance work was done to package is very similar to the IBM PC AT
understand and compensate for this The design decision was to offer a wide desk-top configuration. The IBM 6150 has a
difference. variety of display options and ensure that the floor-standing console to provide room and
architecture allowed for future options to be power for more adapter cards and files.

9
The key requirements for the packaging were providing a user interface with simple environment. The architecture was tested on
set in compliance with the basic design selection of desired tests and reporting test numerous occasions and allowed for needed
philosophy mentioned above. One was to results in a concise manner. These design changes that preceded the initial
provide for the use of existing IBM PC cards, characteristics were considered mandatory product announcement.
which established minimum physical for a machine with customer setup and
dimensions and power requirements. File service. The use of an open architecture similar to the
capacity requirements to support the earlier IBM PC products allows for extension
addressing capabilities of the processor Both the RT PC design and manufacturing by anyone who chooses to develop hardware
dictated the need to have models that can processes have resulted in the ability to attachments and applications that enhance
hold multiple files. A system board is used to produce a complex workstation in high the features of the base machines. This
mount connectors for the various cards that volumes. The component selection and approach continues to be successful in
make up the base models and to provide qualification process, failure analYSiS, and personal computer systems and should be
extra slots for options. run-in testing allowed supporting a 12-month successful in the more advanced workstation-
warranty. oriented systems.
Equally important were the requirements to
design the product for automated Conclusion Numerous enhancement possibilities are
manufacturing. This included limiting the The RT PC system was designed to bridge obvious to designers and users of this new
number of separate subassemblies, the gap between the personal computer class of advanced product. The architecture is
establishing a standard packaging form for products introduced during the past few years capable of supporting increased memory
each of the subassemblies delivered to the and emerging advanced 32-bit workstations capacity, higher capacity files, higher
manufacturing line, minimal use of internal with extensive virtual memory management performance displays, other local area
cables for interconnections, and selection of facilities. These workstations will become the networks, higher speed host attachments,
one standard card size for all cards. Details basis of computing systems that have and other coprocessors. Enhancements
of the manufacturing process are described extensive storage, display and should follow as time and new technologies
by Bartlett, et al.[9]. communications requirements to satisfy new allow interested companies in the computer
applications as they evolve. Specifically, the industry to respond to the business
Quality And Reliability RT PC: opportunities.
Many design and manufacturing decisions
during RT PC development were made to • Introduces an IBM-developed, high- Some enhancements may be limited by the
ensure a high quality and reliable product. performance, 32-bit RISC architecture with 110 devices, or by the 110 channel
These included design for automation virtual memory. characteristics. Others may be limited by
concepts in the original design, development computational speeds in the main processor,
of an automated manufacturing process, • Combines the new 32-bit features with a the IBM PC AT coprocessor, or the floating
component selection process, analysis of standard PC 110 channel. point accelerator. Performance requirements
early life failures, and automated error logging of new applications will reveal these
during system run-in testing. • Provides an optional PC coprocessor for constraints. Potential solutions to many
compatibility with existing PC application anticipated future requirements have already
A diagnostic program based on an expert programs. been defined by the development team.
system (see Burns and Williams [10]) is
provided to aid the customer in diagnosing The development cycle for the product was It is hoped that the decisions made during the
system problems. This program tests all executed during a period of continual change RT PC system development process will
RT PC system board functions and all 110 in technologies and design specifications, so survive the test of time, that the technologies
adapter functions. Major considerations in the an architecture was defined to provide provided by the product will satisfy the needs
development of the diagnostic program were consistency of design decisions in this of developers, and that the applications built

10
on the product will meet the needs of users
ranging from technical professionals to office
workers.

References
1. P.O. Hester, Richard O. Simpson, Albert Chang, "The
RT PC ROMP and Memory Management Unit
Architecture," IBM RT Personal Computer Technology,
p.48.
2. D.E. Waldecker, C.G. Wright, M.S. Schmookler, T.G.
Whiteside, R.D. Groves, C.P. Freeman, A. Torres,
"ROMP/MMU Implementation," IBM RT Personal
Computer Technology, p. 57.
3. D.E. Waldecker, K.G. Wilcox, J.R. Barr, W.T. Glover,
C.G. Wright, H. Hoffman, "Processor Card," IBM RT
Personal Computer Technology, p. 12.
4. Scott M. Smith, "Floating Point Accelerator," IBM RT
Personal Computer Technology, p. 21.
5. Ronald E. Rowland, "System Memory Cards," IBM RT
Personal Computer Technology, p. 18.
6. Sheldon L. Phelps and John D. Upton, "System
Board and 1/0 Channel For The IBM RT PC System,"
IBM RT Personal Computer Technology, p. 26.
7. John W. Irwin, "Use Of a Coprocessor For Emulating
The PC AT," IBM RT Personal Computer Technology,
p.137.
8. Joe C. St. Clair, "IBM RT PC Displays and Adapters,"
IBM RT Personal Computer Technology, p. 31.
9. Charles W. Bartlett, A.V. Burghart, George M. Yanker,
"Manufacturing Innovations to Increase Quality and
Reduce Cost," IBM RT Personal Computer
Technology, p. 40.
10. Nancy A. Burns, C. Edward Williams, "Use Of
Artificial Intelligence To Diagnose Hardware," IBM RT
Personal Computer Technology, p. 35.

11
Processor Card

D.E. Waldecker, K.G. Wilcox, J.R. Barr, W.T. Glover, C.G. Wright, H. Hoffman

Introduction Support
Clock processor
The processor card provides the central interface
Clocks ~ generator ~Clocks
processing and memory management
functions of an IBM RT PC system. It
interfaces with memory cards [1] and I/O -"-

hardware on the RT PC system boards [2] in

a manner which readily supports future
MMU
enhancements of memory cards or the ROMP Memory data bus
r--+ processor
storage
processor card itself. The card contains the r---
controller
ROM P processor and M M U memory
n
management chips [3] plus support functions t Address bus
including ROM and internal clock generation. e
I/O
channel L-.. Memory Data
u Reference/
Card Functional Overview convertor controller
change
P Address
A functional diagram for the processor card is t array
given in Figure 1. Logic on the card adapts r
the ROMP and MMU interfaces for other e
q
Diagnostic indicators
I
system components and develops a special u
test interface [3] that supports hardware and e ~ ROM r---.
Processor Memory
softvvare debug vv'ithout reiiiova: of the RO~Y1P ICard I address Memory I
processor chip or any perturbation of the IChannel I bus data
bus
physical card components.
Memory interface

The MMU connects to ROM and a Reference-

and-Change Array on the processor card as Figure 1 Processor Card Functional Diagram
well as with the interleaved memory cards.
The ROM contains programs to perform selecting dynamic RAM and ROM modules for and to enhance performance. This approach
power-on diagnostics and IPL functions for optimum cost/performance characteristics in also restricts the high frequency, repetitive
the system. The diagnostic display indicators the system. The Reference-and-Change Array clocks to the card and minimizes
are also driven by logic on the card. Failure is external to the MMU due to space electromagnetic interference exposures for
isolation is improved by packaging the limitations on the chip. (The function of the the system.
diagnostic ROM and the display drivers with Reference and Change Array is explained
the processor components. later.) The clock generator logic is driven by a
23.5294 MHz oscillator to provide clocks for a
The memory-specific controls were placed I/O interface adapter logic was included on 170-nanosecond processor cycle time. The
external to the MMU to improve flexibility in the processor card to improve fault isolation

12
timing relationship between clocks on the from 512K bytes to 8M bytes can be Enable signals are provided to control read/
card is tightly controlled by synchronizing the supported by decoding four control lines (two write of the memory as well as the direction
clocks in FAST TTL modules. from each memory card slot in use). During a of the data bus.
memory access, the memory card capacity
Processor Card Interfaces indicators and several bits of the storage The MMU chip makes use of an external
Two independent system interfaces, the address bus are used to verify that the array consisting of one"Reference" bit and
processor channel and the memory channel, access is to a valid memory address. one "Change" bit for each page of real
connect the processor card to the rest of an Although the processor card accepts a one or storage in the system. The Reference bit
RT PC system. A test interface is also two memory card configuration, "slot-O" must indicates if the corresponding page has been
available for special hardware and software be used first. Also, the memory capacity of accessed, and the Change bit indicates if the
debug functions. the card in slot-O must be greater than or page has been altered. This information is
equal to the memory capacity of the card in used by system software for page
The memory channel can connect to one or slot-1. replacement decisions. The Reference-and-
two memory cards containing a maximum of Change Array is implemented with a 16K by 1
16 megabytes of memory. The memory cards The RAM on each memory card is divided static RAM. The storage address bits and the
are described in the article by Rowland [1]. into two independent banks (an even bank storage interface control signals from the
and an odd bank) for interleaving purposes. M M U are used to determine if a RAM access
The processor channel is an asynchronous, The even bank operates on requests with an has taken place and, if so, to set the
32-bit, bidirectional channel which connects to even fullword storage address from the MMU appropriate bits in the array. The Reference-
the I/O Channel Controller (IOCC) on the and the odd bank operates on the odd and-Change Array is also accessible to
RT PC system board [2] and to the Floating address requests. All accesses to storage are system programmers via the Programmed
Point Accelerator Card [4]. done using fullword data transfers. Input/Output (PIO) commands to the MMU.
!nterleaved memory improves system
Memory Interface performance by allowing two memory Eight bits of data (comprising two decimal
The memory interface logic manages an accesses to be in progress at the same time. digits) for the Diagnostic Display LED
address bus, a data bus, and control signals (A timing diagram which shows interleaved indicators are driven by the memory interface
permitting two memory accesses to be in memory operation is included in the paper on logic. During IPL the LED indicators are used
progress simultaneously. The interface ROMP/MMU Implementation [3].) A separate by software to show the hardware diagnostic
connects to both ROM and RAM and is 10-bit RAS/CAS address bus is provided for program that is either currently executing or
flexible regarding the amount of each which each bank of storage. The memory card which has failed. In addition, the memory
may be present in a system. Memory refresh interface consists of the two 10-bit address interface logic automatically sets the LED
is managed and directed to an idle memory buses, a 40-bit bidirectional data bus indicators to "88" if the ROMP processor
bank when possible, thus reducing refresh (including 8 bits ECC), and 21 control lines. stops due to a severe error or due to a halt
interference. command during debug.
The processor card memory interface
The memory interface logic contains two IBM generates all clocks and controls needed to Interface to the System Board
bipolar gate arrays, TTL logic for memory operate the memory modules on the memory The design objectives of the processor card's
card interface buffering, four ROM modules, cards. Four separate row address strobe interface to the system board (the "processor
and a 16K by 1 static RAM which is the clocks are created to support the maximum channel") were high performance, non-critical
Reference-and-Change Array. memory card configuration (Le., even bank/ timings, simple system board attachment
slot-O, odd bank/slot-O, even bank/slot-1, and logic, and isolation of the processor card from
Two memory card slots on the system board odd bank/slot-1). Two column address strobe the system board. The desirability of high
and a range of memory card configurations clocks are provided: one for the two even performance, relaxed timing, and simple
are supported. Memory cards ranging in size banks, and one for the two odd banks. attachment is obvious. Isolation is

13
advantageous because it limits the most time- 170 ns
critical signals and clocks to the processor
card, allowing better performance. It also RSC cycles
allows future improvement of processor cycle
time without impact on system design. Finally, RSC
GXD 0
restricting the high-speed signals to the
processor card reduces the potential for -I/O cycle
\~------------------~I From Proc. Cd.

electromagnetic radiation problems.

-Data STB From Proc. Cd.

The interface between the processor card and

the system board is 32-bits wide, multiplexed,
Data bus
GXD ( R
>
and asynchronous. The address and data
transferred over the processor channel are in
-Busy
\ ......._ - - - _....../ From system

the same format as when transferred over the

RSC. The processor channel has some
-RDY
"---I From system

attributes of a general-purpose bus, but the

processor card is the sole bus master, and all
-Data gate \ / From Proc. Cd.

bus timing is under its control. Figure 2 Programmed I/O Cycle

On the system board interface, there are two positive and negative transitions of DATA In the RT PC system, the 10CC always
slaves, the I/O Channel Controller (IOCC), STROBE, respectively. If the slave requires a causes a single envelope cycle. Accesses to
which develops the I/O channel, and an "single envelope" cycle, it may lock the the floating point card, however, may overlap
optional floating point card. The processor channel by activating the BUSY line. each other or 10CC cycles.
may access the 10CC or floating point card Otherwise, new requests may appear on the
using Load or Store instructions (memory- interface. A reply to a request may occur For processor-originated I/O cycles, the
mapped I/O) to segment 15 of the virtual or either within a single envelope cycle or at maximum transfer rate is approximately 7.8
real memory space. In addition. the 10CC may some later time. When a reply !s availab!e, the megabytes per second. Transfers to the
access ~)'~tem storage through DMA. READY line is asserted. The processor card system iiG channei are paced by the speed
responds with a gating signal which is used of the I/O channel. Transfers to the floating
The basic memory-mapped I/O operation to enable the slave's drivers onto the point card could approach the theoretical
involves two types of transfer: request and interface. The basic PIO cycle is shown in maximum, limited primarily by the program
reply. All operations begin with a request, and Figure 2. doing the transfer. For DMA transfers, the
replies occur if the operation is a read or a interface supports a transfer rate of about 4
translated write. The requests and replies The DMA cycle is managed by the processor megabytes per second.
may be uncoupled from each other, or they card. The system board makes a request, and
may be attached. This is controlled by the when able, the processor responds with The I/O interface is implemented primarily
slave using handshaking signals. A request gating signals used by the system board to with three bipolar IBM gate arrays, with a
consists of address and data. In response to gate out the address and data for the total of about 1000 gates.
a request from the system processor, the transaction. The I/O interface logic generates
processor channel interface logic outputs a request on the internal storage channel and Test Support
address, then asserts DATA STROBE, sends a reply (if required) to the system The processor card provides many functions
changes the address to data, removes DATA board. Overlapping DMA requests are not which aid in the testing of both hardware and
STROBE, and finally disables its data bus performed. The basic DMA cycle is shown in software in the RT PC system. These
drivers. Address and data are latched on the Figure 3. functions are built into the ROMP chip set,

14
 The second set of functions provides control
RSC cycles
of the system; stopping, starting, setting
RSC C£I:E) CD breakpoints, and other functions. Stopping
and starting the processor card is done by

FI
Data bus D ) ( D ) causing the clock chip to stop or start the
ROMP clocks. Breakpoints, which can be
-DMA Req. \ I r From system specified as either instruction or microcode

-DMA cycle
i\ !
Ir-
I
From Proc. Cd.
addresses, are set up by scanning
information into the ROMP which causes it to
signal via a sync output just prior to executing

~I I the instruction or microcode at the indicated

-ADDR gate From Proc. Cd.

address. The clock chip can then stop

'\ /
~
-Data gate From Proc. Cd. execution by turning off the ROMP's clocks if
a stop on compare has been selected. The
-Data strobe From Proc. Cd.
sync signal is also available as an output
from the ROMP, and is very useful as a
Figure 3 DMA Cycle trigger event for a logic analyzer. Microcode
cycle or instruction stepping is performed by
and are accessed by simply connecting • register display and alter clocking the ROMP for a single machine cycle
another computer (currently an IBM PC with • clock control for breakpoints, etc. (for microcode stepping) or until its instruction
special interface card) to the processor card. • memory display and alter. complete line goes active (for instruction
stepping). This provides very accurate
The ROMP, MMU, and clock chips were The first set of functions gives display and visibility into the execution sequence down to
designed to provide easy testability with alter capability for the internal registers and the microcode level, if desired.
minimal external hardware. This means that control state of the ROMP. The ROMP
unlike many development systems, no special provides access to its internal state through The third set of functions provides the ability
emulator circuit is required and the phYSical its Level-Sensitive Scan Design (LSSD) scan to display and alter memory and internal
hardware configuration is not altered for test. strings (Le., all registers and latches are MMU registers. The MMU provides a serial
This is an especially important advantage for connected as shift registers for test port to allow memory or register reads and
card-level test, as the ROMP processor is purposes). By scanning data into or out of writes to be performed. The serial port is
soldered on the card and removal is time these registers, all of the ROMP's registers completely separate from the memory
consuming and inconsistent with high-volume may be examined or altered. By scanning interface, and therefore can be used whether
manufacturing. certain data into the shift registers and or not the ROMP is functional. This provides
clocking the ROMP, the general-purpose a good starting point for system debug, since
The support computer, called the ROMP registers may be accessed. Examining the a substantial part of the processor card logic
Support Processor, processes commands contents of the ROMP's registers does not (MMU, ROM, and memory interface) can be
typed in by the user, sends required signals interfere with what would be the normal checked without the services of the ROMP.
to the processor card, and displays the processor execution if the Support Processor Accesses to memory through the serial port
internal state of the ROMP and MMU, as well were not attached (other than requiring the do not affect any outstanding memory
as ROM or RAM memory. processor to be halted and then restarted), requests which the MMU may have previously
and in fact provides excellent control and buffered; therefore the system may be
The test features can be divided into three visibility into the workings of the processor stopped, memory displayed, and the system
categories based on function provided: card and internal chip logic. restarted with no effect on normal execution.

15
The serial port is also used to upload or Physical Configuration processor card layout. The physical card
download programs between memory and PC In addition to the ROMP and MMU modules, contains four signal planes plus one ground
disk/diskette. the 4.5" X 13" card contains six bipolar IBM and one voltage plane.
gate arrays, TTL components (including
Test features providing stopping plus register ROM), and various passive components such Conclusion
and memory display/alter capability are built as resistors and decoupling capacitors. There The RT PC packaging and processor card
into the RT PC processor card and are are two 100-pin connectors-one for the design approach are well suited to
extremely useful for both hardware and system board and the floating point responding to future technology
software debug. The hardware debug aids accelerator card, and a second which developments. The memory cards connect
are helpful in debugging many software connects to the memory cards. The special only to the processor card memory interface,
problems which are time critical, branch off to test interface is via a 60-pad arrangement on permitting the relative timing between the
an unknown point, or result in a processor the top of the card, which is gripped by a memory and processor to be easily changed
stopped condition (e.g., closely-spaced, special connector on the ROMP Support as technology improves.
multiple program checks). Processor cable. Figure 4 shows the

r-- - - - ---- --- - --- ,---- -- ----- - - --- - - ----- - -- - -- - - - - - ---------,

I

U1 q
r2I
1 U2

q@) I
q g ~
r-I- u - 3 -"""'l1

g:
I

I @I]
q~~---------' [§]
II> a:
G
~
EEftill
.....
1 U4
==~I~I
'rcrJ-"""'RP;::1
q
,.....----:::::1
1 U5
I
11@ill~I;::::=::;RP8;:::::::;;-;~[]!:O
Support i SO

U53
; Connector
1
.
I
9
0

m1[J@][Ji@i)
r-I-U-6-ct"""@J 1 U7 U8 @ill MMU U ROMP I RP7 C1r-6_ _ _-,

I U1~g ~ lnaon~I'~ .1J, ~:,~ II~ U11~ 0

r-1-U1-6-g-'
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25MM
M4
lru 25MM
M5, @[) """
M1

:r-I"'::;:;;:::;'~...!ilnl---:[§[]=--§]=C33::-'
~ ,,_
(§E] [§[] [ED C37
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C38 C39 r.-------~-

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__[@__2~~ __________ -I
::.

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:::! q 9 q 53 I 9 53 ~
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@TI I: -, :1 U17 1 U18 1 U19 1 U2C U21 1 U22
! 1)25 q I DI. 1 I! U26 g! C! d
U27 U23 .J I U24 RPI5. r"'I . - . ';" . rI r;" .-,

~ @ill ~-C48-@m :IRo;,.. I I ROM U28 =;IRP1~29 ~@!llJq~JlL:JI~L:JII~ I~':QI

, U3C ql r--U-31-g-' P"I-U-3-2-q""" ,-,-U-33-C1....,: ....S-1~---~-C50---' S 2 / @ [ ] RP17 M6 f3 M7 Ii1 M8 J;;;l..J
RP18 I 1 U36 q EJ EJ IQI
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,.....----,
rnD
U38 q I
@[]
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q
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~ III. RP20 rem I
@!!]L_S!~ ___ @D ~S4:-jlT---@[);:;;C7~O~r-I.::;R~:;;:::::;I;;I;;(ffiJ:;::::71 1 U42
9 J
=:t
9
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25 MM ~ ,,:~ MM
.....
I U43 53
25 MM
r-I- - - - - : I
"""-U4-5-q""" 1 U46 q 1 U47 q 1 U48 q 1 U49 q 1 U5C q I U51 qd I
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CI C74 C75
~~R~~~~~~~~~~~riT~~~
RP23
o I @ID--r:fE) o
nnr'nnlnnl~n~lnnlnnrlnnnnrlnnnnr'nnnnl'nnlnnlnnrlnnlnnrlnnnnrlQnn ""r'nnnnr'nnnnr'n",nnl~n~lnnlnnrlnnnnl'nnlnnr'nnlnnlnnrlnnlnnrlnnn

I
I
I
Memory interface I I/O interface
____________________________________ L _________________________________ --1

Figure 4 Processor Card Layout

16
The interface to the system board effectively
decouples the processor card from the
remainder of the system timing. Thus the
processor card performance can be improved
without impacting the system design.

References
1. Ronald E. Rowland "System Memory Cards," IBM RT
Personal Computer Technology, p. 18.
2. Sheldon L. Phelps and John D. Upton, "System
Board and 1/0 Channel for the IBM RT PC System,"
IBM RT Personal Computer Technology, p. 26.
3. D.E. Waldecker, C.G. Wright, M.S. Schmookler, T.G.
Whiteside, R.D. Groves, C.P. Freeman, A. Torres,
"ROMP/MMU Implementation," IBM RT Personal
Computer Technology, p. 57.
4. Scott M. Smith, "Floating Point Accelerator," IBM RT
Personal Computer Technology, p. 21.

17
System Memory Cards

Ronald E. Rowland

Introduction correcting all single-bit errors, detecting all processor card can operate them one
Each IBM RT PC system memory card double-bit errors and detecting the majority of machine cycle out of phase with each other in
contains two independent memory arrays and multiple-bit package errors. The architecture an interleaved fashion. The two-way
associated support circuitry. The architecture also provides a means of automatically interleaving allows for a memory reference to
of these cards provides for full two-way identifying the characteristics of the system occur every machine cycle. The 4-byte data
interleaving between the two arrays, with one memory configuration to the remainder of the access in combination with the two-way
array containing only even-addressed words system. interleaving results in a system memory
and the other containing only odd-addressed channel throughput rate of four bytes every
words. This on-card interleaving scheme Memory Card Architecture 170 nanoseconds (or a 23.5 megabytes per
allows for a data word access every second bandwidth). This memory interface
170-nanosecond machine cycle while using The RT PC system memory card architecture performance is approximately quadrupled
industry-standard 150-nanosecond dynamic is shown in Figure 1. The card is divided into over a conventional 16-bit microprocessor
random access memories (DRAMs). Each two independent arrays with each array system operating at 12 MHz.
data word access consists of 32 data bits and having its own support circuitry to allow for
eight error correction code (ECC) bits. The full two-way interleaving between the arrays. The figure shows that the input signals
availability of four data bytes every 170 The interleaving between the arrays is required to control these cards are very
nanoseconds results in a memory interface performed on a word (32 data bit) boundary. similar to a standard DRAM component. The
bandwidth of 23.5 megabytes per second. One array is used only for even-addressed card interface consists of 10 multiplexed
word references and the other is used only address lines (ADDR 0- 9), a Row Address
The RT PC contains two dedicated slots for for odd-addressed word references. The Strobe (RAS), a Column Address Strobe
the system memory cards. The memory chips interleaving function is provided on a single (CAS), a Write Enable (WE), and a Bus Enable
are packaged on 1-megabyte and 2-megabyte memory card, allowing for a system memory (BEN) for each array on the card. The 40 data
memory cards which provide for system configuration utilizing only one memory card lines (DATA 00-39) are shared by the two
memory configurations of 1M bytes, 2M and leaving room for memory expansion in arrays. Since the cards were a;ochitected to
bytes, 3M bytes, and 4M bytes. The 1M-byte the other dedicated memory slot. accept various DRAM technologies, two
interleaved ECC memory card design is additional Bank Address Bit (BAB) lines and a
based upon 64Kx4 DRAM technology while The processor card operates on a basic Refresh (REF) line were added. These
the 2M-byte card uses 256Kx1 DRAM machine cycle of 170 nanoseconds and the additional lines are shared between the two
technology. processor can cycle each of the memory arrays on the card and are only valid when
arrays in two machine cycles. This translates the RAS line for a given array is activated.
The hardware architecture allows for cards to a memory array cycle time of 340 The BAB lines contain the same information
containing up to 8M bytes of memory per nanoseconds with one memory reference that the high order address lines contain
card and for a total system memory performed every array cycle. Each memory during the column address phase of the
addressing capability of 16M bytes. The use reference gains access to 32 bits (four bytes) memory cycle. This information is required at
of eight ECC bits per data word supports the of usable data. Since the two memory arrays the beginning of the cycle (during the row
use of an error correction scheme capable of on the memory card are independent, the address phase) for cards with multiple banks

18
 r--- - - - - - - - - - - ---------, The RT PC system memory cards are piggy-back modules. Any of these 64K DRAM
I
I ...
- ... attached to the system processor card via the solutions to the problem would require a total
AD DR (0-9) EVEN ) C
0 v
) memory channel. All controls for proper of 160 DRAM chips and the use of a non-
RAS EVEN:
" n EVEN operation of memory read, write, and refresh standard packaging technique to achieve the
t memory
CAS EVEN
r array cycles are provided by the processor card. desired 1M byte capacity. The added cost
WE EVEN Since the memory arrays share a common and power requirements of these approaches
0
--'"
REF I
BAB (0-1) data bus (on the memory interface), the made them unattractive for production.
I "----
processor card also has the responsibility to
I /\..
I - ensure that there are no data bus usage The granularity question of how to combine
I X
c
conflicts between the two arrays. 1M byte of memory, a 32-bit data access, and
BEN EVEN I
I e two-way interleaving on a card with 60 square
I i
v
DRAM Technology inches of surface space was resolved by
I

A
I
I
I ~"
.... e
r < A

Data (00-39)
....
Due to the interleaved nature of the card,
each card must be able to supply the system
using a new version of the 256K DRAM chip.
The answer came in the form of the 64Kx4
'---
Data (00-39) with a minimum of 80 bits (32 data bits and 8 DRAM. The 64Kx4 DRAM is a 256K DRAM
r--
.....
I ECC bits from each array). When using teChnology, but it is four bits wide instead of
)
A
I
I
X
c
K... Data (00-39) standard 256Kx1 DRAMs in 16-pin dual inline the usual one bit wide arrangement. With the
I " e packages (DIPs) to achieve this minimum, the 64Kx4 DRAM the minimum requirement of 80
I i
result is 80 DRAM modules per card. Since bits per card could now be accomplished with
I v
BEN ODD e the physical card size is approximately 60 only 20 DIPs and the 1MB card could be
I r
square inches (one side), the minimum of 80 implemented with 40 modules (instead of the
I -
I 'J 256Kx1 DRAM DIPs is also the maximum 160 required when using a 64K DRAM
BAB (0-1) I
I - quantity that can be packaged on one card. technology). The 64Kx4 DRAM also provided
C
REF
0
Use of this standard packaging technique for a card design with varying capacities. The
WE ODD I
n ODD dictates a memory card capacity of two quantity of DRAM components could now be
CAS ODD t
RAS ODD I r
memory megabytes (2MB) with 256Kx1 DRAM DIPs. If increased in increments of 20, yielding card
I .... array
.... 0 such a card were to be implemented using capacities of 512K bytes, 1M bytes, 1.5M
AD DR (0-9) ODD
"
/ I .../ " standard 64Kx1 DIPs, the resulting card bytes and 2M bytes. With the merchant
I " '----
capacity would be 512 kilobytes. DRAM marketplace commanding a price
premium for the 64Kx4 over the 256Kx1
c Technical and marketing considerations DRAMs, it was decided to keep the 2M byte
o deemed that a 1M-byte memory card would card deSign based on the 256Kx1 DRAM
n
Size, ECC, fast refresh be necessary for the RT PC system. Since modules rather than deSigning it to be an
f
I using 256Kx1 DRAM DIPs resulted in a card expanded version of the 1M byte card.
I 9
I with a minimum of 2M bytes and using 64Kx1
I
I _____________________ _
L DRAM DIPs resulted in a card with a Automatic Memory Identification
maximum of 512K bytes, a new approach The RT PC system memory cards provide
was needed. Various packaging methods information to the processor card and to the
Figure 1 System Memory Card Logical Dataflow
which would allow doubling the quantity of system board identifying the system memory
64K memory chips on the cards were configuration. This identification indicates the
per array so that the appropriate bank of the
explored. These alternative techniques capacity and functional requirements of the
array can be activated. The Refresh line is
included the use of surface-mounted installed memory cards. The information is
required on these types of cards in order for
components (SMCs), single in-line packages provided on five static output lines, with three
the on-card logic to refresh the entire array
(SIPs), zigzag in-line packages (ZIPs), and of the five lines identifying a card capacity of
(and not just one of the banks).

19
512K bytes, 1M bytes, 2M bytes, 4M bytes, or Summary
8M bytes of memory. Another identification The RT PC system memory cards achieve a
line indicates that the card has an increased bandwidth roughly quadruple that of a PC AT.
refresh requirement allowing the processor This improvement is the result of employing a
card to automatically double the refresh rate. full 32-bit data interface and utilizing two-way
This line was added due to the uncertainty of interleaving. In addition to the 32 data bits,
the refresh requirements for future 1M-bit eight ECC bits are provided for correction of
DRAM technologies. all single-bit errors and detection of most
multiple-bit errors by the system MMU. The
These identification lines are basically architecture allows for use of any of the
"hardwired" on each memory card and common DRAM technologies now in
provide the RT PC system with all the production or envisioned over the next
information required for proper operation of several years. The automatic card-
the installed system memory. This automatic identification features provide the system with
identification mechanism relieves the the capability of determining the system
customer of having to adjust any switch memory configuration and relieve the
settings whenever the system memory customer of switch setting whenever the
configuration has changed. configuration is altered.

These lines are routed to the Memory The cards are somewhat restrictive when
Configuration Register (MCR) on the system trying to maximize their memory capacity
board and to the Memory Management Unit using standard DIP type components, due to
(MMU) on the processor card. The MCR is the physical size of the cards. This limitation
read by the system software to determine the can be overcome, however, by using other
memory configuration and the MMU uses this packaging techniques (SMC, SIP, ZIP, etc.)
information for proper control of the memory. with 256K DRAMs or with the availability of
The information and functions provided by 1M-bit DRAM technologies. The performance
this mechanism include determining: of the system memory interface could be
extended beyond the current 23.5 megabytes
a. the amount of physical memory installed per second limit by utilizing faster DRAMS in
(on a per card basis), conjunction with a decreased basic machine
cycle time. Other alternatives to extending the
b. the physical address range of each card, memory interface performance include using
a different interleaving scheme, the addition
c. whether or not the current memory of a cache, or a combination of the above
configuration is a valid one, approaches.

d. whether or not the current memory

reference is to a valid physical location,

e. and if the memory requires a normal or a

doubled refresh rate.

20
Floating Point Accelerator

Scott M. Smith

Introduction Overlapped Processing between ROMP and

ROMP
The IBM RT PC Floating Point Accelerator FPA Storage Channel
(FPA) is an optional feature which provides ROMP MMU
Before we begin the discussion which is the
significantly enhanced performance for subject of this section, some background
floating point, math-intensive applications. It material on the ROMP's use in a floating
consists of one 4.5" x 13" circuit board which point environment is needed. Processor
Card
plugs into a special slot in the RT PC system Interface
board. The FPA is based upon the 10 MHz The ROMP itself has no explicit floating point
National Semiconductor NS32081 Floating commands. In the base RT PC system, a

&'
Point Unit (FPU). software floating point emulator provides the Processor
Card
floating point arithmetic capabilities. If the Channel
Since the NS32081 's hardware interface is customer requires improved floating pOint
considerably different than the RT PC internal performance, the optional FPA may be added
bus, logic is added to adapt the part to the to his system. There is a compiler option
10CC
RT PC. In any such non-native adapter design called "compatible mode" which allows the
there is a risk of decreasing performance. resulting object code to run on either the
Several features are included in the design to emulator or the FPA. The other option, called
minimize and compensate for the potential "direct mode," produces code which will run ~

performance loss. The most significant of only with the FPA installed.
~
these are discussed in this paper. They are: I/O devices
overlapped processing between the system The FPA is attached as a memory-mapped I/O ~
channel
32-bit microprocessor (ROMP) [1] and the I/O device and its commands are encoded in •
FPA, use of an external register file, and the address. Specifically, the address is •
program synchronous exception handling. x'FFxxxxxx' where 'FF' is the FPA's channel
•
~

address and 'xxxxxx' is the FPA command.

Note that while the topic of discussion here is Figure 1 shows a block diagram of the RT PC
design features which improve floating pOint system and how the FPA is attached to it.
Figure 1 Attachment of Floating Point Accelerator
accelerator performance, it is difficult to
assess the contribution of each feature to In order to execute an FPA command, the
overall system performance. That level of ROMP loads the command (x'FFxxxxxx') into of 170 nanoseconds each to execute and the
analysis is beyond the scope of this paper. one of its registers. If data is to be sent as memory accesses that they initiate take a
minimum of 850 nanoseconds. The command
part of the command, it is also loaded into a
ROMP register. Several ROMP instructions is then sent to the FPA using a ROMP Load
are required to accomplish loading of these or Store command. When the address and
registers. The instructions require a minimum (optional) data appear on the ROMP Storage
Channel, the Processor Card Interface

21
recognizes the FPA's address and accepts ROMP Activity FPA Activity Comments
the command. The command is then sent to (FPA initial conditions - IDLE and No Exception on previous command)
the FPA over the Processor Card Channel. FPA command 1 •
Depending upon logic delays, 115 to 188 ~Reply 1 wlo exception Command 1 received
nanoseconds elapse between the address/ and execution begun

I
command first appearing on the bus and its
being strobed to the FPA. The data (if any)
will be strobed 242 to 315 nanoseconds from
T
Non-FPA
commands
the first appearance of the address. Because
the FPU clock is 10 MHz and the ROMP
clock is asynchronous, an additional 0 to 100
1
FPA command 2 ----1.~
Command 1
execution
Command 2 queued
nanoseconds delay is incurred due to
synchronization. T
No ROMP execution

Once the command is received, a reply is

excerst Fetch
returned to the ROMP indicating successful
receipt of the command. In the case of - Re~y 2 IexceP,on Start execution of command 2

commands issued using ROMP Loads, the

requested data is also returned in the reply. T
Non-FPA

If the ROMP were used to drive the

NS32081 's protocol directly, several such
command/reply sequences would be required
to execute an FPA command, e.g., Floating
Add, Subtract. The ROMP cannot execute the
Figure 2 Overlapped Processing Between the ROMP and the FPA
protocol fast enough to avoid significantly
degrading the NS32081 's performance. Logic
is therefore provided on the FPA to execute Figuie 2 illustiates how the ovei:apped immediate:y, allowing the ROMP to pioceed
the NS32081 's protocol while receiving only processing between the ROMP and the FPA as before. If the command was issued using
complete floating point commands such as actually works. FPA command 1 is issued by a ROMP Load command, the FPA must wait
Fadd, Fsub, and Fmul from the ROMP. This the ROMP (Store assumed). The FPA for execution to complete in order to obtain
logic provides the base mechanism for receives the command, returns the reply, and the data to be returned to the ROMP in the
overlapping ROMP and FPA operation. begins executing the command. In the reply.
meantime, the ROMP upon receipt of the
If the reply is sent back to the ROMP early on reply proceeds to execute other code, in this
FPA commands issued by ROMP Stores, the case preparing and issuing the next FPA
ROMP can continue to do other work such as command. The FPA, still executing command
setting up the next FPA command while the 1, queues command 2. At this point the
FPA executes the current command. In fact ROMP can only issue instruction fetches to fill
this concept is extended in the FPA to allow it its internal buffer. Once the FPA finishes
to actually receive the next command from command 1, it immediately begins executing
the ROMP while executing the current command 2. If command 2 was issued using
command. a ROMP Store, the reply can be returned

22
The External Register File o 31

The following table shows several key FPR 0 Register

instruction execution times for the NS32081 set 0
FPR 1
running with National Semiconductor's 10
MHz NS32032 microprocessor [2]. ·
·
SINGLE DOUBLE ·
FPR 14 - status
INSTRUCTION CASE PRECISION PRECISION
FPR 15 - system
ADD MEM-MEM 7.8 IlS 8.4 IlS
REG-REG 7.4 IlS 7.4 IlS Register
set 1
MULTIPLY MEM-MEM 5.2 IlS 7.2 IlS
REG-REG 4.8 IlS 6.2 IlS
MOVE (NO CONVERSION) MEM-REG 2.6 IlS 2.8 IlS
·
REG-MEM 2.9 IlS 3.1 IlS h

· :h

Several relationships among these execution By providing an external register file on the
·
times are of interest. An ADD or MUL Single RT PC FPA, the Floating Point Register (FPR) Register
set 31
memory-to-memory is only 0.4 IlS slower than single-precision write float register command
the register-to-register version of the is reduced to 1.9 IlS measured at the FPA
commands. An ADD or MUL Double memory- interface. The single-precision read float o 4 5 8
to-memory is only 1.0 IlS slower than the register (into ROMP register) command is Register
Register set Register file
register-to-register versions. The time to load reduced to 2.2 JJS. It should be noted that the 10 address address
one single precision operand into an NS32081 corresponding times using the internal register
register is 2.6 IlS, or 2.2 IlS slower than registers would increase by approximately 1.5
Figure 3 External Register File Organization and
executing an ADD or MUL using the same IlS in the FPA system due to interface delays, Addressing
operand memory-to-memory versus register- becoming 4.1 IlS and 4.4 IlS respectively. The
to-register. The time to load a register double result is a savings of 2.2 IlS for both FPR the last two are reserved for status and
is 1.8 IlS slower than executing an ADD or reads and writes. system use, providing the user with 14 FPRs,
MUL memory-to-memory versus register-to- or six more than are provided internally by
register. The times to move an operand to Since the ROMP can transfer a maximum of the NS32081. A command is provided which
memory are slightly slower still. 32 bits in a single bus cycle, two FPR read or changes the register set pOinter and restores
writes must be used to handle double- the FPA status register associated with the
While adds and multiplies are the most often precision operands. Thus, the savings is new register set. The register sets may be
used floating point arithmetic operations, doubled or 4.4 IlS per double-word move. allocated to different tasks in the same or
loads and stores occur even more often. In (ROMP Load and Store Multiple commands different jobs. For this reason, the register set
particular, at least one non-register-resident could have been used to move double- switch command (called 'Task Switch') is
operand is needed for most floating point precision operands, but doing so did not executable only from the ROMP supervisor
operations. Computations commonly seem justified.) state. Figure 3 shows the organization of the
occurring in engineering and scientific FPA's external register file and the associated
problems such as matrix inversion, dot Once the external register file logic is added, address register.
product evaluation, and polynomial evaluation the cost to expand the number of registers in
seem to have this characteristic. Fast load the file and to provide multiple register sets is
and store commands are one key to the minimal. The RT PC FPA has 32 sets of 16
performance of a floating point accelerator. 32-bit registers. Of the 16 registers in a set,

23
A Lock command (executable only in write (Store), virtual or real addressing mode, As an example, suppose that the ROMP
supervisor state) is provided which places the and problem or supervisor state. The Virtual issued a "Fadd short FPR1 to FPR2 into
FPA in a mode where it will execute only a Resource Manager (VRM) reads the FPA's FPR2" to the FPA (FPA command 1 in Figure
few special supervisor state commands in its Status Register (FPASR) and finds that the 4) and that FPR1 contains a denormalized
instruction set. This command is used when FPA caused the Program Check. The FPASR, number. The NS32081 cannot process
the RT PC supervisor switches to a task register 14 in a set, also contains information denormalized numbers so the FPA would
which does not use the FPA, to prevent indicating the reason help was requested. return a reply with 'Exception' asserted when
inadvertent alteration of another task's FPA VRM passes control and the contents of the it tried to execute FPA command 2. The
state. FPASR to the supporting software. This FPASR would next be read by VRM. When
program, called FPFPX, can read register 15 FPFPX is activated, it would read FPR15 and
Exception Handling to determine what the command was. It can find a valid Fadd short command. It would
The NS32081 supports the IEEE 754 Floating also read the contents of the FPRs specified then read FPR1 finding the denormalized
Point Standard, but requires external software by the command. FPFPX completes the number. The command would be emulated in
support for a fully conforming implementation. operation if possible and causes execution to accordance with the IEEE Standard to
Thus, an efficient mechanism is needed to resume at the proper point using information produce the correct result, which would be
allow the FPA to request assistance from saved when the Program Check occurred. stored by FPFPX in FPR2. FPA command 2
software as necessary and resume normal would then be reissued as shown by VRM
execution at the proper point. The ROMP There is, however, one problem. The section and control returned to the active task.
could read the FPA's status after each on overlapped operation between the ROMP Normal execution would resume.
command to determine if assistance is and the FPA states that the reply is sent back
needed. While this approach would maintain to the ROMP shortly after execution is begun Conclusions
synchronization between the ROMP program in order to facilitate the overlap. While some Several methods for enhancing performance
and the FPA, it is hardly an efficient types of exception conditions such as parity in floating point accelerators have been
mechanism. errors and illegal commands can be detected discussed. Overlapped processing between
before the start of execution, others such as the ROMP and the FPA allows each to
The FPA uses the ROMP Program Check overflow, underflow, and inexact result cannot process at a faster rate and still maintain
mechanism to signal the ROMP when it needs be until execution is complete. The problem is synchronization with the other. The external
support to conform to the IEEE 754 Standard solved by reporting these exception register file provides increased read and write
or to report a floating point exception as conditions in the reply for the following FPA FPR performance by taking advantage of the
defined in the IEEE Standard, i.e., overflow, command. If one of these conditions is fact that in the NS32081 relatively little time
underflow, divide by zero, invalid operand, or detected, the command which caused it is penalty is incurred in using externally versus
inexact result. Thus, if the FPA detects a saved as are the unaltered FPRs (0-13). The internally stored operands. Expanding the
situation in which it needs assistance, it FPASR is set to indicate the exception register file to multiple register sets enhances
signals an 'Exception,' causing a ROMP condition. When the next FPA command is task switching performance. Use of the
Program Check. It does not alter any of the received, its reply is returned immediately with ROMP Program Check mechanism to notify
data registers and copies the command the 'Exception' line asserted. The new the executing program of FPA exception
needing assistance into register 15 command itself is discarded, but will be conditions provides an efficient, synchronous
(numbering from 0) of the active register set. reissued by the VRM after FPFPX processing exception handling mechanism.
The 'FF' portion of the command is implicit if normal processing can continue. Figure 4
and is therefore replaced by information shows how such an exception is reported, The RT PC Floating Point Accelerator
(received with the command) on the ROMP how the result might be corrected, and how improves system performance of the
state when the command was issued. Some normal execution is resumed. Whetstone bench mark from approximately
of the items contained are bus read (Load) or 12K WIPS (Whetstone Instructions Per

24
ROMP Activity FPA Activity Comments

(FPA initial conditions - IDLE and No Exception on previous command)

FPA command 1 •
Receive command 1
......-Reply 1 wlo exception Start execution of command 1

T
Non-FPA

FPA command 2 -----il.~

I
Command 1
execution
Command 2 queued

T
Inst fetch

1 ........---Reply 2
with exception
Return exception for command 1

T
Read FPA
status I I
....... . - - - Reply Rd Stat
Receive read status
Execute read status

wlo exception
Re-execute
command 1
in FPFPX
ROMP Re-executes command 1 in FPFPX
1-
FPA command 2 -----il.~
(re-issued) Receive command 2
......-Reply 2 wlo exception Start execution of command 2

T
Command 2
execution

Figure 4 Exception Processing between ROMP and FPA

Second) to approximately 125K WIPS in the

compatible mode and over 200K WIPS in the
direct mode.

References
1. D.E. Waldecker, C.G. Wright, M.S. Schmookler, T.G.
Whiteside, R.D. Groves, C.P. Freeman, A. Torres,
"ROMP/MMU Implementation," IBM RT Personal
Computer Technology, p. 57.
2. National Semiconductor Corporation, Series 32000
Instruction Set Reference Manual, pages 8-11 and
8-12.

25
System Board and I/O Channel for the IBM RT PC System

Sheldon L. Phelps and John D. Upton

Introduction has no RS232 serial ports and two less I/O The first logic partition of the 10CC is the I/O
The IBM 6150 and 6151 system boards are slots. The logic hardware design of the two Channel Converter. It is the function of this
designed to efficiently support the new IBM system boards is the same. This allows the logic to demultiplex the 32-bit processor
32-bit microprocessor (ROMP). The system same system software to be used. channel and generate the signals needed to
board integrates the processor card, the emulate the 8/16-bit PC I/O channel. An
system memory cards, and the I/O The system board contains two major groups internal 16-bit data bus is generated on which
subsystems. The 32-bit address and data of logic. These are the I/O Channel resides the I/O Subsystem. The I/O Channel
structures of the ROMP are translated into Converter/Controller (IOCC) and the I/O Converter handles data width translations to
the 8 and 16-bit PC and PC AT compatible Subsystem. The 10CC contains the logic that and from the 32-bit wide processor channel to
I/O channel by the Input/Output Channel emulates the PC I/O channel while the I/O the 8/16-bit wide I/O channel data bus. The
Controller (IOCC). Subsystem incorporates the adapters and second function of the Converter is to
system support functions normally found on implement the protection mechanism for the
The partitioning of the design and some of the IBM PC, PC XT and PC AT system I/O channel and I/O Subsystem. It does this
the major hardware divisions were governed boards. Figure 1 shows a conceptual layout by selectively disallowing certain accesses to
by the physical size of the system boards. of the functions on the system boards. the I/O channel and I/O subsystem. This
Other decisions were based on the size of the gives the RT PC Virtual Resource Manager
system units and the cost of the item. While The 10CC is responsible for translating the the ability to protect system resource integrity
the system board design was constrained by RT PC 32-bit processor channel to one in a multi-user configuration. The final
physical size, the objective of flexibility was compatible with the IBM PC product family. function of this logic partition is to report
met in many areas by the use of Much of the design of the IOCC was driven error conditions to the ROMP and maintain
approximately 20 Programmable Array Logic by the need to provide features which would status information on the state of the system
(PAL) devices. The PALs allowed design enhance the system's use in mUlti-user board for use in error recovery.
changes with minimal impact to the system environments. Because of the complexity of
board layout and schedules. its logic and a very short design schedule, The second partition of the 10CC is the I/O
much of the 10CC is implemented in Channel Controller. This is the logic that
This article will include information about Programmable Array Logic. This design controls the flow of data and addresses on
configurations, design features, data transfer approach resulted in a compact, flexible the I/O channel. The controller logic also sets
methods and I/O channel performance. design which was easy to modify as the up the proper data alignment on the I/O
system design point was refined. channel for each transfer. Finally, the
System Boards Controller has responsibility for the protection
There are two basic system boards for the The 10CC function is accomplished using of system board resources from alternate
IBM RT PC system. The system board of the three groups of logic. Together they make up controllers operating on the I/O channel.
IBM 6150 (floor-standing unit) and the system about fifty percent of all logic on the system
board for the IBM 6151 (table-top unit) are board. The logic groups are known as the I/O The last logic partition of the 10CC is the
functionally the same, except the IBM 6151 Channel Converter, the I/O Channel Controller Address Translation Controller. This logic is
and the Address Translation Controller. used during Direct Memory Access (DMA) to

26
 Floating point 32-bit 32-bit ECC data, the destination memory (I/O channel or
accelerator processor memory card
socket socket sockets system), and in the case of system memory,
the translation mode (real or virtual).

The I/O Subsystem on the system board

Memory Channel
provides the basic system functions found in
32-bit
Processor the IBM PC product family. This gives the
Channel RT PC system a high level of compatibility
with preexisting PC family hardware adapters.
I/O channel I/O channel
The I/O Subsystem resides on the Internal
I converter protection
Channel as shown in Figure 1. This channel is
isolated from both the processor channel and
16-bit
internal (on System Board) the I/O channel.
channel

The DMA facilities on the system board are

Translation 1 I Interrupt very similar to those found on the IBM PC
I Controller
I I Controller
1 AT. Standard 8237 A DMA Controller modules

I I I
are used. The DMA controllers allow the use
of either 8-bit or 16-bit devices and support
16-bit alternate controllers. The two DMA
I
DMA
Controller
I I
Real Time
Clock
1 controllers are not cascaded together. All
channel arbitration is implemented in separate
Keyboard &
Keyboard logic to enhance performance.
connector
locator
adapter Locator
connector In addition to the seven DMA channels of the
System Board
PC AT, the RT PC system supports an eighth
I/O Channel

I Controller protection
Dual port Port A
channel for the RT PC 80286 Coprocessor.
This extra channel supports a specially
serial connector
communications Port B
modified arbitration protocol for coprocessor
~ B/16-bit controller* connector applications. The special arbitration allows the
I/O Channel
coprocessor to use the I/O channel while the
ROMP executes out of system memory. The
coprocessor will relinquish the I/O channel
whenever any other device needs to use it.
I/O card sockets: AT AT AT AT AT PC AT* PC*
Like the PC AT, I/O channel memory refresh
is generated with special logic. This logic,
Figure 1 Block Diagram Of System Board
*Items on 6150 only. however, differs in that refresh is executed in
a burst manner. To minimize I/O channel
couple the 32-bit address space of the RT PC spaces, the Address Translation Controller is overhead from refresh, the system will wait
processor channel with the 16/24-bit address also capable of relocating addresses during until at least five refresh cycles are required
space of the IBM PC and PC AT. In addition the DMA transfer. This relocation is used to before requesting service. The refresh logic is
to its function of coupling the two address specify the new destination address for the capable of saving up to 16 refresh requests
between uses of the I/O channel.

27
Included on the system board is an capability and to give flexible control of the Since an alternate controller operating on the
MC146818 Real Time Clock module. This RS232C interface signals. I/O channel only has access to 24 address
device maintains time for the system and also bits, the Address Translation Controller
contains system configuration information. Address Translation and Protection provides a programmable means of allowing
Keeping system configuration data in a Since the RT PC systems were designed with access to the system memory address space.
battery backed RAM eliminates the need for multi-user capability in mind, logic was Also, additional logic is provided to allow the
user changeable jumpers on the system incorporated into the system board to allow alternate controller to select real or virtual
board. In addition to saving system data and several addressing modes and provide for addressing when the destination is system
keeping time, the module is used to generate system resource protection by the operating memory. If desired, the Address Translation
the system "heartbeat" timer for the ROMP. system software. These features are not Controller may be programmed to allow the
generally required for a single-user, stand- alternate controller to run using I/O channel
The system board uses two 8259A alone system. Address translation is used attached memory.
Programmable Interrupt Controllers to only during DMA operations. Two distinct
implement the interrupt system. These address translation modes are supported on The heart of the Address Translation
controllers are not cascaded. They are the system board. Each has a specific design Controller is the array of Translation Control
connected to two separate ROMP interrupts. point and use in the RT PC system. Similarly, Words (TCWs). The TCWs are actually a 1K
This allows the ROMP early knowledge as to there are two ways in which the adapters on by 16-bit high-speed RAM. Each word of the
the priority class of the interrupt. The interrupt the system board are protected from TCW is an address translation element. Half
controllers are isolated from the I/O channel unauthorized access. of the TCWs are used by Page Mode to map
by logic which allows diagnostic software to a 2K-byte section (a page) of system memory.
emulate interrupts during system Power On The RT PC system utilizes a 32-bit address The other half is used by Region Mode to
Self Tests. bus on the processor channel and yet has a map 32K-byte sections of system memory.
16/24-bit address bus on the I/O channel. The The DMA Mode Register on the system board
An 8051 microprocessor is used for the coupling of these two address spaces is is used to determine which type of TCW word
system console input devices. The logic handled by the Address Translation will be used for a given DMA channel.
supports attachment of the RT PC system Controller. For a Processor Input/Output (PIO)
keyboard and the RT PC system locating cycle, the I/O channel is seen as one of two The half of the TCW entries dedicated to
device. The locating device interface uses a 16M-byte segments in the 32-bit address Page Mode is further divided into eight
serial RS232C-like interface protocol. This space. Accessing either segment results in a groups of 64 entries each. Each of the groups
flexibility allows the attachment of other transfer cycle on the I/O channel. The result is used to provide the address mapping for a
RS232C input devices. The speaker for the is that the 64K-byte PC I/O address space single DMA channel. In this way each DMA
RT PC system is mounted in the keyboard. and the 16M-byte PC AT memory address channel is allowed to transfer up to 128K
Besides its normal use as an audio output space are mapped into the 32-bit address bytes of data. The remaining half of the TCWs
device it also is used to provide audio space on the processor channel. is shared by all DMA channels operating in
feedback for key depressions on the soft- Region Mode. In this mode, each TCW entry
touch keyboard. DMA devices present a unique problem to the maps 32K bytes of memory. Thus region
system board. The DMA Controllers are mode devices can access all of the 16M-byte
The IBM 6150 also has two Serial capable of generating only 16 bits of address address space. The Address Translation
Communication Ports on the system board. on their own. Thus the Address Translation Controller can be set up so that some
These ports are implemented with a single Controller must supply the remaining 8 bits if portions of this address space are mapped to
8530 Serial Communications Controller the destination is the I/O channel and the the I/O channel-attached memory while others
module. Additional logic is provided on the remaining 16 bits if the destination is system are mapped to system memory.
system board to support DMA transfer memory. Furthermore, it must determine the
proper destination bus for the data.

28
 Processor
Protection of valued system resources is the operate properly on the I/O channel. card 1""'1-11-1-0X-O-O-r-I----r-----r------.I
key to a maintainable multi-user system. The However, it must be pOinted out that they will channel . . .
address 0 7 8 31
RT PC system incorporated several protection require the RT PC 80286 Coprocessor card to
mechanisms into the 10CC design point. Each
of these protection functions is
operate them unless special programs for the
ROMP are written to drive them.
~~nnel
select
I
MSB LSB
I
programmable, for greater flexibility. I/O I I
The 10CC on the RT PC system board
channel
address
I23 0
I
First, the PC I/O channel may be protected performs the necessary transformations
MSB = Most significant bit
from access by an application program. This between the processor channel (IBM protocol) LSB = Least significant bit
protection is separate for the I/O and memory and the PC AT compatible I/O channel.
address spaces. The operating system always Figure 2 Processor Card Channel to I/O Channel
has access to the I/O channel, while Two methods of data transfer are used in the Addressing
application programs may be disallowed from RT PC system. They are Processor Input/
accessing either the I/O map, memory map, Output (PIO) and Direct Memory Access mode. An alternate controller is an adapter
or both, on the I/O channel. This ensures that (DMA). When PIO is the method of data that is capable of gaining control of the I/O
the operating system has complete control transfer, the I/O channel address is coming channel and driving the address and control
over, and always knows the state of, each from the address/data bus of the processor lines to perform data transfer. Alternate
system resource. This protection helps keep channel. Addresses on the processor channel controllers are limited to 16-bit adapters, but
a wayward application from crashing the can go to several different places. Therefore, can operate on any DMA channel. A DMA
whole system. the 10CC will only respond to those device is an adapter that requires the DMA
addresses which are being sent to it. Figure 2 controller on the system board to drive
Secondly, the system board resources may shows the format of the 32-bit address on the address and control lines in order to perform
be protected from illegal access by an processor channel. Bits 0-7 of the processor the data transfer. Addressing from the I/O
alternate controller. The RT PC 80286 channel address select the I/O channel as the channel to the processor channel is handled
coprocessor is one such controller. A destination of the address. Bits 8-31 are the by a DMA controller and uses the Translation
programmable mechanism exists on the I/O channel address. This method of Control Words (TCWs).
system board that will selectively disallow addressing is used by ROMP to send control
access to certain system board hardware information and data to the 10CC, I/O The 10CC handles data alignment as shown
resources (DMA controllers, for example). subsystems and I/O devices. in Figure 3. ROMP always uses the IBM
Three groups of system board logic can be convention for its operations. This is shown
separately protected from access by an When the addresses are gated on to the I/O on the line titled "Processor card channel
intelligent device on the I/O channel. Each channel address bus they are sent to all of data." A "WORD" on the processor channel
group contains system resources of a the address lines SAO-SA 19 and LA 17-LA23. is 32 bits, with bit 0 being the most significant
different level of importance to system They are held valid for the complete I/O cycle. bit and bit 31 being the least significant bit.
integrity. In this way the system can be Therefore, Bus Address Latch Enable (BALE) But a "WORD" on the I/O channel is 16 bits,
insulated from programming errors on is not driven on the I/O channel by the with bit 0 being the least significant bit and bit
intelligent adapters or coprocessors. system board. It will remain active throughout 15 being the most significant bit. This is the
the cycle. convention used by the IBM PC compatible
I/O Channel Operations and Data Transfer I/O channel. For example, bytes A and Bare
The I/O channel on the IBM RT PC system is DMA is the second method of transferring the most significant bytes on the processor
designed to be compatible with the IBM data on the I/O channel. DMA has two modes channel. The bytes go through two transforms
Personal Computer family. Most adapters of operation; one method is the alternate to get to the 16-bit I/O channel. The
designed for the IBM PC or PC AT will controller mode and the other is DMA device transforms are done in one step. They are

29
Processor
card
channel
data 0
I
MSB
A
7 8
B
I
1516

t
e
I
2324
D I
31
LSB
4). This applies to reads also. Buffer Mode
DMA is limited to use by alternate controllers.
Data transfers must begin on a double-word
boundary. Bandwidth on the I/O channel is up lace
r
(XXOO)
I A B
r
Double word address boundary

(XX10)
I
Word address boundary

[ lace I to 2 megabytes per second when an adapter 0 15 16 2324 31

I is designed to transfer data using both buffer 7f
1
I Intermediate step showing and burst mode OMA. I/O
I
7
A
015
B
reversal of 0&7 and 8&15.
channel
data 15
B
I
8 7
A
0
I
8
LSB MSB Interrupt sharing is being used to solve the
I/O problem of the limited number of interrupt
channel
I B
I A I Complete transform levels available on the PC I/O channel. It is
First step in Buffer Mode DMA transfer
data 15 87 0
MSB LSB also used to resolve some conflicts (two

Figure 3 IOCC Data Transformations

shown in two steps for clarity. First the 10CC

adapters designed to use the same level) and
to allow multiple adapters of the same type to
use a single level. The shareable interrupt
circuit is compatible with PC and PC AT. lace
r
(XXOO)
I A B
r
Double word address boundary

(XX10)
leD
Word address boundary

transfers the bits as-is, with only the numbers Adapters with shareable interrupt circuits and o 7 8 15 16 2324 31
of the bits being changed. That is, bit 0 is
renumbered to bit? and bit? to bit O. The
adapters with nonshareable interrupt circuits
can be plugged in at the same time. Only one I/O
•
10CC also reverses the bytes themselves. type can be enabled at a time on anyone channel B A

interrupt level.
data 15 87 o
The ROMP can direct 32-bit writes to the I/O
Conclusion Second step in Buffer Mode DMA transfer
channel. The 10CC receives the 32 bits as
shown in Figure 3. The 10CC will then send The RT PC system boards have an IBM PC
bytes A and B to the I/O channel for a 16-bit and PC AT compatible I/O channel with a Figure 4 Buffer Mode DMA Transfer
device, then multiplex processor channel maximum I/O channel bandwidth of 2
bytes C and D to the 1/0 channel in the same megabytes per second. A single system through the TCWs and control of buffer and
manner as bytes A and B (as described board design was implemented for both the burst mode DMA operations from the !/O
above). This is done in separate I/O cycles. If IBM 6150 and the IBM 6151. Because of channel.
the adapter is an 8-bit device, the 10CC will packaging constraints, two I/O slots and the
multiplex each byte A, B, C, and D separately two Serial Ports were removed from the
to the I/O channel on SOO-SO? implementation of the IBM 6150. Some of the
new features of the RT PC system boards are
The RT PC system is introducing its own the facilities of the 10CC. They include
versions of burst mode DMA and buffer mode protection of the important system registers
OMA. Burst mode OMA allows an alternate from intelligent devices on the I/O channel
controller to take several I/O channel cycles and special address alignment from the
each time it gets control of the I/O channel. processor channel to the I/O channel. The
Buffer mode DMA describes an alternate 10CC also includes the logic to handle all of
controller performing two 16-bit memory the data alignment and multiple cycle
writes to the 10CC before the 10CC writes to requirements for the processor channel's 32-
system memory. System memory bandwidth bit data bus to the I/O channel's 8/16-bit data
is improved because only one 32-bit write is bus. Also included on the system boards is
done rather than two 16-bit writes (see Figure the logic and memory for OMA addressing

30
IBM RT PC Displays and Adapters

Joe C. St. Clair

Introduction displaying 720 by 512 pixels; a 14-inch color APA8 and APA8 Color Adapter Functions
AII-points-addressable displays allow a wide monitor with a 0.31 millimeter shadow mask The APA8 display adapter provides a single
variety of applications, from windowed text that has the same refresh rate and pixel plane of 64K bytes of memory. The color
processing to graphics, to be run on a format and displays 16 colors simultaneously version, the APA8C, provides four planes of
system. However, this flexibility comes at a out of a palette of 64 colors; and a 15-inch memory identical to that found on the
price. The large number of picture elements black and white monitor with a 60-Hertz monochrome adapter, for a total of 256K
(pixels) that must be processed can make it non interlaced refresh rate displaying 1024 by bytes of memory. Both cards have a unique
difficult to update the screen rapidly. To solve 768 pixels. The 12-inch and 14-inch monitors byte-overlapped memory organization.
this problem for a range of applications that can display 25 lines of 80 characters using
have different cost-versus-function needs, a the standard 9-pixel by 20-pixel character The APA8 and APA8C display adapters'
family of three all-points-addressable display box. With the 15-inch monitor, 38 lines of 113 unique memory organization allows the
adapters has been designed. This family of characters can be displayed using the same ROMP to access the bit map without
adapters solves the problem of updating the character box. Because the display adapters encountering any word boundaries. This is
display screen rapidly with a combination of that drive the monitors are all-points- done by having successive 16-bit words
techniques. First, all three family members addressable, character boxes of any size may overlap each other by one byte. Thus, any 16-
use innovative bit-map memory organizations be used. All three monitors provide tilt and bit word can be written into the bit map with a
that allow the pixels to be accessed easily. rotate pedestals, have an antiglare treatment, single memory operation. This memory
Second, performance assistance hardware on and have equal spacing between horizontal organization is particularly efficient when
the cards provides help to the ROMP in and vertical pixels (square pixels). displaying text composed of character boxes
manipulating the pixels. For the two smaller that are the usual nine pixels wide. Without
members of the family, this consists of Each of the three display adapters that drive this unique memory, half the character boxes
special data paths on the card that, among the monitors provide the ROMP with would bridge two words and so would require
other things, work with the system processor performance assistance hardware that allows special processing by the ROMP. With this
to move pixels in the bit map. The largest the bit map to be updated quickly. The entry organization, all character images on the
family member has a display command level display adapter is the AII-Points- screen are treated the same.
processor that can process lists of display Addressable-8 (APA8). It drives the 12-inch
commands with a minimum of help from the black and white monitor. The APA8C is a Mode bits in the control registers on the
ROMP. The third way that the display adapter direct extension of the APA8 to allow it to APA8 and APA8C display adapters can be set
family solves the screen update problem is by drive a color monitor. The AII-Points- to configure the bit map memory so that 16-
using a range of technologies that includes Addressable-16 (APA 16) display adapter bit words written into the bit map appear on
CMOS standard cells, bipolar gate arrays, drives the 15-inch black and white monitor. the screen either as two successive
and surface-mounted components. The three adapters provide successively horizontal bytes or with one byte atop the
greater levels of assistance to the other. Also, an overlay mode is available so
The display adapter family drives three microprocessors in updating the bit map. that new information written into the bit map
monitors: a 12-inch black and white monitor Each of the adapters takes up one slot in the is "OR"ed with the information already there.
with a 92-Hertz interlace refresh rate RT PC.

31
This avoids many of the read-modify-write Figure 1 shows a block diagram of the APA8 custom ICs. However, because the cells
cycles usually needed when updating display monochrome display adapter. The APA8C is themselves are like small custom ICs,
bit maps_ identical except that it has four copies of the typically implementing such functions as flip-
bit map and logic unit. Also, the video output flops and multiplexers, they are smaller and
Both adapters also help the ROMP move passes through a look-up table before it goes have better performance than their gate array
blocks of pixels around in the bit map and to the monitor. equivalents.
between the main store and the bit map_ To
help move pixels within the bit map, the cards These two adapters use CMOS standard cell APA8 Color
provide a set of registers, barrel shifters, and integrated circuits to achieve a high level of On the color display adapter, a plane
logic units that realign pixels within bytes. function at a low cost and with minimum protection mask register can be used to
Using this hardware assistance, the ROMP power dissipation. Standard cell technology prevent any of the four bit-map planes from
can move and realign 16 pixels at a time by occupies a place between gate arrays and being updated. This adapter also provides a
reading from a source address and writing to custom integrated circuits in terms of both color expansion function that allows all
a destination address. Hardware on the card cost and development time. Like custom ICs, unprotected planes to be written
takes care of realigning, masking and merging it requires that a full set of masks be simultaneously. When using this function, a
the source data before writing it to the generated for each circuit. However, the bit written by the system processor to a value
destination. Optionally, the data can be development time and cost is considerably of "ONE" is converted into a
inverted before being written back into the bit less because the technique puts constraints "FOREGROUND" pixel color before being
map. The color adapter operates on all bit on the IC designer. A standard cell circuit is written into the bit map planes, and a
map planes simultaneously and so can built from a library of cells all having the same "ZERO" bit is converted into a
perform data moves at the same speed as height. These cells are arranged into rows "BACKGROUND" pixel color. The
the black and white adapter even though it with variable spacing between the rows to "FOREGROUND" and "BACKGROUND" pixel
must move four times as many bits. Both allow for wiring. The constraints on the colors are defined by a value written into a
adapters have an autoincrementing pOinter circuit's physical design allow automatic control register. The color display adapter
that can be used to address the array when placement of the cells and interconnect also has a color look-up table that maps the
moving blocks of data between the bit map wiring. The automation reduces both design 16 possible pixel values into the 64 possible
and system memory. costs and turnaround time compared to color values that can be displayed by the
monitor.

24-bit system
In order to fit the extra bit map planes and
address
System
Address
-2... 720 x 512 304 x 512 CRT function onto the color display adapter,
bus Video
inter- refresh
inter-
face logic out surface mount technology is used. Small
16-bit system
data/commands
face .--:L..- "Visible" "Hidden"
outline (SO) packages and plastic leaded chip
bit map bit map
carriers (PLCC) are used for most of the
components on the card. These packages
take up less card area than more
Logic
conventional dual-inline-pin (DIP) packages.
unit The PLCC package is particularly attractive as
an alternate to 64-pin DIP packages and pin
grid arrays. Such large DIPs make inefficient
use of card space and present reliability
Figure 1 APA 8 Display Adapter Functional Diagram problems because of differences in the
thermal expansion coefficients between the
DIP and the card on which it is mounted.

32
PLCC packages have considerable cost
~
24-bit system
advantage over pin grid array packages. address
System BAMDA CRT
bus address 1024 x 768 Video
refresh ......
inter- inter- "Visible" bit map out
16-bit system logic
APA 16 data/commands
face face r--l+-
The APA 16 display adapter drives the 1024
by 768 pixel 1S-inch black and white monitor.
Because of the larger number of pixels this
adapter must manipulate compared to the
Logic 1024 x 256 Hardware
APA8 and APA8C adapters, it provides more unit cursor I--
"Hidden" bit map
extensive hardware on the card to help the
ROMP. This additional hardware includes a
unique bit-map addressing scheme, a

--
command processor, and a hardware cursor.

Figure 2 is a block diagram of the APA 16.

This display adapter provides 128K bytes of
... Display
control
1024 x 40 bits
Read-only storage

memory. The first 96K bytes of this are

scanned out to the monitor to form the image.
Figure 2 APA 16 Display Adapter Functional Diagram
The remaining 32K bytes are used by the
display controller located on the card. The reads from main store can also operate
down-load the command list from main store.
In this mode of operation, the non-displayed on two-dimensional arrays of bits. Blocks of
The bit-map addressing scheme used on the
portion of the bit map acts as a cache for the bits read from main store can replace blocks
APA16 is called a Bit Addressable,
display controller and the main store is used of pixels in the bit map or they can be
Multidimensional Array (BAMOA). The BAMOA
to hold the extended display command list. merged with bit map data just as they can
memory organization allows up to 16
when doing merge operations entirely within
contiguous pixels to be accessed in a single
The set of commands for the display the bit map. These operations can also rotate
memory cycle along either the horizontal or
controller includes operations to draw lines, and mirror data just as the intra-bit-map
vertical screen axis and to begin at any
manipulate blocks of pixels (BITBLT), read operations can.
arbitrary pixel boundary. This BAMDA allows
from main store (DMA), and control the flow
vertical lines to be drawn at the same speed
of instructions. The coordinates for line The flow control instructions to the display
as horizontal lines. It also allows tall and thin
drawing can be in either absolute or relative controller include a branch, a subroutine call,
areas, such as character boxes, to be
screen coordinates. The basic operations that a return from subroutine, a wait for scan line
manipulated efficiently.
manipulate blocks of pixels include count, and several instructions that will
rectangular area fill, copy, and merge source interrupt the ROMP under various conditions.
The system processor can either update the
area with destination area using any of These flow control instructions allow the
bit map directly by writing to the BAMOA
several logical operations. The copy and display controller to execute complex lists of
memory, or it can load commands into a
merge operations can simultaneously rotate display commands with little or no
display controller located on the adapter and the image ( - 90°, - 180°) or mirror it about intervention from the ROMP.
let it update the bit map. Lists of display
the X or Y axis. These basic operations can
controller commands are executed out of the
be chained together to perform more complex The APA 16 also provides a hardware cursor.
non-displayed portion of the bit map. These
BITBLTs. This is a 384-byte section of hidden bit map
command lists may be loaded directly into the
non-displayed bit map by the system
processor or the display controller itself can

33
that is displayed on the screen overlaying the
primary bit map image. It appears as a 48 by
64 pixel block with the position of the block
determined by values loaded into registers on
the card.

Like the other members of the family, this

adapter uses LSI technology to allow a high-
function display to fit onto a Single PC card.
Because of the high speeds needed on large
screen display adapters, bipolar gate arrays
are used on this card as well as CMOS gate
arrays. The display controller located on this
card is implemented as a programmable
sequencer using a bipolar gate array and
horizontal microcode. Other bipolar arrays
provide a data path for the pixels. A CMOS
gate array and video DRAMs that include an
internal address incrementer provide the
BAM DA memory.

Conclusion
This family of display adapters uses a range
of bit-map architectures, performance
assistance hardware, and technologies to
provide solutions to a spectrum of
app!!cat!ons that !nc!ude graphics and high-
function text. The two adapters that drive the
smaller monitors use byte overlapped bit map
arrays and CMOS standard cell ICs to assist
the ROMP. The color display adapter uses
surface-mount technology and provides extra
assistance to the ROMP by allowing all
planes to be manipulated simultaneously. The
adapter for the 1S-inch monitor uses CMOS
and bipolar gate arrays and video DRAMs
with address incrementers to provide
extensive performance assistance hardware.
This includes a bit-addressable, multi-
dimensional array bit map, a
microprogrammed display controller, and a
hardware cursor. All three adapters ease the
burden of the ROMP in updating the bit maps.

34
Use of Artificial Intelligence to Diagnose Hardware

Nancy A. Burns and C. Edward Williams

The Design Problem and artificial intelligence offered the In an effort to limit user interaction, it is
The diagnostic software package for the IBM opportunity to extend the state of the art. desirable to have the expert system learn the
RT PC is designed to provide both operators answers to its own questions, if possible.
and service representatives alike with the The General Purpose System for Inferencing This required that a method be created for
ability to diagnose the hardware, isolate faulty (GPSI) was chosen as a basis for the expert indicating that a series of specific test results
parts, and replace them with new parts. This system needed to meet these challenges is equivalent to the answer to a single
strategy provided many interesting challenges because of its characteristics and structure question posed to the user.
in the design of the RT PC diagnostic system. [1]. GPSI is an expert system shell developed
The program would be running on a machine at the University of Illinois under the funding Since real memory size is limited, and
suspected of having faulty components, of the IBM Scientific Center in Palo Alto, CA. hardware configurations are variable and
controlling and analyzing the results of It was designed for diagnostic and interpretive volatile, a method of segmenting the
hardware tests run on itself. Memory space applications. Written in Pascal and running on knowledge base is needed. When the expert
was limited to a minimum of 1 megabyte. an IBM Personal Computer, GPSI uses a rule system concludes that a particular component
Everything necessary for bringing up the base which consists of a forest of trees [2]. is present and needs testing, the rules
machine and running the diagnostics should Each tree contains a goal at its root, and necessary for the diagnostics of that
be diskette resident. Finally, the configuration evidences needed to substantiate this goal at component can be read in and used in
of the machine can be complex, variable, and its leaves. This structure reflects quite well isolating machine faults.
expandable. the complex, interrelated nature of hardware
diagnostic rules. Architecture
Solution The resulting RT PC diagnostic system is
The implementation of an expert system was The original GPSI system lacked many structured as illustrated in Figure 1. There are
chosen as the solution to the design problem features necessary to the diagnostics of a several layers of hardware and software
of RT PC diagnostics. Expert systems are small machine. Most significantly, there was which make up the system. At the lowest
programs that take knowledge encoded as no method of obtaining information except level is the RT PC hardware itself, controlled
rules and make conclusions on the basis of through asking questions of the user. by device driver software. The hardware is
the rules in much the same way as human Information found in the machine itself, such hidden from the application level by the
experts. Encoding knowledge in rule form is as error logs and status words, is much more Virtual Resource Manager (see Lang,
generally easier for human experts than reliable than users in isolating hardware Greenberg, and Sauer) which provides a
programming in a high level language. In problems. In addition, tests can be performed standard 110 interface to all devices and
addition, a rule base can be easily modified to on hardware, and the results of those tests manages the memory allocation. The
diagnose new components or even provide a clear indication of the problem diagnostic application has its own operating
completely different machines. This feature encountered. A method of invoking these system, the Diagnostic Control Program
should allow the same inference engine to be tests and analyzing their results was (DCP). The DCP is a virtual machine which
used in future development efforts. Finally, implemented. provides an AIX file system and a direct
since the limits of current diagnostic interface to the hardware device drivers.
technology had been reached, expert systems

35
Segment Table Real memory is divided up into 2048-byte makes it feasible to map a system's entire
Page 0 XPT page frames. A page frame can be thought of
Page 1
data base using a single set of virtual
for
Segment as a container for a virtual page. The Inverted addresses (the "one-level" store). With a one-
N Page Table (IPT) defines the virtual page that level store each segment can be large enough
Segment N
is currently associated with each page frame. to represent an entire file or collection of
Page 0 XPT The MMU uses the information in the IPT data.
Segment M Page 1 for
Segment when translating a virtual address into a real
M address and when determining if a protection This is possible because the address
violation has occurred[2]. The MMU will translation hardware only needs the location
respond with a page fault for any virtual of pages that are present in real memory. If a
Inverted Page Table memory reference that cannot be translated page is not present, the hardware must
using the information in the IPT. The IPT detect this fact, but it does not require the
contains one 32-byte entry for each page secondary storage address. The VMM does
Page Frame for Segment M
frame and is not pageable. need this information, however. Hence, the
VMM must keep this information in some data
Page Frame for Segment N Support a Large Virtual Address Space structure that is associated with the page. In
Virtual memory extends the power of the VRM this data structure is the external
computer memory by expanding the number page table. Unless this external page table is
of memory addresses that can be pageable, the advantage of the inverted page
Figure 1 Virtual Memory Data Structures represented in a system while relaxing the table is lost, because the pinned real memory
limitation that all addressable memory must requirements become proportional to virtual
A segment is divided up into 2048-byte virtual be present in real memory. The address memory size.
pages. A virtual page can be located in real translation hardware requires page tables
memory or on the disk. Each segment has an fixed in real memory to perform its function. Large and Sparse Segment Support
external page table (XPT) with one 4-byte The size of a conventional page table is The VMM supports segments of up to 256
entry for each of its virtual pages. The XPT proportional to the size of the virtual address megabytes. The VMM defines any segment
entries for a given segment are in contiguous space, placing a practical limit on the address that is one megabyte or larger to be a "large"
virtual memory and are therefore directly space size. segment. A large segment can be totally filled
addressable. An XPT entry describes the with data, assuming sufficient disk space. A
characteristics of its corresponding virtual Paged segmentation is a means of reducing large segment may also be lightly filled with
page, such as its protection characteristics this overhead. It takes advantage of the data that is scattered throughout the
and its location on disk. The XPT is pageable. grouping of related data in virtual memory by segment. This is known as a sparse segment.
representing page table data separately for
There is a pool of external page table entries each segment. This allows space savings for The external page table for a large segment
defined in the VRM [1] segment. The size of short or unused segments of the address can itself be fairly large. An XPT entry defines
this pool limits the size of the virtual address space. 2048 bytes of virtual memory. A page of XPT
space. The XPT for each defined segment is entries contains 512 of the 4-byte entries and
contained within this pool. The XPT for the An inverted page table further expands the defines 1 megabyte of virtual memory.
VRM segment defines each page in the VRM range of addressability by reducing the real Therefore, 256 pages of XPT entries are
segment, including the pool of XPT entries. memory overhead required to support a very required to define a 256-megabyte segment.
The subset of the VRM segment's XPT that large virtual address space. Since an inverted
defines the pool of XPT entries is referred to page table contains an entry for each page of Since the XPTs are pageable and reside in
as the XPT of the XPT. It is not pageable. real memory, its overhead is proportional to virtual memory, a subset of them describe the
real rather than virtual memory size. This XPT area itself. These are the XPT of the

127
 Knowledge questions and reporting goals. Records from
engineer
this file are read in one at a time when
+ needed.

Construct
The main CONSULT module consists of a
supervisor which is invoked by the system
1 System checkout
checkout shell. It communicates with the
operating system throughout consultation
I Text file
whenever new rule base segments need to be
Rule file
:......
Inference User The invoked or power turned off.
engine interface user

The inference algorithm, which performs such

tasks as the selection of goals, the chaining
Procedure I through trees, and the investigation of
Data
interface evidence structures, is also contained in the
r
main CONSULT module. This inference
I Procedures
I--
algorithm is explained in detail in the following
I--
section.
Standalone I
utilities
I f Independent modules, bound along with the
inference engine, contain the User Interface
Diagnostic control program Routines and the Procedure Call Coordinator.
These two modules contain all machine-
Virtual Resource Manager
dependent code. The user interface routines
r---------------., provide the code necessary for formatting,
: Hardware device drivers
: displaying, and retrieving of information to
and from the terminal screen. For the
Hardware diagnostic application, a full-screen, menu-
driven interface is impiemented.

Figure 1 Diagnostic System Architecture

The Procedure Call Coordinator for the
The expert system application is the indicating which parts, if any, are faulty, and diagnostics locates the code for a particular
uppermost level of software in the diagnostic returns the list of concluded goals to the procedure on the diagnostic diskette and
system. The system checkout shell presents system checkout program. loads this code into memory, dynamically
menus to the user and obtains information binding the code to provide addressability for
about the type of testing to be performed. It All rules used in the expert system are the expert system when so requested. In
calls the inference engine as a subroutine, precompiled by the CONSTRUCT program. addition, it builds input and output buffers for
passing it a list of values to be used in The output of the compilation process is two parameters passed between the two modules
controlling the inference process. The files. One file contains the information and manages the invocation of the procedure
inference engine reads in the rule base and necessary for building the data structures to on a procedure call request from the rule
gathers evidence by asking questions or be used during consultation sessions. The base being investigated.
running procedures. It then concludes goals other file contains the text for asking

36
The Inference Process
The knowledge base which drives the Hypothesis:
diagnostics is represented as a forest of one run all tests
or more n-ary trees. Each tree contains a goal
to be concluded or rejected at the root of that
tree. The leaves of the tree contain evidence
of several different kinds that can be acquired
I
by querying the user, executing external
f And
~
procedures, or referencing other nodes, trees,
or subtrees. Between the root goal and the I
leaf evidences are internal nodes representing
a variety of functions. AND, OR, and NOT I I
nodes can be used to relate evidences and External: External:
form rules of high descriptive ability. Other interfaceJest peripheralJest
return_code = 0 return_code = 0
types of nodes, such as the ALTERNATIVE,
WAND, PAND, IF, and the PREEMPT node,
introduce special structures used in
controlling the flow of execution. The addition
of new node types, as required by the External: Evidence:
application, is an easy enhancement because device_test 'yes' of
return_code = 0 interactive_mode
of the open architecture of the knowledge
base and the modularity of the code.

The consultation session of the inference

engine primarily uses backward chaining to
Goal:
make conclusions. Once a potential goal is device is bad
selected, the underlying tree is traced in a
post-order traversal which prunes off
unnecessary branches and gathers any
necessary evidence. The type of evidence to
be gathered is indicated by the type of leaf
nodes on the tree. An EVIDENCE node
indicates that data should be obtained by
asking the user a specified question. An 0.6 10 0.2
EXTERNAL node indicates that data will be r----- -----, ,---- -----,I r---- -- ---,
obtained through the execution of a specified I
I I
I I
I I
I
I
I
I
procedure. A REFERENCE node indicates I External: I I
I
External: I I External: I
I interfaceJest ran
I deviceJest ran I I peripheralJest ran
I
that a (sub)structure in some other rule must I & return_code = 0
I I
I
& return_code = 0 I I I
& return_code = 0
IL ___________ JI I I
L _ _ _ _ _ _ _ _ _J
I
be investigated to obtain the required IL... _ _ _ _ _ _ _ _ _ -'

information. The structure of a sample rule

tree is illustrated in Figure 2. Figure 2 Sample Rule Tree in Diagnostic Expert System

37
Each node of a rule tree has associated with unacceptable for an expert system residing Any evidence which is common to more than
it a confidence factor. For an EVIDENCE or and supervising hardware diagnostics on a one unit can be labelled 'GLOBAL'. This
an EXTERNAL node this confidence is based small machine with a variable configuration. information is copied onto a global list which
on an association factor given to the node by is passed between the calling rule base and
the knowledge engineer and the answer to During the diagnostic process, the amount of the rule base it calls. This allows information
the question asked or the value returned from memory available for the knowledge base to be passed between the individual rule
the procedure. A REFERENCE node assumes was restricted to approximately 170K bytes of bases.
the confidence value of the structure which it memory. Therefore, it is desirable to store
references. The confidence values of other only those rules relating to components Besides its usefulness for memory
nodes are calculated from the confidence of actually present and being tested in the management, the rule base call has also
its children. The computations used for these consulting machine. At the same time, proven useful for other reasons. Division of
nodes are dependent on the type of the node. however, the knowledge base should not the rule base allows separating the rule base
need to be changed for any configuration. To into segments of coherent knowledge
Multiple Rule Base Segmentation accomplish this goal, rules in the diagnostic structures. This makes rule writing and
In order for expert systems to simulate the application are segmented into contextual debugging easier and results in a more
reasoning processes of humans, they have units. Each segment contains all rules understandable rule base. Rule base calls
historically required vast amounts of necessary for the diagnosis of a single also allow the same rule base to be used
knowledge. In the past, this knowledge has hardware component and is read into memory several times to conclude goals about similar,
been stored in a single large knowledge base. only when needed. yet distinct, items. For example, only one rule
As a result, most expert systems run on large base is needed for diagnosing diskette drives,
computer systems and require large amounts An action can be associated with any node in although a hardware configuration may
of memory space for holding the complete a rule base to indicate that the state of the consist of multiple diskette drives.
knowledge base. This organization is current rule base should be saved, and a new
rule base should be paged in. This action will Knowledge Base Features
only be taken if the confidence of the current The knowledge base used by the expert
node is evaluated to be greater than the high system for diagnosing hardware problems on
threshold associated with that node. The new an RT PC consists of multiple rule base
ruie base is then traced until ail ruies have segments. The first rule base segment is the
I been evaluated. master rule base. The master rule base
1 I I executes procedures to determine the
Standard Standard Parallel Other
When all rules in the called rule base are configuration of the machine and then calls
fixed-disk diskette adapter exhausted, the original rule base is reloaded, device rule base segments to test the devices
devices ...
rule base rule base rule base
and the tracing of it is resumed from the point which are present. Each device rule base
I at which it was suspended. Answers gathered segment tests one or more of the device
Feature in the called rule base and referred to in the options. The entire diagnostic system resides
disk original rule base are passed into the original on diskette and includes all rules necessary
rule base
rule base. Goals concluded in the called rule to test the work station in any mode.
base are appended to the list of goals
I I concluded in the calling rule base. Any The System Checkout program presents
Feature Advanced number of rule base calls can be made from menus to the user to determine the testing
diskette diskette any rule base, and a called rule base in turn environment. From the user's responses, the
rule base rule base
may call another rule base. diagnostic shell sets three global values
which are passed to the master rule base.
Figure 3 Organization of Diagnostic Rule Bases

38
The first of these values indicates whether the execution of tests was simplified when the large and complex knowledge base. The
system is being run in system checkout mode resolution of the failure was kept separate. ability to call an unrestricted, dynamic list of
by the operator, or in advanced mode by a external procedures makes the capabilities of
service representative. If a problem is not Resolution rules determine which parts are this system almost unlimited.
detected by the operator in system checkout likely to be faulty by analyzing the results of
mode, the system can be tested in advanced the test units. Typically, a single goal Acknowledgments
mode. Tests are longer, and there is more indicates a failing Field Replaceable Unit We wish to thank the entire diagnostic
interaction with the user in advanced mode. In (FRU). References to procedures in resolution development team for their creativity and
addition, advanced testing will often result in rules do not cause the procedures to be persistence. This paper would not have been
a more precise list of possible failing parts. executed, but allow conclusions to be made written had it not been for the dedicated
because of tests that have previously been technical leadership of Richard Flagg; the
A second global value is used to indicate run. efforts of Chris Iwaskiw and Roberta Starbird
which device is selected for testing or on the Inference Engine; Mike McBride, Luke
whether the entire system should be checked Separating the rule base into two types of Browning, and Scott Porter on the Diagnostic
out. If the user has an indication of where a rules in this manner reduced the depth of the Control Program; and Doug Benignus, Chuck
problem lies, they may test only the device rule trees and made the rules easier to Cruse, and AI Laurence on the knowledge
that is suspected. develop, understand, and maintain. base. We are also grateful to our managers
Jay Ashford and Niel Wiegand for their
A third global value is used to indicate that an Conclusion willingness to try something new and for their
intermittent problem is occurring, so tests Expert systems have gained wide popularity untiring support.
may be run in loop mode until the problem is to a large extent because the reasoning
found or the user wishes to quit testing. If a mechanism of the expert system is separate References
from the knowledge on which the inferences 1. M.T. Harandi, "The Architecture of an Expert System
machine is not tested in loop mode, then the
Environment," Proceedings of the Fifth International
rule base is completely traced one time. are drawn. In this way, the inference logic
Workshop on Expert Systems, Avignon, France, May
becomes a general-purpose tool for use on 1985.
Goal text in the diagnostic system is in the other problems, requiring only a new set of 2. M.T. Harandi, "A Tree Based Knowledge
form of a service request number (SRN). This codified knowledge. The use of an expert Representation Scheme for Diagnostic Expert
SRN is a number that the customer can system has allowed the creation of a Systems." Proceedings of the 1984 Conference on
report to a service organization or use diagnostic system that diagnoses a complex Intelligent Systems and Machines, Rochester, MN,
machine with a varying and complex 1984.
themselves to replace the faulty part. When a
configuration. This system works equally well 3. F.D. Highland, "Design of an Expert System for
hardware part is identified as bad by the
Shuttle Ground Control," Master's Thesis, School of
expert system, its number is returned to the for a naive operator or an experienced
Sciences and Technologies, University of Houston,
diagnostic shell which displays up to four service representative. Clear Lake City, TX, 1985.
items in descending order of their confidence 4. P. Nielsen, "A User's Manual for Construct and
values. One of the problems which has kept inference Consult in the GPSI Environment," Department of
tools from being truly portable, both from Computer Science, University of Illinois at Urbana-
Rule Segment Design problem to problem and from machine to Champaign, 1984.
Rule segments are designed by creating rules machine, has been the dependence of the
of two types: control rules and resolution expert system program on the idiosyncrasies
rules. The control rules decide which tests are of the underlying operating system and the
to be executed. Execution of the hardware requirement of vast memory resources in
tests are order dependent and influenced by current expert system technology. The use of
such things as the diagnostic mode or loop segmented rule bases allows the diagnostic
mode values. The logic for control of system to run in limited memory and have a

39
Manufacturing Innovations to Increase Quality and Reduce Cost

Charles W. Bartlett, A.V. Burghart, George M. Yanker

The IBM RT PC 6150 and 6151 are carton identifies the vendor providing the part, The sizing and exception handling station links
manufactured by a continuous flow process. the part number, and the engineering change the bar code label on the tote with the carton
The demand for finished units, instead of the level of the part. Cartons of a part are of parts and verifies that the bar code label
quantities of available raw parts, paces the arranged on a standard 40 by 48 inch pallet. on the carton accurately describes the
assembly line. Supply and demand determine Each pallet has a bar code label. contents of the carton. It does this by
the need for finished units and control the weighing the carton and measuring the height
manufacturing flow according to this When parts arrive by truck, each pallet filled of the carton. If either the weight or height
fluctuating need. This process minimizes with cartons is brought to a pal/et sizing does not match the part indicated by the
inventories of raw parts and of finished station. This station measures the filled pallet carton bar code label, the tote is sent to an
products and, thus, reduces manufacturing to verify the pallet will fit in the flow racks, operator for correction. After correcting the
cost. scans and records the pallet's bar code label, problem, the operator can return the tote to
and places the pallet on a metal skid to await the sizing and exception handling station.
The automation of the process further storage in the flow racks.
reduces cost, decreases production time, and Totes that pass the sizing tests move to the
increases product quality. Automated An operator using a semiautomatic fork truck stackers for storage. When parts are needed
manufacturing methods give consistency and moves the filled pallet from the metal skid to in the assembly line, a conveyer system
precision to material handling, product the appropriate flow rack. All flow racks use a moves a tote from the stackers to the
assembly, quality control, and data first-in, first-out system. When parts are assembly line.
management. required in the assembly line, an operator
using a semiautomatic fork truck moves a When a tote is emptied of aU parts, the
Material Handling filled pallet from the flow racks to the conveyer system moves the tote to the empty
Automated material handling minimizes the depalletizing station. An operator debands the tote verification station. This station scans the
people and the time involved in storing parts, pallet and removes the over-pack from the tote bar code label and weighs the tote. If the
in delivering parts to the assembly line, and in pallet. tote is empty, the tote returns to the
moving the RT PC system units between depalletizer. If the tote contains a reusable
assembly, quality control, and packaging The depal/etizing robot scans the pallet bar card carton, the carton is removed and
stations. All objects that the material handling code to determine the size and arrangement directed to an in-house return conveyor and
system conveys are packaged and labelled of cartons on the pallet. The robot then the tote returns to the depalletizer. Otherwise,
for automation. removes the top from each carton, places the tote moves to the sizing and exception
each carton in an empty plastic tote, and handling station for operator disposition.
Vendors must package and label parts places each carton top on a trash belt. The
according to specifications. Each carton empty pallets are returned to the flow racks Each RT PC system unit remains in a plastic
contains only one type of part and one layer and the plastic totes containing the cartons of tote while it is assembled, checked for quality,
of parts. All parts are arranged for robots to parts are moved to the sizing and exception and transported to the packaging station.
pick up. A bar code label located on each handling station. Each tote has a bar code label and is

40
Figure 1 The Manufacturing Area

transported through the manufacturing processes make certain demands on product assembly "bottom". Each part fits into or
process by a system of conveyors. design, manufacturing engineers and onto a previously inserted part, and where
development engineers worked together needed, adequate space is available for a
Product Assembly throughout the design process. robotic gripper. Parts snap together and are
Automation increases the efficiency of the "trapped" by other parts. (Screws are used
assembly process by reducing assembly time The engineers designed the RT PC system only where needed for grounding.) Special
and cost and increasing assembly accuracy. units to be assembled in layers using a features enable parts to funnel into place,
Because many automated assembly "bottom up" method, a side being the increasing alignment precision. Parts that

41
require an area that a robot can reliably grip Pwr supply (120V)

are designed with such an area.

Manufacturing systems monitor each robotic

manipulation. Some systems use vision
techniques to determine the placement of
parts. Other systems analyze strain gauges in
the robotic gripper to compare the actual
force required to insert a part with the
expected force. Such monitoring prevents
damage, increases assembly precision, and
thus improves product quality.

Quality Control
All RT PC system units undergo a general
quality control test, and some RT PC system
units undergo special stress tests and
communications interference tests. The
internal self-test features of the RT PC
system units, the software resident in the test
controllers, and the software designed to
perform unattended testing enable the quality Screw
control testing to be automated.

The general quality control test involves a

power-on test, an operation test, and a
verification test. A unit that fails a test moves
to a repair operator. The unit is powered-on
(the power-on test) and directed to perform
repeated self tests (the operation test). The
unit runs without a keyboard or a display and
records test data on a resident diskette. A
Bridge
test controller checks the test data and
repeats the operation test (the verification ~ Processor card asm
Floating point card asm
test).

Several types of stress tests further monitor

Figure 2 An IBM RT PC System Unit
quality. Short term and long term reliability
tests assess the ability of the product to
Data Management without affecting total network performance.
perform satisfactorily in the customer
The RT PC manufacturing process uses a The computer systems in the data
environment. These reliability tests are
distributed computer control architecture to management network perform at three
performed at an elevated temperature using
integrate computer systems and to simplify functional levels. The highest level contains
typical customer software. The elevated
error recovery. This allows one system in the the main system, the middle level contains the
temperature accelerates hardware failures.
data management network to malfunction area systems, and the lowest level contains

42
the station systems. Figure 3 shows the Tier 1
Manufacturing
Transfer build information area control
functional arrangement of the systems that Track status system
control the manufacturing process.
1
The manufacturing area control system, which
serves as the main system, controls the entire -- ------ ------ ------ ------ ---
Tier 2 It ~ If ~
manufacturing process. This system
Distribution Assembly Test Laser engraver Packaging
communicates with the area systems. The area control module control area control control area control
following manufacturing areas are controlled system system system system system
by area systems: material handling, product
assembly, quality control, label engraving, and
L
product packaging. Each area system
controls the transfer of information and tracks - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - --
the status of parts, products, and station Tier 3

systems within its area. Each station system + 1 ~ It ~

controls a specific manufacturing task. Physical

process
flow
Flow
racks
~ De-palletizer .... Stackers ~ Assembly ~ Test ~ Engraver ~ Packaging

The distribution area control system controls

the distribution of materials supplied to the
manufacturing process. This system manages
t
Parts
t
Finished
product
parts inventory, tracks parts and totes, and
provides data to the manufacturing area Figure 3 The Data Management Systems Hierarchy
control system. The distribution area control
system communicates with the following assembly area. The assembly conveyer accuracy and quality of the engraving, and
station systems: stacker interface, stacker control system also sends information about sends the results to the manufacturing area
control, flow rack control, outer loop interface, each system unit being assembled to the control system. Units leaving the engraving
outer loop control, depalletizer control, and manufacturing area control system. area are ready to be packaged and shipped.
exception handling control. Thus, the
distribution area control system oversees all As assembled units enter the quality control The packaging area control system directs the
workflow dealing with pallet storage, area, the manufacturing area control system packaging process and notifies the
depalletizing, sizing, and tote storage. sends product profiles to the test area control manufacturing area control system of boxes
system. The test area control system tracks being released to outside distributors. The
The assembly module control system and the each product through the test cycles by packaging area contains the following station
assembly conveyer control system work communicating with the following test station systems: modicon monitor station, packing
together to direct the assembly process. As systems: rework control, run-in control, test station #1, packing station #2, and palletizing
the manufacturing area control system sends conveyer control, screen test, and verify test. station.
build requests to the assembly module control Upon the successful completion of the quality
system, the assembly module control system tests, the test area control system conveys
checks the status of each assembly station the results to the manufacturing area control
and sends instructions to the assembly system and routes the units to the laser
stations. The assembly conveyer control serializing area.
system directs the parts totes, the RT PC
system unit totes, and the empty totes The laser engraver control system directs the
through the system of conveyers in the engraving of serial numbers, verifies the

43
ROMP/MMU Technology Introduction

D.E. Waldecker and P.Y. Woon

The ROMP/PL.8 project was initiated by the by compiler requirements as opposed to compiler compatibility required that this
IBM Office Products Division (OPD) in mid- performance on bench marks or optimization change be made to both machines.
1977 in Austin. OPD architects were for a particular software kernel.
motivated to develop a high-performance ROMP /801 Differences
microprocessor which could be efficiently The ROMP definition was influenced by many Although the 801 and ROMP have a common
programmed using a high-level language. The factors. Maintaining a strong relationship with heritage, some important differences exist
"801 Project" at IBM Research in Yorktown the 801 activities in Research was important between the two. The 801 assumed the use
Heights, New York had many of the same in order to take advantage of compiler of two cache memories, one for instructions
goals. (This project is described by George advances which continued throughout the and one for data. A requirement for caches
Radin in [1] and [2].) It was decided to take development phase. Cost was a key was not incorporated into the ROMP design
the 801 architecture and modify it as consideration and influenced both architecture for cost and complexity reasons. Since the
appropriate for OPD objectives. This and technology selection. Storage economy ROMP can execute an instruction almost
cooperative effort became known as the was a main factor that led to differences every processor cycle, an efficient memory
Research - OPO - MicroProcessor and was between the ROMP and the 801 instruction interface capable of high bandwidth was a
given the acronym ROMP. sets. A technology goal was to fit the requirement. Two key features of the ROMP
processor (ROMP) and the Memory design which greatly reduce memory
ROMP/801 Objectives Management Unit (MMU) on a single chip bandwidth limitations are: the Instruction
Objectives of both the 801 and ROMP each. Another goal was to fully exercise the Prefetch Buffer and the use of 16-bit, in
projects were to provide high performance, Burlington Silicon Gate Process (SGP) addition to 32-bit, instructions. The ROMP
Reduced Instruction Set Computer (RiSe) technology while maintaining chip sizes that contains a 16-byte instruction pretetcn buffer
architectures which were especially well- would produce reasonable manufacturing which practically guarantees that all
suited as the target for an advanced, yields. sequentially accessed instructions are
optimizing compiler (the PL.8 compiler). The available for execution when they are needed.
RISC architectures are characterized by use An initial TTL model of the ROMP was
of general-purpose registers, use of only operational in Austin at the end of 1978. The 801 migrated to all 32-bit instructions
Load and Store instructions for referencing Differences between this first ROMP and the while the ROMP maintained both 16- and 32-
memory, and execution of most instructions in current chip were driven by technology and, bit instructions. The judicious use of 16-bit
a single processor cycle. The PL.8 compiler to a greater extent, by changes in the instructions decreases memory code space
was under development at IBM Research in Research 801 definition. The original and allows more code per real-page frame in
Yorktown Heights in conjunction with the 801 machines performed 24-bit arithmetic and had a virtual memory system, resulting in fewer
project. The goal of the PL.8 compiler was to both 16- and 32-bit instructions. The 801 page faults and improved system
produce code which is almost as efficient as evolved to 32-bit arithmetic and addressing performance. More importantly, the shorter
code developed in assembly language. and the ROMP followed this lead, primarily average instruction length of the ROMP
Attention was given to ensure that both the because the need for a 32-bit address was decreases the memory bandwidth required for
801 and ROMP machines were good compiler recognized and maintaining the desired PL.8 instruction fetches. For example, an
targets. Instruction set definition was driven instruction mix containing 30% Load and

44
Store instructions (which require 32 bits of 16 general-purpose registers (Le., System! another "backend" for the ROMP. This
memory reference each for data) would 370). The ROMP does an excellent job of involved a complex working relationship
require 41.6 bits of memory bandwidth per emulating other machines which have a more between Research and Austin. This excellent
instruction if all instructions are 32 bits long. limited register set. The 801 is significantly relationship has continued over the years with
The same instruction mix executed in the better at 370 emulation. Aside from emulation, enhancements and modifications being made
ROMP, where the average instruction length the use of all 32-bit instructions is estimated by both groups. The compiler is currently
(weighted average of 16- and 32-bit to make the 801 MIP rate about 15% to 20% owned by Austin with enhancements being
instructions) is about 20 bits (2.5 bytes), only more powerful than the ROMP MIP rate. That made by both groups.
requires an average of 29.6 bits for each is, software path lengths for 801 programs
instruction. This is a reduction in memory are about 15% to 20% shorter than they are The PL.8 compiler currently supports three
bandwidth requirement of almost 30% per for equivalent ROMP programs. source languages, Pascal, C, and PL.8, a PL!I
instruction for the ROMP over a design which variant designed to be suitable for generation
contains only 32-bit instructions. Since The use of both 16- and 32-bit instructions of efficient object code for systems
memory bandwidth is usually the adds some design complexity. Instruction programming. Object code is produced for the
performance-limiting factor, a 30% reduction handling and decoding must account for 801, ROMP, System!370, and MC68000.
in the bandwidth requirement will certainly instruction location on both 16- and 32-bit
improve performance in a non-cache system. boundaries. The 16-byte Instruction Buffer The ROMP PL.8 compiler development
and its management also adds complexity. influenced the deSign of the ROMP
It must be recognized that a machine with all However, studies have shown that the 16- instructions in a number of significant ways.
32-bit instructions should do more "work" for byte Instruction Buffer provides about the The goal of program storage (byte) efficiency
each instruction executed than a machine same performance advantage as a 256-byte caused the following modifications to be
with some instructions that can only be instruction cache, with a significant savings in made:
executed in a 16-bit format. That is, an the silicon required for implementation.
equivalent MIP (Million Instructions Processed 1. Short (16 bits) forms of several
per second) rate for a machine with only 32- The design point chosen for the ROMP is well instructions were introduced to provide
bit instructions should represent more suited for a microprocessor VLSI design. for the special case of an immediate
processing capability than the same MIP rate Good performance is achieved with readily operand with value less than 16. For
for a machine with both 16- and 32-bit available memories and the silicon area example, Add Immediate, Subtract
instructions. One of the limitations of 16-bit requirements are a good fit for our SGP Immediate, Compare Immediate, and Load
instructions is the limited number of bits technology. The ROMP's dual 16- and 32-bit Immediate were provided.
available to specify operation codes, instruction format provides about a 10% net
registers, displacements, etc. This limitation is performance advantage over an equivalent 2. A short-form relative jump instruction was
one of the reasons that the 801 uses 32-bit 801 microprocessor in non-cache systems. added with maximum displacement of
instructions exclusively. Use of only 32-bit plus or minus 256 bytes.
instructions permits the register specification Compiler Development for ROMP & 801
fields to contain the 5 bits required to select The PL.8 compiler was initially developed for 3. The long (32-bit) Branch instructions were
one of 32 general-purpose registers (GPRs). the 801 project in Research as part of the defined to be relative rather than absolute
The limit of 16 registers for the ROMP results exploration of the interaction of computer in order to reduce the storage necessary
in only a modest increase in Load and Ston-: architecture, system deSign, programming for relocation information from modules.
frequency, since the PL.8 compiler perform', language, and compiler techniques. The
an efficient register optimization. A primary adaptation of this compiler to the ROMP 4. A Load Character instruction was added
motivation for having 32 registers is efficient architecture was done in Austin. A single in order to handle character data with
emulation of other architectures which have compiler was maintained with the addition of fewer bytes.

45
 In addition, Load Multiple and Store register-to-register (RR) operations in the Silicon Technology
Multiple instructions were provided to instruction stream so that processing of the As stated earlier, the initial ROMP TTL
improve the speed of subroutine linkage. RR operation can overlap the memory Prototype was operational in Austin at the
reference. The compiler also makes effective end of '7B. The success of this Prototype in
The resultant ROMP architecture proved to use of the Branch with Execute instruction. demonstrating the B01 concepts applied to
require about 30% fewer bytes than B01 for a This instruction allows execution of an the ROMP, motivated us to proceed with a
selected set of bench marks. instruction following the Branch while the ROMP VLSI design. In early '79, the IBM
branch target instruction is being fetched. General Technology Division in Burlington,
In addition, the ROMP instruction set design This overlap of instruction execution with the Vermont was interested in applying their SGP
includes only instructions which can be used fetching of the new instruction stream results (Silicon Gate Process) technology to a logic
effectively by the compiler. The ROMP does in better CPU utilization. part (as opposed to a memory part). One of
not contain complex instructions and their objectives for such a project was that
addressing modes which a compiler finds In addition the PL.B compiler uses LALR the logic part selected should be complex
difficult to generate. The ROMP does not parser generator [5] techniques. Syntax- enough to stress the technology ground rules.
have complex loop closing instructions which directed translation enables the compiler to The ROMP appeared to fit the requirements
require several free registers in order to associate the intermediate code generation for a "technology-proving" development. It
operate. It does not contain instructions like directly with the syntactic structure of the contains a custom register file, ROM, custom
repeat, rotate, and edit-instructions which source language. Furthermore, it uses a map- logic in data registers, multiplexers, and the
are not primitives for PL.B constructs. coloring algorithm from topology for register ALU, Off-Chip Drivers and Receivers, plus
Register allocation is simplified by the allocation [6]. Most programs of reasonable random logic designed with a master image
requirement that variables be loaded into size color in 16 GPR without spilling. 32 GPR approach.
registers before being operated upon. would reduce spilling on larger programs but
would require 5 bits for register specification The division of design tasks between Austin
The PL.B compiler employs state-of-the-art which would require 32-bit instructions. The and Burlington was a rather complex
compiler technology [3] utilizing several trade-off was made in favor of the use of 16- arrangement. Austin was responsible for the
independent advances in the theory of bit instructions (with the 25% to 30% Functional Specification and logic design.
compiler design. John Cocke and Fran Allen performance advantage) at the performance Burlington was responsible for the final chip
[4] published a procedure of data flow detriment of large programs, layout but many macros and iarge portions of
analysis-a technique fOi analyzing the the chip were deSigned in Austin. Austin
interval of execution over which a variable is The compiler incorporates the primary performed the logic simulation and also built a
used, and using that information for theoretical advances in compiler design nodal model of the ROMP chip to verify
optimization and assignment of variables to achieved over the past decade. The proof of functionality. Burlington designed the memory
registers. The technique allows efficient use the theory lies in its effectiveness. The for this model and also wrote many of the
of registers and enhances the reliability of approach of developing the language and the Architectural Verifications Programs (AVPs)
generated code. instruction set as a joint effort has paid off in used to test the model, drive the logiC
language efficiency and in ease of code Simulation, and ultimately test the chip
The compiler's scheduling algorithms make generation. Benchmarks have shown that the functionally. Manufacturing test patterns were
use of the data flow analysis results to compiler generates code that approaches the generated in Austin but special test patterns
produce a program which takes advantage of performance and storage requirements of to resolve unique problems early in the
the pipelined implementation of the ROMP. assembly code produced by a good hand program were generated in Burlington.
Since only Load and Store operations coder. These results are a testimony to the
reference memory, the compiler can very success of the design approach and the Early ROMP parts did indeed stress the
effectively intersperse memory references and compiler technology used. technology. We were required to change the

46
design several times as technology ground architecture. Some of the more prominent 3. Marc Auslander and Martin Hopkins, "An Overview of
rules evolved. Changes were made to features are use of inverted page tables to the PL.8 Compiler," in ACM, 0-89791-074-5/82/006/
0022.
improve yields and chip reliability well after minimize memory page table space, special
4. F.E. Allen and J.A. Cocke, "A Program Data Flow
we had achieved functional parts. As we segments to provide protection with 128-byte
Analysis Procedure," in CACM, 19,3 (March 1976).
progressed, the chip was also made smaller. resolution, and ability to accomodate variable
5. W.R. La Londe, "An Efficient LALR Parser
The initial pass was 8.35 mm square and the speed memories. Generator," University of Toronto, Technical Report
final version is 7.65 mm square. CSRG-2 (April 1971).
Favorable experience with ROMP logic 6. Gregory J. Chaitin, Marc A. Auslander, Ashok K.
Projected performance of the ROMP chip was simulation convinced us that there was no Chandra, John Cocke, Martin E. Hopkins, and Peter
significantly improved over time. Initial need to build a TTL nodal model of the MMU W. Markstein, "Register Allocation via Coloring,"
projections were for a cycle in the 250 - 300- chip. However, in order to support early Computer Languages, 6, No.1, pp. 47-57, 1981.
nanosecond range. As we gained more data RT PC prototypes, a three-card TTL
and modified the design to eliminate critical equivalent of the MMU function was
paths, the projections were reduced to the developed. The early prototypes were
200 - 250-nanosecond range. We also completed in early '83. When MMU chips
projected that 50% of the functional parts were received in late '83, the three-card TTL
could be selected to execute at a 170- version was replaced by less than one-half
nanosecond cycle. The design which is in card containing the VLSI MMU.
manufacture has virtually no fall-out of
functional parts due to selection for 170- Summary
nanosecond operation. The typical ROMP will The ROMP project is an excellent example of
run at about a 135-nanosecond cycle. System several IBM divisions at different sites
considerations of memory and i/O interfacing, working together to produce a successful
system clock skews, voltage variations, and program. The project ultimately resulted in the
tester tolerances limit our CPU cycle from RT PC product design by the Engineering
being faster than 170 nanoseconds. Systems Products group in Austin. It
embodied the 801 RISC / PL.8 compiler
MMU Memory Management concepts developed in IBM Research and
The MMU is a 9 mm square SGP chip which served as an important vehicle to mature the
performs the RT PC system memory Silicon Gate Process (SGP) technology of the
management function. IBM General Technology Division.

The MMU chip used the same technology and The close relationship of the PL.8 compiler
design approach as ROMP. Since the ROMP development and the hardware design is a
had served as the vehicle to solidify the rare occurrence and, we believe, was one of
technology and design methods, the MMU the key elements in achieving an excellent
design was more straightforward in many and balanced design.
respects. However, the MMU functional
requirements resulted in a larger chip than References
the ROMP. The MMU definition was initiated 1. George Radin, "The 801 Minicomputer," in ACM,
in late '81. The basis for the functional 0-89791-066-4 82/03/0039
definition was System/38 and work done at 2. George Radin, "The 801 Minicomputer," IBM Journal
of Research & Development, 27, pp. 237-246, May
Research on memory management
1983.
approaches consistent with the 801

47
The IBM RT PC ROMP and Memory Management Unit Architecture

P.O. Hester, Richard O. Simpson, Albert Chang

Introduction The ROMP and MMU have segment techniques include asynchronous
This paper describes the ROMP registers, but they are used for different prefetching and partial decoding of
microprocessor and companion Memory purposes than in typical 16-bit computers. instructions, a packet-switched channel
Management Unit (MMU) used in the IBM Each segment can span 256 megabytes; between the ROMP and the MMU,
RT PC. The ROMP and MMU grew out of the segment registers are used to provide execution of instructions beyond a "load"
IBM's requirements in the late 1970s for a addressability to a number of different until the loaded data is actually needed, and
modern microprocessor for use in office objects rather than to extend addressability delayed branches which overlap the
equipment and small computers. Several beyond the first 64K bytes of an object. execution of another instruction with the
major goals were identified at the start of the fetching of the branch target.
project. • Two Chips. For cost reasons the number of
VLSI chips in a small system must be • Virtual Memory. This requirement was
• High-Level Language Programming. With minimized. Existing technology did not allow identified later than the others, after it was
software costs rising, it was decided that functions as complex as the ROMP and realized that the ROMP had the potential of
almost all programming for the new MMU to be combined into a single chip, so being used in much more elaborate
processor should be done in a high-level one chip was used for the processor and systems than just office machines. The
40
language because of its greater efficiency one for the Memory Management Unit. The virtual addressing mechanism provides 2
of programming. This meant that a good split is about even; the two chips are of bytes of virtual addressability and supports
compiler was needed in conjunction with comparable complexity (the MMU is real memory sizes of up to 16 megabytes.
the processor. lr: fact, an excellent co~p!!er somevvhat !arger than the ROMP) It uses concepts from the System/38 r21,
was needed-one that would produce the and additionally provides a means of
tightest possible object code, to reduce the • High Perfor~ance with Inexpensive controlling access to sections of virtual
size of ROM and RAM storage required for Memory. The 801 minicomputer [1], a memory smaller than a page for assistance
office machines. Reduced Instruction Set Computer (RISC) in database locking schemes.
then under development at the IBM Thomas
• Addressability. Sixteen-bit computers are J. Watson Research Center in Yorktown The PL.8 compiler [3], which was developed
limited to addressing 64K bytes or words Heights, New York, had exceptionally high at IBM Research in conjunction with the 801
unless some additional hardware, such as performance. However, much of its architecture, offered the potential of
segment registers, is introduced in the performance depends on its two caches, generating extremely efficient code for a
addressing path. The difficulty of handling which can deliver an instruction word and a machine which matched its paradigm of a
objects larger than 64K even with segment data word on each CPU cycle. Since such computer. Thus, the ROMP programming
registers led to the decision to make the caches were prohibitively costly for small model and instruction set are derived from
ROMP an all 32-bit machine, with 32-bit systems, pipelining techniques normally the 801 processor for which the PL.8
registers, 32-bit addresses, and 32-bit data found in larger machines were adapted to compiler was originally designed, but the
quantities. the ROMP so that useful work could be ROMP is designed for greater byte efficiency
done during the (comparatively) long time (the programs are smaller) than the 801. That
needed for memory operations. The the ROMP instruction set is a good target for

48
a compiler is demonstrated by the fact that • Provide an architected address and data During the architecture definition, it became
the PL.8 compiler generates code that is width of 32 bits clear that systems using processors of this
within about 10% of the size of good hand class must provide virtual memory. In order to
code. • Provide an efficient target for an optimizing support virtual memory, precise interrupts
compiler were defined for the ROMP so that the cause
Together, the ROMP and MMU implement a of a page fault can be identified easily. All
system with the following major • Support virtual memory instructions are restartable; an instruction
characteristics: causing a page fault can simply be re-
• Provide system integrity through separate executed after the fault is resolved. This sort
• A large uniformly-addressed virtual memory user and supervisor states of virtual memory support is common on
(2 40 bytes) mainframes and some minicomputers, but
• Provide improved error detection and had not appeared in a microprocessor prior
• A large number of general-purpose reporting facilities to the design of the ROMP.
registers (16)
• Provide high performance with low-cost The need to provide protection of user
• A simple, uniform instruction set with most memory. programs and isolation of control program
instructions executing in a single cycle. functions resulted in the definition of separate
The first requirement dictated an architecture user and supervisor states. Only instructions
As with other RISC designs [4, 5], the ROMP providing both 32-bit address and data which cannot be used to affect system
instruction set performs all operations on data quantities. As a result, it was decided that all integrity are valid in user state. Instructions
within general registers; the only memory registers and computations would support 32- associated with control program functions are
operations provided are Load and Store. The bit quantities. However, the architecture valid in supervisor state only.
compiler "pipelines" the Load operations by provides for specific support of 8-bit and 16-
separating them from the use of the loaded bit quantities in addition to 32-bit quantities. In order to guarantee data integrity, certain
data as far as possible. requirements and facilities are provided for
The ROMP processor architecture was error detection and reporting, including:
Although most ROMP instructions execute in defined with the assumption that most
only one cycle, additional cycles are taken software would be developed in a high-level • Parity checking on all external buses
when it is necessary to wait for data to be language. At this same time, an optimizing
returned from memory for Loads and compiler was being developed at IBM • Bus timeout detection
Branches. As a result, the ROMP takes about Research which supported a variant of the
three cycles on the average for each PL/I programming language. A joint study was • Non-maskable hardware error detection
instruction. At the cycle time of 170 conducted to evaluate this compiler and the interrupts.
nanoseconds used in the RT PC, the ROMP architectural requirements to take advantage
runs at about 2 MIPs. of the compiler optimization techniques. This Good system performance with low-cost
study indicated the need for a large number memory was an early requirement. Although
Details of the ROMP and MMU architecture (16 or 32) of 32-bit general-purpose registers, cache memories were considered, they were
are described in the following sections. and an instruction set closely matched to the quickly discarded due to their cost and
compiler intermediate language. Specifics of complexity. A compromise was made
ROMP Processor the resulting instruction set are provided later between cost and performance that resulted
The RT PC ROMP processor was designed in this paper. in the decoupling of memory operations from
to: CPU operations, and in the definition of an

49
innovative high bandwidth packet switching o 31 Instruction Set
storage channel that supports multiple o The ROMP is generally a two-address
outstanding operations. The MMU was 1
architecture, with both 2- and 4-byte
designed to allow overlap of the address 2
instructions of seven formats as shown in
translation process with memory access. The 3
Figure 2. The various formats provide an
MMU also supports two-way interleaved 4
opcode field, register fields (RA, RB, and RC)
memory which provides a throughput of one 5
and an immediate field (I, JI, BI, and SA). RA,
memory operation every CPU cycle. 6
RB, and RC are each 4-bit fields which
7
specify one of the 16 GPRs.
Programming Model 8
The ROMP provides 16 32-bit General 9
Although most ROMP instructions are two-
Purpose Registers (GPRs) that can be used 10 address, the X format provides three register
for either address or data quantities. There 11
addresses. In all other formats, the RB and
are no restrictions on which registers can be 12
RC fields specify the source registers, with
used for addresses or data. Figure 1 shows 13
RB also specifying the destination register. A
the 16 GPRs. 14
single instruction called Compute Address
15
Short (CAS) is implemented in the X format,
Note that the 16 GPRs are also grouped in where the contents of registers RS and RC
o 8 16 24 31
eight pairs. These pairs (0-1, 2-3, etc.) are Register Word are added together and the sum placed in
used with the paired shift instructions to
provide nondestructive shift capability. Details
Upper-half I Lower-half Half-word

of the paired shifts are provided in the

CO I C1 I C2 I C3 Char/Byte
0 4 8 12 16 31

instruction set section of this paper.

Figure 1 General-Purpose Registers
I I OP RA RB RC X format

A 32-bit register quantity can be treated as

either a full 32-bit quantity, two 16-bit • The Machine Check Status (MCS) and I I OP I RB RC D short format

Program Check Status (PCS) which are

quantities. or four 8-bit quantities. Instructions
are provided to manipulate data in any of used to report hardware errors and OP RB RC D format

these forms. software errors and exceptions respectively

OP RB RC R format
In addition to the 16 32-bit GPRs, a separate • The Interrupt Request Buffer (IRB) used for
posting interrupts
set of System Control Registers (SCRs) is
provided. The SCRs include the following: OP Ici N J JI format
• The 32-bit Instruction Address Register
(lAR)
• Three registers associated with a 32-bit
system timer facility
OP RB I BI BI format

The Interrupt Control Status (ICS) register

used for controlling interrupts and interrupt OP BA BA format
• The Multiplier Quotient (MQ) register used
levels, address translation, memory protect,
with the multiply and divide step
instructions and other miscellaneous control functions
OP-CODE RB • RC •

• The Condition Status (CS) which contains

the condition code bits. Figure 2 Instruction Formats

50
register RA. Extensive studies indicated the 4-bit immediate field provided by the 2-byte Load and Store Multiple instructions are also
need for a three-address add instruction for format. Several evaluations were made included in this class that permit loading or
address computations so that both source trading off the byte efficiency of the 2-byte storing of from one to 16 of the GPRs to
register quantities could be preserved. instructions versus their limited displacement memory. A test and set instruction is also
capability. The final instruction set definition provided for multiprocessor synchronization.
The various instruction formats were defined included 79 2-byte instructions and 39 4-byte
so that the opcode and two register fields instructions. Ongoing analysis of compiler- All Memory Access instructions compute the
(RB and RC) are always in the same bit generated code indicates an average effective memory address as the sum of a
positions within each instruction format. This instruction length of 2.4 to 2.7 bytes, GPR contents plus an immediate field
allows these fields to be used as defaults to indicating good use of the 2-byte formats. specified in the instruction (base +
unconditionally control fetching of instruction displacement addressing). Two-byte memory
microcode and register operands without In certain formats (X, D Short, and JI) a 4-bit access instructions provide a 4-bit immediate
instruction pre-decoding. This is necessary to opcode is used. Opcodes were chosen so field, with 4-byte instructions providing a
support a goal of single-cycle execution of that these particular formats could be easily 16-bit immediate field.
each instruction. Note that in certain formats determined with a minimum of pre-decoding.
(JI, BI, BA for example) one or both register The Memory Access instructions operate only
fields are not used. However, these fields are The ROMP provides a total of 118 between memory and one or more GPRs. No
still used to fetch register operands. During instructions in the following ten classes: memory-to-memory operations are provided.
the execute phase of instruction processing, a The architecture allows instruction execution
decision is made to use the immediate Number of to continue beyond a load instruction if
information rather than the register quantities. Instruction Class Instructions subsequent instructions do not use the load
Since this decision is not made until the data. This increases system performance by
execute phase, the register information can 1, Memory Access 17 overlapping memory access with subsequent
be fetched by default and later discarded with 2. Address Computation 8 instruction execution.
no undesirable results. This approach is 3. Branch and Jump 16
required to achieve the goal of single-cycle 4. Traps 3 Address Computation instructions are
instruction execution, without creating 5. Moves and Inserts 13 provided which compute memory addresses
implementation constraints. 6. Arithmetic 21 without changing the condition codes. These
7. Logical 16 instructions include a three-address add
During the definition of the ROMP instruction 8. Shift 15 instruction (Compute Address Short),
set, several studies were conducted to 9. System Control 7 Increment, Decrement, and 2- and 4-byte
determine the frequency of use of each 10. Input and Output 2 instructions which permit loading a GPR with
proposed instruction. These studies indicated Total 118 a 4-bit or 16-bit immediate value respectively.
that certain instructions (Increment, Immediate Separate Compute Address Lower and
Shift, Short Branch, Loads and Stores with The Memory Access instructions permit Compute Address Upper instructions are
small displacements, etc.) were very heavily loading and storing data between the 16 provided to load a 16-bit immediate value into
used. Some of these were defined as 2-byte GPRs and main memory. These instructions either the lower half or upper half of a GPR.
instructions in order to achieve the desired support four types of data: Two Address Computation instructions are
byte efficiency and to reduce the memory provided specifically to aid in the emulation of
bandwidth requirements of the processor to • 8-bit (character) quantities 16-bit architectures. They allow computing a
less than one word per cycle. Four-byte • 16-bit (halfword) quantities 16-bit quantity that replaces the low-order 16
versions of certain of the 2-byte instructions • 16-bit algebraic (sign extended halfword) bits of a GPR without altering the upper 16
were also defined for completeness that quantities bits.
allowed a 16-bit immediate field instead of the • 32-bit (fullword) quantities.

51
Standard Branch and Jump instructions are Extend. Also, Multiply Step and Divide Step Two instructions that load and store GPRs to
provided for decision making. Two-byte Jump instructions are provided. The Multiply Step I/O devices are included in the Input and
instructions are provided that provide a instruction produces a 2-bit result per step, Output class. These instructions are normally
relative range of plus or minus 254 bytes. and can be used to construct variable length used to access control registers in the MMU
Four-byte Branch instructions provide a range multiply operations. The Divide Step or other system elements.
of up to plus or minus 1 megabyte. A group instruction produces a single bit result per
of Branch and Link (SAL) instructions is also step, and can be used to construct variable Interrupt Facility
provided for subroutine linkage. length divide operations. The ROM P implements a priority-based
interrupt scheme supporting seven external
A delayed branch (called "Branch with The Logical class provides AND, OR, XOR, interrupt levels. In addition, two error
Execute") is provided to allow overlap of the and negation operations using two register reporting interrupt levels are also provided.
branch target fetch with execution of one quantities or one register and an immediate The program check level is used for reporting
instruction following the branch (called the value. A group of Set and Clear Bit software errors and exceptions such as page
subject instruction). Execution of the subject instructions is also included in this class that fault, protection violations, and attempted
occurs in parallel with fetching of the target allows any bit in any GPR to be set to one or execution of a reserved opcode. The machine
instruction, thereby eliminating dead cycles zero. check level is used to report hardware
that would normally occur during fetching of failures such as bus parity errors,
the target instruction. The Shift class provides Algebraic Shift Right, uncorrectable memory ECC errors, and bus
Shift Right, Shift Left, and left and right paired timeouts.
Three Trap instructions are provided for run- shifts. Shift amounts from Dto 31 bits can be
time address checking. These instructions specified as either an immediate quantity in The interrupt facility includes old and new
compare a register quantity against a limit, the instruction, or as an indirect amount using program status words (PSWs) similar to those
and cause a program check interrupt if the the value in a GPR. The concept of paired of System/37D. Each PSW pair contains the
limit is exceeded. shifts was introduced to provide non- IAR, condition status, and interrupt control
destructive shifts that shift a specified GPR a information. Hardware automatically performs
The Move and Insert class of instructions given amount, and place the result in a a PSW swap when an interrupt occurs. GPRs
support testing the value of any bit in a GPR, different register (the "twin" of the source are not automatically saved by hardware, with
and the movement of any of the four 1-byte register) without altering the source register. system software using a Store Multiple
fields in a GPR. A Move instruction is The twin of a given register is determined by instruction to save required GPRs. A Load
provided that allows moving anyone of the complementing the low-order bit of the Program Status (LPS) instruction is provided
32 bits in a GPR to a test bit in the condition register number (Le., the twin of register 4 is that automatically restores the machine state
status register, with a corresponding 5, the twin of 11 is 1D, etc.). from the old PSW once interrupt servicing is
instruction that moves the test bit value to complete.
any of the 32 bits in a GPR. A series of Move Instructions in the System Control class are
Character instructions are included that move generally privileged instructions that are valid Memory Management Unit
any of the four 1-byte fields in a GPR to only in supervisor state. Included in this class The MMU combines the functions of virtual
another 1-byte field in a GPR. are instructions that move GPRs to and from addressing support and memory control.
SCRs, set and clear SCR bits, Load Program From the system point of view, it translates
The Arithmetic class supports standard Add Status, and Wait for interrupt. Also included is virtual addresses to real addresses,
and Subtract operations in both single and a non privileged Supervisor Call instruction. implements the memory protection model,
extended precision modes. Other instructions performs "lock-bit" processing (explained
in this class include Absolute Value, Ones and below), and provides interrupts to the ROMP
Twos Complement, Compare, and Sign for exceptional conditions such as page
faults.

52
As a memory controller, the MMU is Program 32-bit Segment Long-form 40-bit
virtual addressing registers virtual addressing Real memory
responsible for the hardware-level control of
32 40
up to 16M bytes of RAM and ROM. Separate 2 bytes SID = 12 bits 2 bytes 224 bytes

controls are provided for RAM and ROM that 256M-byte 00000000 000.0000000 000000
256M-byte segment
o 256M-byte segment Up to 16M bytes
support different speed memories and allow
interleaving of RAM for improved memory
bandwidth. Internal logic is provided to OFFFFFFF 2 OOO.FFFFFFF FFFFFFL......-_ _ _ _~
support Error Correcting Code (ECC) for RAM 256M-byte 10000000 001.0000000
and parity for ROM. The MMU also provides 256M-byte segment 3 256M-byte segment

control signals for the external Reference-

and-Change Array (R/C). - :;-.
1FFFFFFF 001.FFFFFFF

20000000 E 002.0000000
The support for ECC on the RAM is new in ~I.. I;: 256M-byte segment

the microprocessor field and is a reflection of EFFFFFFF F 0-

the large memory sizes expected to be used 256M-bytes FOOOOOOO 002.FFFFFF F

with the ROMP. The lockbit mechanism 256M bytes
003.0000000
memory-mapped
provides a sub-page-Ievel protection and I/O To L..
:"'
memory-
locking mechanism and is new with the MMU. FFFFFFFF mapped FFD.FFFFFF F
I/O FFE.OOOOOO 0
Virtual Address Translation 256M-byte segment

Figure 3 shows the memory model which the

MMU implements. When the ROMP is FFE.FFFFFF F
opeiating in Real mode (Translate bit in FFF.OOOOOOO
256M-byte segment
Interrupt Control Status off), the MMU
functions simply as a hardware memory
controller. In this mode, up to 16M bytes of FFF.FFFFFF F
real memory can be addressed. When the
ROMP is in Translate mode (Translate bit in Figure 3 Storage Model
ICS on), the MMU translates each address
from the ROMP from virtual to real and then 28 bits of the .incoming address. To the The Segment Registers reside in the MMU,
uses the real address to access the memory executing program, memory appears to be 4 and can be read and written from the ROMP
arrays. Memory access from adapters on the gigabytes of virtual memory broken into 16 by supervisor-state programs, using I/O
I/O Channel is also supported by the MMU, segments of 256M bytes each. instructions. Each SR contains the following:
with a control bit for each access indicating
whether the access is real or translated. • Segment Present bit
The largest addressable entity is normally the
256M-byte segment, but system software can • ROMP Access Protect bit
Program virtual addresses generated by the
construct larger objects by (for example) • I/O Access Protect bit
ROMP are 32 bits. These are expanded in the • 12-bit Segment ID
assigning consecutively-numbered SIDs to
MMU to 40 bits by using the high-order 4 bits
adjacent SRs, creating an object whose • Special Segment bit
of the program virtual address to select one
maximum size is any multiple of 256M bytes • Key bit.
of 16 Segment Registers (SRs), and then
up to 4 gigabytes. Objects larger than 4
concatenating the 12-bit Segment Identifier
gigabytes will require special techniques.
(SID) contained within the SR to the remaining

53
Because the virtual addresses generated by Virtual In order for the MMU to respond to a virtual
address
programs are only 32 bits long, while I Hash anchor address at all, the Segment Present bit in the
Inverted page table
I table
translation is performed on 40-bit virtual appropriate SR must be set. This feature is

tl ~r­ ....
addresses, each program is restricted to Virtual address Chain used not only for protection, but to provide
~ddressing only those segments supplied to it
(I.e., SIDs loaded into SRs) by the operating .-- memory-mapped I/O by arranging for the
address range covered by one or more SRs

l'J
system. Segments can be shared between .~------:. 1;--..::1:, to be ignored by the M M U but responded to
processes by placing the same SID value into
an SR for each process (not necessarily the ! t=J!
L-DJ
by the I/O Channel Controller.

same SR). For SRs which have the Segment Present bit
set, access through the MMU is controlled by
The 40-bit virtual addresses are translated to the settings of the ROMP Access Protect and
Figure 4 Hash Anchor Table and Inverted Page I/O Access Protect bits. A segment register
real by looking them up in an Inverted Page
Table (Conceptual)
Table (IPT) as shown in Figure 4. The table is can thus be aSSigned to the ROMP
"inverted" because it contains one entry for processor, to I/O devices via the I/O channel
"miss" occurs, then the MMU automatically
e~ch real memory page rather than one per controller, to both, or to neither.
searches the IPT and reloads the least
virtual page. Thus a fixed proportion of real recently used entry for the appropriate
memory is required for the IPT regardless of For virtual accesses which are allowed by the
congruence class. This typically adds 8 to 11
the number of processes or virtual segments control bits described above, one of two
cycles to the translation time. An IPT "miss"
suPP?rte.d. To t.ranslate an address, a hashing types of memory protection is applied. Which
is a page fault.
fu~ctlon IS applied to the virtual page number one to use is determined by the Special
(high-order part of the 40-bit virtual address, Segment bit in the SR. If this bit is 0, then a
The M~U provides functions for use by
less the byte offset) to obtain an index to the key ~atching scheme adapted from System/
supervisor-state software which cause
Ha.sh Anchor T~ble (HAT). Each HAT entry selected entries in the TLB to be purged and
370 IS used. Processes are given key 0 or
POints to a chain of IPT entries with the same key 1 access to segments via the Key bit in
thus reloaded from the IPT the next time they
hash value. A linear search of the hash chain ea~h SR. Individual pages have 2-bit keys in
are needed. Such purging is required at
yields the IPT entry (and thus the real page their IPT (and thus TLB) entries. The types of
certain times to keep the TLB contents
number) which corresponds to the original 40- access allowed are definArl
__ h\l
-1 +ho
".1'-' fnlln\Alinn
IVtlV •• It.~

synchronized with changes to the IPT.

bit virtual address. If no such entry is found, table:
Purging c~n be done for an individual page,
then the virtual page is not mapped and a for an entire segment, or for the entire TLB. A
page fault interrupt is taken. task switch by itself does not require that any
of t.he TLB be purged; only the segment
The hashing technique results in chains which registers need be loaded. A "load real
are typically short-between one and two address" function is also provided for
entries. Even so, translating a virtual address supervisor-state software to allow determining
using only the HAT and IPT would require t~e real address corresponding to a given
several memory accesses for each virtual address.
translation. In order to eliminate most of the
IPT searches, the MMU maintains a cache of
Memory Protection
recently-translated addresses in a Translate Several functions performed by the MMU
Look-aside Buffer (TLB). The TLB is two-way
combine to provide memory protection for
set-associative, with 32 entries. If the required programs running with address translation on.
entry is in the TLB, then the M M U can
complete its translation in one cycle. If a TLB

54
Page Key Type of page SR Key Load Store Use of the Special Segment facilities allows
interprocess locking of items smaller than
00 Key 0 fetch-protected 0 Yes Yes pages. Interrupts caused by disallowed
1 No No accesses can be used to grant locks, to
01 Key 0 read/write 0 Yes Yes cause processes to wait, or to indicate actual
1 Yes No protection violations.

10 Public read/write 0 Yes Yes Conclusions

1 Yes Yes Together, the ROMP and MMU provide many
11 Public read-only 0 Yes No of the characteristics of a mainframe
1 Yes No computer-large virtual memory, 32-bit
addressing and data flow, high
If the Special Segment bit in the SR is 1, then performance-while requiring only a few
a finer granularity of protection is applied. chips to implement. The Reduced Instruction
Each page is considered to be made up of 16 Set Computer concept allows the hardware
"lines" of 128 bytes each (with 2K-byte architecture to be relatively simple, while the
pages) or 256 bytes each (with 4K-byte combination of ROMP and MMU hardware
pages). Access to a particular line within a and modern system software can produce a
page is controlled by the value of a "Iockbit" very powerful computer system which is small
associated with each line. Each IPT (and TLB) enough to reside on a desk top.
entry contains 16 lockbits for each page, a
"write" bit that determines how the lockbits The realm of personal computers need not be
are interpreted, and an 8-bit Transaction restricted to those applications which can fit
Identifier (TID). In addition, the MMU contains on 8- or 16-bit machines with limited
a Current TID register which is loaded by the addressability and CPU speed. Programs
operating system when a process is typically considered mainframe applications
dispatched. Access to the lines within pages can take advantage of the addressability,
of "special segments" is determined by the virtual memory, and speed of the ROMP.
following table:

Current TID Write Lockbit value

compared to Bit in for Access permitted
TID in IPT IPT selected line Load Store

Equal 1 1 Yes Yes

0 Yes No
Equal 0 1 Yes No
0 No No
Not Equal No No

55
References
1. George Radin, "The 801 Minicomputer," Proc. of
Symposium on Architectural Support for Programming
Languages and Operating Systems, Palo Alto, CA,
March 1-3, 1982. Published in ACM SIGARCH
Computer Architecture News Vol. 10, No.2, March
1982. Also published in IBM Journal of Research and
Development Vol. 27, pp. 237-246 (1983).
2. G.G. Henry, "Introduction to IBM System/38
ArChitecture," IBM System/38 Technical
Developments, IBM Corporation, Atlanta, GA, 1978.
3. M. Auslander and M.E. Hopkins, "An Overview of the
PL.8 compiler," Proc. of the SigPlan '82 Symposium
on Compiler Writing, Boston, MA, June 23-25, 1982.
4. J. Hennessy, N. Jouppi, S. Przybylski, C. Rowen, T.
Gross, F. Baskett, and J. Gill, "MIPS: A
Microprocessor Architecture", Proc. of the SigMicro
15th Annual Microprogramming Workshop, 1982.
5. D.A. Patterson, "Reduced Instruction Set
Computers", CACM 28, 1 (January 1985).

56
ROMP/MMU Implementation

D.E. Waldecker, C.G. Wright, M.S. Schmookler, T.G. Whiteside, R.D. Groves, C.P. Freeman, A. Torres

The IBM RT PC central processor and instruction operation codes, invalid real- transfer and the data transfer may be for
memory management functions are memory addresses, and time-out conditions independent operations. Independent
implemented in the ROMP and MMU chips. caused by non-response of a system element. acknowledgment is also provided for the
These VLSI parts are manufactured by the address and data cycles. A transfer may not
IBM General Technology Division in ROMP-MMU Interconnection be accepted if the recipient is "busy" or if the
Burlington, Vermont and are contained on the The ROMP and MMU chips are connected via recipient detected a parity error on the
RT PC processor card. The technology is a high-performance channel. The ability of the transfer. The acknowledgment sequence will
discussed by Dupont et al.[1]. See also ROMP RISC architecture to execute an indicate these conditions and the source will
Waldecker et al.[2] for a description of the instruction almost every CPU cycle highlights re-send the address or data in the case of
RT PC processor card. The basic challenge in the need for this channel to support high "busy" or "error." Data replies from memory
the ROMP/MMU functional design was to bandwidth. Two primary considerations for a or I/O have priority over data being sent to
organize the chips and interfaces to execute high-performance memory interface are: 1) memory or I/O. This priority is necessary to
one instruction every 170-nanosecond the ability to support a high transfer rate, and prevent potential overflow of the buffering
processor cycle, except for a few types of 2) low latency on replies to requests. available in the receiving device. The ROMP
instructions. This execution rate is maintained takes advantage of the system memory
with relatively slow memory by interleaving The ROMP Storage Channel (RSC) is a interleave capability in two areas. First, it
memory accesses (see also Rowland [3]). packet-switched, 32-bit channel designed to prefetches instructions and is capable of
ECC checking is performed on each memory match the pipelined operation of the ROMP sending out four instruction fetch requests
access without impacting the ability to processor. Its most distinctive aspect is the before requiring a reply. Because channel
execute an instruction every cycle. Functional ability to support overl,apping of memory bandwidth is inherently greater than
highlights of the ROMP and MMU chips, as accesses. Memory reads are split into two necessary for instruction execution, the
well as their interaction and the logic design distinct actions, a request and a reply, and 4-word prefetch buffer is usually at least
process used, are presented in this article. multiple outstanding requests are allowed. An partially full, providing some immunity to
address packet and a data packet can be interference from program data references
The ROMP chip fetches and executes transmitted each 170-nanosecond processor and DMA traffic.
instructions. It also manages instruction flow cycle, giving a channel bandwidth of 23.5M
for interrupts, program checks, and machine bytes per second. Secondly, for data references to memory or
checks. The MMU accepts memory requests I/O the ROMP allows two outstanding
from the ROMP or from I/O, translates Address and data transfers on the RSC are requests. Program execution is stopped only
memory addresses from virtual to real, done on a synchronous basis. The 170- if the data being referenced is required to
manages memory page faults, performs nanosecond CPU cycle is divided into two continue. Instructions following a Load are
memory access authorization checking, and transfer periods. The first half of each CPU executed in parallel with the actual memory
interfaces to the RT PC system memory cycle is dedicated to address transfers and reference unless they require the data being
cards. Both parts contain checking to the second half to data transfers. The fetched by the Load instruction. The PL.8
generate machine checks and program address cycle and the data cycle each have compiler places Load instructions in the
checks in case of parity errors, invalid independent arbitration since the address instruction stream as far ahead of the

57
instruction using the data as it possibly can.
Also, Load data is placed into the ROMP
register file through a dedicated port to
eliminate interference. Instruction
address <---->
Of course, the M M U and memory must also Storage channel
support fully overlapped operation if the
performance potential is to be achieved. In
fact, the MMU can simultaneously be
Memory address < >
processing two memory requests while the
result of a third is being transmitted to the
MMU
activity ITranslate

ROMP. The memory in the RT PC system is

implemented as two interleaved 32-bit wide IMemory access

banks, allowing overlapped operation. The RT

PC system memory card design supports
interleaved operation on a single memory
ROMP Register
card. activity operand
fetch
Management of requests and replies on the Control
word
RSC is accomplished by having a unique tag fetch
accompany each request and each reply. Instr.
Whenever the ROMP issues a memory execution
request, it sends a unique 5-bit tag with the Result
request. The MMU remembers the tag and storeback
returns it with the requested data or
instruction. The tag received with each reply Figure 1 ROMP/MMU Instruction Execution Flow
allows the ROMP to handle the received data
or instruction correctly. The same tagged the ROMP, the execution overlap of Loads 100% , ROMP performance starts to be
approach is used for requests from the and Stores is suspended when operating with degraded linearly by increased I/O activity.
ROMP to the I/O or from I/O to the MMU. virtual addresses, but overlap continues for
instruction fetches. The ROMP generally Figure 1 shows the typical operations
It can be seen that ROMP instruction requires 60% to 70% of the RSC bandwidth required to execute a single ROMP
execution is relatively "decoupled" from to support its inherent performance. The instruction. The sequence begins with the
memory requests. Instructions are prefetched remainder of the RSC/Memory bandwidth is fetching of an instruction from memory. The
and the ROMP usually has about two available for I/O DMA traffic. Even though request is sent from the ROMP and accepted
instructions in its prefetch buffer. Instruction DMA traffic may interfere with ROMP memory by the MMU one-half cycle later. The MMU
execution is not suspended on Stores. That requests, the decoupled nature of the ROMP translates the address, uses the result to
is, after the ROMP sends the address and and memory can permit such interference address memory, checks the returning data
data to the MMU, it is free to continue without performance degradation in many for ECC errors, and latches the result. The 2-
executing instructions. If the compiler is cases. That is, in many cases it does not cycle memory access time includes address
successful in plaCing Loads "upstream" in matter if a ROMP instruction fetch or a data translation, address and data buffering, and
the program, the ROMP also need not wait load is delayed a cycle. Of course, as I/O ECC error detection. Error correction is not
for requested data in order to continue traffic causes the RSC usage to approach included in this time, however. (If an error is
execution. In the current implementation of

58
detected, the reply to the ROMP is cancelled
and retransmitted to the ROMP on a
subsequent cycle. This practice reduces the
Instruction
impact of ECC on access time when no error address
is detected from 80 nanoseconds to about 30
Storage
nanoseconds.) After access, this instruction is
returned to the ROMP, and is latched into the
channel ® ® ®® ® @
instruction prefetch buffer. Following latching
of the instruction, a three-cycle process
Memory address <A1 ~A2 ~A3 >
occurs. First, the ROMP extracts the opcode, Translate I A11 IA21 IA31

register addresses, and any immediate Memory A access I A1 I A3

Memory B access A2
operand. The opcode is used to address a
small microcode ROM and the register ECC I R11 IR21 I R31
addresses reference two independent read Reply latch < ~ ~ >
ports in the register file. At the end of this
ROMP
cycle, register and immediate operands and
control information have all been latched. The Instr. prefetch buffer #1 < >
following cycle, operands are manipulated in Instr. prefetch buffer #2 < >
the ALU according to the control information, Instr. prefetch buffer #3 < >
with the result being latched at the end of the Instr. prefetch buffer #4
cycle. In the third cycle the result of the Register operand fetch & control word fetch 11 12 13
operation is stored back into the register file. ALU input latches 11 12 13

Instruction execution 11 12 i3
Although there are several cycles in the Result storeback to register 11 12 13
complete instruction sequence, the process is
overlapped to a high degree. Figure 2 shows Figure 2 Timing Example --- Three 32 Bit Instructions
how the sequence described above would be
overlapped for three identical instructions. The following sections highlight some internal one cycle, but Store and I/O Write
Shown are three 32-bit instructions which functions performed by the ROMP and MMU instructions each take two cycles. The ROMP
execute in one cycle each. chips as well as the logic design and instruction set is described in Hester,
verification process used. Simpson, and Chang [4].
Rapid response (Le., low latency) to memory
requests is most important for instruction ROMP Chip The ROMP processor is partially
fetches which directly follow a branch-taken The ROMP chip is a pipelined processor microprogrammed. It uses ROM for control
execution. The contents of the instruction capable of executing a new instruction every during the execution cycles, but hardwired
prefetch buffer must be discarded in this cycle. While one instruction is being executed, control logic is used for instruction
case. Although latency of starting the new the next instruction can be decoded, and prefetching and for memory data requests,
instruction stream is fixed, the ROMP reduces following instructions can be fetched from since those operations are usually overlapped
its impact by implementing a "Branch with memory and buffered. A one-cycle execution with the execution of other instructions.
Execute" instruction. This Branch form is rate is prevented when either an instruction Figure 3 shows a block diagram of the ROMP
designed to keep the CPU busy with requiring multiple execution cycles is processor data flow.
instruction execution while the contents of the executed, or a hold-off occurs (Le., when the
Branch address is being fetched from processor waits for an instruction or data
memory. from memory). Most instructions take only

59
Instruction Fetching prefetched whenever an IPB is available and that IPB will hold its contents until that
The instruction fetch area includes the there is no other request for use of the RSC. instruction word is gated by the M UX to the
Instruction Prefetch Buffers (IPBs), the IPB Every cycle, each IPB that is waiting for an decode circuits.
Multiplexer (MUX), and the Instruction instruction ingates the data from the RSC.
Address Register (IAR) and its incrementers. During the following cycle, the tag associated The IAR, which in many systems is called a
Four IPBs are provided to keep the processor with that data is examined to determine if it Program Counter, is included among the
supplied with instructions. Instructions are was addressed to any of the IPBs. If so, then hardware System Control Registers (SCRs) in
the diagram, and has two incrementers. One
is used to update the IAR after each
instruction is executed, while the other is
used to calculate the address of the next
instruction to be prefetched.

RSC
write
Execution Unit
ALU write data
data The execution unit includes the register file,
the AI and BI latches, the ALU and shifter,
ALU and the ALU output latch. It also includes the
write
Destination ADDR ADDR MQ register and the Condition Status register,
which are both SCRs. To support a one-cycle
24 x 32 execution rate, a 4-port register file is used.
code RS read 4-port Hardware
RC read register file SCRs The register file is a RAM containing the 16
general registers, some of the SCRs, and
RSC write ADDR other registers which hold temporary values
S out A out
during the execution of some of the
Microcode Immediate field operations. Two of the ports of the register
ROM file are used to read two operands
256 x 34
simultaneously into the AI and BI latches.

~
I I Another port is used to write the result back
from the ALU output latch, and the fourth port
is used to write data from memory or I/O.

~ecute
Data is written into the register file during the
con"" first half of a cycle, and read out during the
second half of a cycle. Therefore, if the same
word is addressed by both a read port and a
write port, the new data will be read out. The
ALU is used for the execution of all arithmetic
and logical instructions, and for address
calculations when executing Load, Store, I/O
and Branch instructions. The addresses are
sent to the RSC request area. For Branches
that are taken, the address is also placed in
~----------------~----------------~--~RSC
the IAR. During the second execution cycle of
Figure 3 ROMP Data Flow

60
Store and I/O Write instructions, the it is data, the tag will point to one of two of signals. Four different formats are used, so
execution unit sends the data to the RSC descriptors which will control the alignment by that some fields have different interpretations
request area. the formatter and store it into the proper for each of the formats. The four formats are:
location in the register file. The RSC receive
A bypass is provided which allows the ALU area also checks the parity of the data word • ALU - Used for arithmetic and logical
output to be gated directly into either the AI and sends back the proper acknowledgment operations
latch or the BI latch. This bypass is used signals on the RSC.
when the result from one execution cycle is • Shift - Used for shift and byte move
needed during the next execution cycle. The Control Unit operations
bypass is activated by circuits which compare The control unit includes the microcode ROM,
both read port addresses of the register file the Control Register (C Reg), the instruction • Channel - Used for address calculations
with the address that will be used for the decoders, and the ROM and register file and RSC requests
result write port during the following cycle. address latches and control circuits. It also
includes circuits for detecting and handling • Control - Used for microcode branching
RSC Interface interrupts, machine checks, and program and miscellaneous operations.
The RSC interface consists of the request checks, as well as the SCRs associated with
area and the receive area. The request area these events. Use of a separate format for microcode
arbitrates for use of the RSC and it receives branching eliminates having an address field
the acknowledgment signals after requests The ROM contains 256 control words of 34 in every control word. Since nearly all
are sent. It also has buffer registers for two bits each. It owes its small size to several instructions use only one or two control
addresses and tags for requests to memory factors. The reduced instruction set contains words, microcode branching is seldom
and I/O. It has one buffer register for fewer than 128 instructions and most require needed.
outgoing data, and it aligns the data for byte only one execution cycle. The control words
and half-word Store and I/O Write are needed only for the execution cycles of The control words are fetched from the ROM
instructions. Instruction addresses arising the instructions, since instruction prefetching into the C Reg during the cycle prior to the
from successful Branches come from the is controlled by hardwired circuits, and the one when they are executed. During the last
execution unit, while instruction addresses last control word of each instruction controls execution cycle of any instruction, the next
which are in sequence come from the IAR the decoding of the next instruction. instruction is selected from one of the IPBs
prefetch incrementer. Requests will be re-sent Therefore, nearly half of the words are by the MUX and decoded. This decode cycle
if the acknowledgment signals indicate either available for other operations, which include is used to simultaneously fetch a control word
a busy condition or a parity error. Program Status Word (PSW) swaps for from the ROM and fetch the two operands
interrupts, System Timer updating, and from the register file into the AI and BI
The RSC receive area contains buffer Power-on-Reset (POR) initialization. The latches. The operation code is taken directly
registers for one incoming data word and tag. initialization routine checks many of the from the output of the MUX and used as the
Each cycle, they capture whatever data word internal facilities, including the Register File, ROM address. This puts nearly all of the first
and tag is on the RSC. The data word is also ALU, and RSC, and goes into an endless loop control words into the upper half of the ROM.
gated into each IPB for which an instruction if an error is detected. Another POR will If additional words are needed, the ROM
fetch request has been made. During the cause it to try the initialization again. address is usually just incremented and
following cycle, the tag is examined to switched to the lower half of the ROM. The
determine if the word is addressed to the Several techniques were used to keep the control signals are obtained by decoding the
ROMP, and if so, whether it is an instruction length of the control words short. Each word outputs from the C Reg. Also during the
or data. If it is an instruction, the tag will also contains several encoded fields, with each decode cycle, the register address for the
identify which IPB has been assigned to it. If field controlling a separate function or group result, called the destination address, is put

61
into a two-stage pipeline to be used two IRSC
cycles later for storing the result from the Address +Latch
ALU output latch into the register file.
l 1 T
System Control and Support Processor Auxiliary
processor SEG REG TLBO TLB1
Facilities 0 o

~\
serial

l(
Common

:5\
The system control facility includes an SCR port front
end
that controls the processor mode, the types ADDR RPNO ADDR RPN1
TAGO TAG 1
of interrupts that are enabled, and interrupt
/',
priority. It has an SCR for buffering interrupt 15 15
requests, and a System Timer facility for real
time applications. There is also an SCR for
identifying program check and machine check
errors. With this, the ROMP can recover from
most software and intermittent hardware
Control
registers
V"-
I\.
'" I L1

I
IAddress
L2
~ADDRtag

JLatch
~
I
t
Compare I
,
Compare I
errors. Real

The ROM P is a Level-Sensitive Scan Design

(LSSD) processor which allows the internal
STG ',/7 CTL Translate CTL
~
! MUX
f
I
registers and latches to be reconfigured as A --.. ECC
Data (40) ) Parity
serial shift registers. A support processor, .... w Interleaved
Master mode
A .. Load real
Purge
t
such as a PC, can then be used to examine Refresh K
'II
Reload
r
) Page fault l MUX
J
and alter the internal state for system or A ~
RASMODE Reload
. /"
Control ROM
program debugging. With other facilities, the '" RAM +
Storage address
processor can be stopped at a specified
instruction or microcode address, or single
stepped so that the state can be examined Figure 4 MMU Data Flow
after each instruction, The processor can also
be reset and initialized. Memory management units that depend on wide variety of ROM and RAM. Memory
processor intervention are much slower due interleaving for maximum bandwidth and error
MMU Chip to the overhead in passing control to the correction or parity checking are among the
The M M U implements the memory processor which must then save and restore options supported by the hardware. External
management features described in Hester, registers and return control to the memory logic supplies all timing-critical memory
Simpson, and Chang[4] with a number of management unit in addition to the page table controls to allow attachment of widely varying
innovations. This article will focus on a few of memory lookup function. Figure 5 illustrates classes of memory. The interface employs a
these innovations. Figure 4, showing the the significant performance advantage simple handshaking scheme that allows
MMU data flow, is included for reference. afforded by hardware TLB reloads as a attachment of different access time memories
Refer to O'Quin et al.[5] for a software function of the TLB hit ratio (the ratio of to the MMU in a manner that overlaps data
perspective of the M M U. accesses without reload to total accesses). transfers with the dynamic RAM precharge.
See also Waldecker et al.[2] and Rowland [3].
Translation Look-aside Buffer MMU Memory Interface
Automatic hardware reload is included for Another key MMU feature is a flexible The flexibility built into the memory interface
Translation Look-aside Buffer (TLB) entries memory interface capable of supporting a was not achieved without difficulties. For
when virtual addresses are not present there.

62
 address translation for the upper address Design Process
E 2.0 L_-----------:7 bits. Thus pins are saved with no Figure 6 shows the general design flow used
f
f performance impact. in the design of the ROMP and MMU.
e 1.5
c
t Many memory interfaces "hang" when an Each logic designer simulated his logic
i 1.0 out-of-range address elicits no response from macros interactively followed by full-chip
v
e the memory controller. The MMU solves this simulation using the AUSSIM simulator. The
Hardware VS. software
M 0.5 TLB miss handling
problem with a special "Address Recognized" full-chip simulation was driven by test
I
P
signal that is used to communicate invalid programs written to cover as many variations
S address conditions without machine error of functional operation as we could
0.0 .....................,I......I...........................L....L.................................................................................L...&................o....J
0.970 0.975 0.980 0.985 0.990 0.995 1.000 conditions. reasonably exercise. New test programs were
TLB hit ratio
continually added as 'problems were
Assumptions: Hidden refresh for dynamic RAMs is another discovered or new test conditions were
Base ROMP speed = 2.0 MIPS
Average instruction length = 2.5 bytes MMU implementation feature. By performing identified. The same test programs were also
refreshes to idle banks when possible, used to test the nodal model as well as chip
Figure 5 Hardware versus Software TLB Performance refresh interference is typically reduced by 50 hardware when it arrived. (The nodal model
Handling percent.

example, provisions for specifying RAM and Error Correction Logic Test program
The MMU provides an efficiently pipelined ~ design generation
ROM ranges in software created a "chicken
or the egg" dilemma of how to run this range-
setting software without the ranges being set.
This led to the invention of "master mode" in
EGG function that separates error checking
from error correction. Data transfer is done in
parallel with the checking phase and is not
1
t ,
which the MMU will accept any memory delayed in the normal case (i.e., when no Macro/chip
simulation
Nodal
model
-
request before the range registers are error is detected). If an error does occur, the
initialized. If the first request after IPL is a data transfer is cancelled and extra time is
memory read (such as a ROMP initial IAR allowed to complete correction. Thus, only +
fetch), this and all subsequent requests are accesses with errors are penalized by the ........... Performance
tuning
directed to ROM until master mode is extra cycle required for correction.
disabled by initializing the ROM and RAM
range registers. The logic level on one of the Logic Design Process +
The ROMP logic design proceeded in parallel Chip physical
pins at power-on determines whether master '---
design
mode is effective to allow using more than with the logic-circuit library definition and the
one MMU on the RSG. SGP manufacturing process evolution in
Burlington. The potential for significant +
changes required having flexible and Build
With any VLSI design, pins are always at a wafers
premium and generally force tradeoffs in automated tools for performance tuning,
performance. The MMU 24-bit memory simulation, hardware verification, chip test 1
address was implemented by multiplexing low generation, and chip problem isolation. The f t
and high address bits without incurring a physical process is described in Dupont et
al.[1 ].
TPG ---.. Test
wafers/modules
Funct. test
system
performance penalty. The low order address
bits are quickly passed through from the RSG
and latched externally, in parallel with the Figure 6 Design Flow

63
was a TTL equivalent of the ROMP chip and built by automatically converting our SGP Memory/
ROMP RSC Array
is discussed later in this article.) circuit library to TTL equivalent circuits. logic
MMU - model
model
(Nodal means that every SGP signal was
Performance optimization was performed by duplicated in the TTL design.) Simulation was
using design automation tools which identified performed using the Austin Interactive
long paths which were then corrected by a
combination of logic and physical design
Simulator (AUSSIM). I I
changes. After all of the logic macros were simulated Master Slave
AVPs
model model
individually, they were connected together
Manufacturing test was driven by test and chip simulation was performed. High level
patterns generated in the design process. simulation models were written for embedded Figure 7 Design Verification
Failure isolation to areas of the chip was arrays and for support logic to simulate a
provided by test procedures and special system environment. Architecture Verification simultaneously and automatically applying
programs written to analyze test results and Programs (AVPs) written in ROMP assembler hundreds of test patterns are used to perform
identify sections of likely failure. language were used to test the functions this testing. To determine in manufacturing
described in our functional specification. which chips in a wafer are defect free, test
Early parts from Burlington with a potential Figure 7 shows the interconnection of patterns are applied to each chip. As the
for working were brought to Austin and external high-level simulation models with the number of circuits on a chip increases, the
functionally tested in our nodal model test ROM P low-level logic. The master and slave number of test patterns required to test all
bed by replacing the CPU portion of the behaviorals simulate additional RSC traffic. possible defects increases dramatically. The
model with the ROMP Chip. The AVPs were loaded into our array model large number of circuits (>50,000) in the
and executed by the ROMP. The first AVPs ROMP and MMU necessitated generating test
Performance Tuning were written in Burlington, and Austin created data automatically. Tp do that, all latches in
Early in the ROMP design, the need to more as they were required. The ROMP AVPs the ROMP and MMU were made Level
estimate path cfelays automatically was grew to over 400 and required eight CPU Sensitive Scan Design (LSSD) latches. LSSD
recognized by Austin logic designers faced days to run on a 3081. latches can be transformed into Shift
with thousands of nets to manage. To meet Reaisters
-..., - - called
- - - - scanstrinas
- - - . - w which allow test
this need, a timing analysis too! was The nodal model helped us discover various data to be shifted into and out of the chip by
developed to estimate latch-to-Iatch paths subtle design bugs not found in logic appropriate clocking. This approach supports
based on block rise and fall delays. Block simulation. The model was quite large, automated testing by shifting in test data and
delay requirements were specified by the containing 14 boards of logic with an average then shifting out the test results. The tester
logic designer, and the physical designers of 280 TTL modules each. CPU support compares test results with correct results
adjusted the block power levels based on functions, including the memory, an I/O test previously generated during test preparation.
loading and wiring capacitance to meet the board, and a test processor interface were Figure 8 and Figure 9 show the test results
specified values. If the requested delay values part of the model. Debug of these areas for the ROMP and MMU.
could not be met, the logic designers would permitted rapid functional test of newly-
modify the design to improve the problem received chips replacing the CPU portion of Chip Defect Isolation
paths and the process would iterate. the model with the ROMP chip. Chip defect isolation involves quickly pin-
pointing which of the 50,000 plus devices on
Design Verification Manufacturing Test Generation a chip are defective.
The potential for significant changes led us to A manufacturing test is performed on each
pursue two independent design verification chip on a wafer to determine which chips Failure diagnosis started out as a laborious
methods - a nodal model and software should receive further processing. Testers manual process of listing the most likely
simulation. A nodal model of the chip was capable of probing over a hundred pads failing signals or circuits whenever a failure

64
 Chips which passed all manufacturing tests in 3. Ronald E. Rowland, "System Memory Cards," IBM RT
ROMP Test Pattern Generation
Burlington were next tested in the Austin Personal Computer Technology, p. 18.
Number of scanstrings 5 4. P.D. Hester, Richard O. Simpson, Albert Chang, "The
maufacturing card test by having the
Longest scan string 157 latches RT PC ROMP and Memory Management Unit
processor card execute a comprehensive set
Number of CPU hours to generate 76 hours (3081) Architecture," IBM RT Personal Computer Technology,
Test coverage on random logic 98.6%
of test software. Discovery of defective parts p.48.
Test coverage on OCDs 100 %
on the processor card is infrequent,
5. J.C. O'Quin, J.T. O'Quin, Mark D. Rogers, T.A. Smith,
Test coverage on RAM 100 % demonstrating the effectiveness of our chip "Design of the IBM RT PC Virtual Memory Manager,"
Test coverage on ROM 100 % test methods. IBM RT Personal Computer Technology, p. 126.

Conclusions
Figure 8 ROMP Test Pattern Generation The organization of the ROMP and MMU
chips, together with the design tools which
were used, have resulted in a high-
MMU Test Pattern Generation performance and flexible processor complex
Number of scanstrings 6 for the RT PC family. The 32-bit RISC CPU
Longest scanstring 169 latches (ROMP) is designed to execute an instruction
Number of CPU hours to generate 15 hours (3081) every cycle and the memory system is
Test coverage on random logic 99.4 % capable of supporting this high execution
Test coverage on OCDs 100 % rate. The high memory bandwidth requirement
Test coverage on RAMs 100 % of the ROMP is satisfied by the combination
of a packet-switched ROMP-MMU interface
(RSC), interleaved memory accesses, and a
Figure 9 Design Verification
pipelined MMU design for address translation
and ECC. The MMU memory management
was detected. The process was improved by
chip contains performance enhancing features
using the AUSSIM simulator to resimulate the
such as automatic hardware TLB miss
failing test patterns to reduce the list of
handling, hidden refresh, and ECC error
possible defects. Later the process was
handling.
improved further with a program that analyzes
all possible defects that could cause a failure,
The design and test tools evolved during our
and filters all but the most likely causes. This
design have been used to design other chips
program proved very successful in accurately
with greater device counts and the diagnostic
pin-pointing defects.
tool has grown in importance and usage for
resolution of chip defects.
Bench-test setups for probing directly on
Signal lines which were only microns wide
References
helped find defective circuits. 1. Raymond A. Dupont, Ed Seewan, Peter McCormick,
Charles K. Erdelyi, Mukesh P. Patel, P.T. Patel,
State-of-the-art tools such as lasers for "ROMP/MMU Circuit Technology and Chip Design,"
cutting shorted nets and voltage contrast IBM RT Personal Computer Technology, p. 66.
tools for observing chip behavior were used 2. D.E. Waldecker, K.G. Wilcox, J.R. Barr, W.T. Glover,
to pin-point and repair defects isolated with C.G. Wright, H. Hoffman, "Processor Card," IBM RT
Personal Computer Technology, p. 12.
the diagnostic program.

65
ROMP/MMU Circuit Technology and Chip Design

Raymond A. DuPont, Ed Seewann, Peter McCormick, Charles K. Erdelyi, Mukesh P. Patel, P.T. Patel

Introduction voltage from the standard 5-volt supply in the

A VLSI design of a 32-bit 801-based RISC system.
microprocessor [1,2,3] was a significant
challenge in the late seventies. The In addition to the circuit challenge, the design
semiconductor processes that were then fully methodology was developed as the chip was
developed did not provide the necessary designed. The available design techniques of
Out
density or performance capability for a one- master slice (gate arrays) and master image
chip implementation of the entire processor (standard cell) were widely used but neither
1N1o-1
function. The 2-micron silicon gate NMOS would provide the necessary density or
technology under development in Burlington performance. A fully custom design would
[4] appeared to offer the higher packing have been too costly for a non-commercial
density and the lower power circuits required chip with volumes less than the normal break- Figure 1 Depletion Load Circuit
in the low-cost system environment. The even point. The best design technique was to
circuit challenge was to use this new use custom circuits in high-leverage data flow provides is a threshold below the supply
technology to design a 200-nanosecond, areas and master image in control (random voltage. The depletion push-pull circuit is
single-chip, 32-bit microprocessor at low logic) areas. used only in areas where a higher up-level is
enough power to satisfy cooling and reliability required. As a general design practice, push-
constraints. Circuit Technology pull circuits were used primarily to drive
global wiring.
Many additionai chaiienges faced the design Base Circuit Technoiogy
team throughout the chip development The The base circuit technology consists of A circuit analysis indicated that the minimum
chip architecture, device process, and all the standard NMOS FET pull-down devices with a power/delay product of the circuit shown in
design tools used to develop the chip were depletion mode pull-up device as shown in Figure 1 occurred at a power supply voltage
new. Even with the early device models that Figure 1. (Vh) of 3 volts. Since 3.4 volts is used by
were provided to the circuit designers, it was some technologies, the compromise was
predicted that the chip powers would exceed When this circuit must drive a large load made to use this value. While the lower
those necessary for the desired cooling and capacitance, a buffer stage is added. In a voltage provides a significant leverage in
reliability. For this reason, an investigation buffered circuit the pull-down devices are many circuits, there are some that perform
into the circuit power/performance was enhancement type, however the pull-up more optimally at 5 volts. Typically, these
undertaken to find a solution to the on-chip devices can be either enhancement or were circuits with low capacitance loading in
power. This investigation led to the depletion type. Figure 2a/2b shows the two which gate capacitances comprised most of
exploration of power supply voltages lower types of buffered ("push-pull") circuits. the net loading. These circuits were kept at 5
than the customary 5 volts, the analysis of Because of its lower power dissipation, the volts. Figure 3 shows how the 5-volt, 3.4-volt
circuit design parameters associated with enhancement push-pull circuit was chosen for and push-pull circuits might be optimally
lower voltage, and generation of a lower general use, even though the up-level it

66
 Custom Circuit Design
Td (ns) The combination of a two-level metal silicon
gate enhancement / depletion NMOS
10 technology and the 32-bit RiSe architecture
Out made custom design an attractive alternative
8
I
for the repetitive logic elements in the data
I
I
flow. This was particularly evident for the on-
6
I
I
chip storage elements which included a 24-
4
I
I
word x 32-bit four-port, simultaneous read-
10.5 mW/circuit write register file implementation of the
I fanout = 3 microprocessor general-purpose registers, a
Figure 2a Enhancement Push-pull 2 I
I RAM implementation of the two-way
I

0.2 0.4 0.6 0.8 1.0 1.2 C wire

associative Table Look-aside Buffer on the
(pF) address translation chip, as well as numerous
18- and 36-bit multi port data-selector
Figure 3 Circuit delay (Td) as a function of wiring registers used throughout the design of both
capacitance chips.
Out

transistor and regulated by the on-chip Whereas the RAM cell was implemented with
regulator. a standard six-device symmetrical cell, the
register file cell was implemented using an
Off-Chip Drivers eight-device asymmetrical cell as shown in
Off-chip driving presented several challenging Figure 4. In this cell, the read devices 5 and 6
Figure 2b Depletion Push-pull problems. The delay of many of the off-chip are made small relative to device 4 to prevent
drivers was in the critical paths, requiring inadvertent destructive read out. The write
applied as a function of the wiring delay to be kept at a minimum. Since the devices 7 and 8 are made large compared to
capacitance. capacitance loads are quite large (in the the current sourcing capabilities of devices 1
range of 25 to 75 pF), faster switching and 2 to guarantee writing.
In order to provide an adequate noise margin requires substantial currents. When off-chip
for the transfer of 3-volt signals, the size of drivers switch simultaneously, the peak
the active input devices was double that currents algebraically add and cause
which would have been used in a 5-volt substantial shift in the ground or power
circuit. This did not have a significant impact supply nets, especially in 32-bit designs. This
on circuit density since the circuits were used shift can disturb the internal circuits. In order IN 0 Out 0

primarily in wiring limited areas. to prevent this, only 12 drivers are connected
to a pair of power and ground pads. In
The 3.4-volt supply was not readily available addition, the 3.4-volt power supply is used to IN 1 Out 1

in the system and it had to be generated from power the final driver stage. This gives an
the available 5-volt supply. This was done improvement in the performance as well as a
using an on-chip regulator to drive the base reduction in the switching currents. Write 1 WL

of an external PNP power Darlington. The

voltage differential is dropped across the PN P Figure 4 Eight-Device Register File Cell

67
Transfer devices were also employed to Sensitive Scan Design, [4]) shift function. The Floor planning is done in conjunction with the
provide area and performance improvements input transfer devices, together with the input high-level logic definition and determines the
in the design of the data registers. A circuit capacitance of device 9, comprise a master optimum size, aspect ratio and placement of
schematic of a typical latch stage of a data latch in which the capacitance of terminal 312 each macro and input/output on the chip
register is shown in Figure 5. The slave latch acts as a storage element. The additional image with appropriate space left for global
of this master-slave latch pair, as shown, is input devices form a data-selector or wiring. An abbreviated version of the chip
composed of nine individual devices. Devices multiplexer function allowing different word floor plan for the CPU chip is shown in Figure
1 and 2 form an output buffer stage to drive inputs to be selected. 6. The floor plan is broken into three areas:
large capacitance loads. Transfer device F, 1) data flow stacks, 2) random (control) logic
when connected to the buffer output, Custom design of these respective data form master image (standard cell) and 3)
performs a polarity hold function and device storage elements using transfer devices to mixed random logic and data flow.
G, when connected to the output of the their natural advantage significantly reduced
previous stage, performs an LSSD (Level chip area, improved performance and lowered After completion of the chip floor plan the
chip power. In addition, the use of standard macro design can begin. This is done in two
predesigned functional blocks, such as steps. The custom bit-stack macros are done
registers, facilitated and standardized the first when the logic data flow is defined, and
logic for these components, reduced data the master image macros are completed as
entry and simulation time and finally formed the control logic is frozen.
the nucleus of the "bit stack" data flow
physical design image for both chips.
Chip
Vdd Vdd Vdd

In addition to these custom circuits, other

specialized circuits were used where they
provided an advantage. These circuits include
ROM, multiplexers, parity and ECC, ALU, ~ S Rsupermacro

incrementers and comparators. These circuits

were manually designed as required.
I I ~ Macros

! !! ! liilililili.!

Custom Physical Chip Design Super macro

D
During the physical chip design, five levels of

Hold
Read wordline
L2 clock
hierarchy were defined. These consisted of
the chip, super macro, macro, circuit and
transistor. The use of hierarchical design
~ ilNrF
I
III
III

T # = Q buffer n
* = Q buffer n-1
methodology allows the design to proceed in
two areas in parallel, these being the macro
Master image Mixed Custom

Shift
and global areas. This reduces the chip
design turnaround time and permits the
T 312
design of reusable macros. This hierarchical
top-down approach proceeds in three steps. Figure 6 Abbreviated Chip Floor Plan
The first step is the chip floor planning, the
Figure 5 Data Register Bit Cell second is the macro design, and the third the
global design and verification.

68
Data Flow Bit Stacks Wiring bays

A data flow stack is a predefined bus

structure to coordinate macro-to-macro x
T T ~ l
communications along predefined wiring I
x x x
channels. The primary characteristic of the x I
macros placed in the bit stack is their bit-slice
~ ~ ~
nature. The macros are designed in a 1 X N
configuration, 1 bit in height and N bits wide.
Typical macros in the data flow stack are data T
~ ~
registers, multiplexers, register file, ALU, Control x I Control
shifter, rotators, parity functions and off-chip signals ~ ~ signals

data bus structures. The macros are then , x

placed in the vertical stack, aligning the bits I Circuit columns Circuit books
from macro to macro. x x ~
x Figure 8 Control Logic Image
For both the processor and memory (2) N
management chips the data flow stacks were Data or down after placement and wiring are
designed for seven 36-bit data buses across
the horizontal cross section as shown in
• Macro output
x Macro input t flow complete. The chip critical paths can then be
power-tuned late in the design cycle to
Figure 7. The data bus wiring flows vertically improve overall chip performance and the
and the control signals flow horizontally. By Figure 7 Data Flow Bit Stack
over-powered nets can be adjusted to reduce
integrating the data bus with the circuits, both on-chip power dissipation.
meta! layers are fully utilized, reducing chip powering levels to obtain a wide range of
area, as circuits can be placed under the power performance for each circuit. Global Design
wiring. The minimum distance between inputs Appropriate push-pull drivers were also After chip floor planning is complete as
and outputs can be obtained by efficient wire provided to drive the global wires that leave described above, the global chip design is
packing of the data buses, reducing wiring the macro boundary. defined at a high level. The actual macro
capacitances and improving chip input/output positions are required for the
performance. Another advantage of bit-stack The circuits in the control logic macros are global chip wiring. These are defined for the
design is that it allows reuse of general- automatically placed and wired. This permits data flow stacks early in the design process
purpose macros such as multiplexers, parity the control iogic to be designed late in the and the control logic macro input/output pins
checkers, data registers, etc. These macros design cycle, similar to a PLA approach but are fixed prior to their design. With this
can be predesigned to fit into this structure, with the advantage of having control of path information, both the macro and global chip
thereby preserving the custom advantages performance. The basic layout for a typical designs can proceed in parallel. Capacitance
while keeping the design time and resource at master image macro is shown in Figure 8. values are continually fed back for
a minimum. The circuits are of a fixed height, but have a performance estimation and verification
variable width depending on the function. during the global design phase.
Master Image Design There are variable wiring bay widths between
The control logic structures are implemented the circuits for interconnection. Once the Design Verification
using a master image (standard cell) circuit bays and wiring bays are defined, In a complex VLSI design, one of the keys to
approach. The circuit library is predefined and placement and wiring programs, based on success of the design is the ability to verify
consists of 200 combinations of AND, OR, those described by Donze et al.[5], complete the process ground rules and logic-to-physical
NAND, NOR, OAI, AOI, XOR and latches. the design of the macro. The power-tuning correspondence. Due to the complexity of the
Each of these books has five different option permits each circuit to be powered up process and the subsequent lengthy

69
processing times, it is imperative that the the commercial environment where large 7. P. McCormick, M. Lang, "Hierarchical Design
design be fully functional on the first pass. numbers of chips will be built and every last Methodologies, A VLSI Necessity", Advances in CAD
This is achieved through a very extensive bit of silicon must be used. Some trade-offs for VLSI, vol. 6, Design Methodologies, 1985 (in
press).
checking methodology. In order to contain the have been made between silicon area and
8. 1MB Corporation installed user program document
data volumes, the macro designs are design turnaround time, where automatic
SH20-1118-0, "Advanced Statistical Analysis Program
individually checked for both logical-to- tools are effective. (ASTAP), Program Reference Manual", Program
physical correspondence and process ground Number: 5796-PBH.
rules. This data is then suppressed and the Finally, the successful combination of all the
same checks are repeated at the global level. design techniques permitted a complex and
The macro level logical-to-physical checks are highly bused architecture to be implemented,
done down to the device level, while the providing the major logic components to the
global checks are done only to the macro system in only two chips.
level. In addition to the above key checks,
other verification is done on the chip Photomicrographs of the two chips are shown
performance, DC power drops and power in Figures 9a and 9b.
busing, as well as manual audits.
Acknowledgments
Conclusions The circuit and physical design of the
Both the process and the circuit technology processor and memory management chips
were selected to achieve the design of a high- reflects the contribution of many designers in
performance, 32-bit, 801-based RISC both Austin and Burlington. Their efforts are
processor and memory management unit at gratefully acknowledged.
reasonable system cost. The use of the lower
voltage circuits reduced on-chip power and References
improved circuit performance. To provide an 1. George Radin, "The 801 Minicomputer", IBM Journal
economical power supply for the lower level of Research and Development, 27, 237-246, May 1983.

of supply voltage, an on-chip voltage 2. George Radin, "The 801 Minicomputer", ACM,
regulator was used, Innovative custom
3. D.E. Waldecker. C.G. Wright, M.S. Schmookler, T.G.
designs significantly improved the overall
Whiteside, R.D. Groves, C.P. Freeman, A. Torres,
processor performance and provided a more "ROMP/MMU Implementation," IBM RT Personal
efficient use of silicon. The hierarchical design Computer Technology, p. 57.
method reduced the overall design time by 4. E.B. Eichelberger and T.W. Williams, "A Logic Design
permitting more than one area of chip design Structure for LSI Testing", Proc. 14th Design
to proceed in parallel. The separation of data Automation Conference, June 1977, 77ch1216-1 c,
flow and random logic permitted the custom pp.462-468.
circuits to be employed for high-leverage 5. R. Donze, J. Sanders, M. Jenkins, G. Sporzynski,
repetitive logic and standard cell design for "PHILO - A VLSI Design System", ACM IEEE 19th
Design Automation Conference, June 1982.
the control logic, where fast design
6. R. Bechade, M. Concannon, C. Erdelyi, W. Hoffman,
turnaround time is required. In addition, the
"A Comparison of Mixed Gate Array and Custom IC
use of the data flow concepts permitted a Design Methods", 1984 ISSCC Digest of Technical
highly-bused architecture to be implemented Papers, February 1984.
in a small chip area. Many of the design
concepts described in this paper are unique
to the IBM design environment as opposed to

70
Figure 9a Processor Chip Figure 9b Memory Management Chip

71
Software Development Tools for ROMP

Alan MacKay and Ahmed Chi bib

Introduction the execute form of Branches which perform compiler assumes that certain registers (RO-
Traditionally, a microprocessor is designed the next ("subject") instruction in parallel with R5) are killed (scratch registers) by a CALL.
with minimal interaction between the the branch, or the overlapping of a Load The compiler, therefore, uses those registers
hardware and software engineers. The instruction with the execution of another first to avoid saving and restoring any of the
resulting architecture often contains many instruction that doesn't require the result of CALLer's registers. However, if more
complex instructions and addressing modes the Load. This was accomplished by having a registers are needed, they are used in
well suited for the assembly programmer. scheduling mechanism in the compiler that descending order (R15-R6). This is
However, such instructions are seldom analyzes each basic block of generated code particularly important because the STM (Store
utilized by compilers due to their complexity. and rearranges the instructions to facilitate Multiple) instruction always saves from the
such an overlap. register specified through register 15.
This paper describes a set of tools used to
assist the hardware engineers in designing, In the spirit of the RISC architecture, certain After the initial ROMP design was completed,
refining and verifying the architecture of a high-level functions on the ROMP, such as a few opcode points remained available. To
Reduced Instruction Set Computer (RISC) [1] multiply, divide, and storage-to-storage move make the best use of them, a statistical
to be a suitable target for optimizing operations, are implemented with subroutines gathering feature was added to the compiler
compilers. This IBM System/370-based tools rather than microcode. On the assumption to collect information on the frequency of
package consists mainly of an optimizing that only one shared copy of these routines instructions and their operand's value. After
compiler, a binder, a fast simulator, and a will exist, the subroutines, which are called numerous bench marks had been compiled,
host of execs, utilities and libraries. We Run-Time Routines are hand tailored and those opcode pOints were assigned to the
should point out that these are internal IBM highly specialized for speed efficiency without short form (2 bytes) of severa! instructions.
tools and are not part of the software regard to space.
available for the IBM RT PC. The short-form instructions included memory
Most languages, regardless of their level, "Loads" and "Stores". They have a
Compiler Tailoring make use of subroutines to implement maximum displacement field of 15 units,
The ROMP processor architecture [2] and primitives and data abstractions. The PL.8 where the unit is a byte, half-word, or word
compiler design was a cooperative effort compiler takes advantage of the ROMP depending on the particular instruction. The
performed by software and hardware architecture by providing an efficient PL.8 compiler tries to maximize the use of
engineers in Austin and Yorktown. It was one subroutine linkage and parameter passing these short-form instructions by arranging the
of few projects where compiler technology mechanism. In passing parameters, the first program's data so that the small and most
influenced many hardware decisions and vice four are loaded into predetermined registers. frequently used variables are mapped closest
versa. The ROMP instruction set was tailored The invoked procedure may use those to the base address, without regard to the
for speed and space efficiency of the registers without ever having to copy them order in which they were declared in the
generated code without sacrificing the into storage. program.
function of the processor itself. By the same
token, the PL.8 compiler [3,4,5] took Another aspect of subroutine linkage is the Because the compiler was deSigned as a
advantage of such hardware features [6,7] as procedure's prologue and epilogue. The PL.8 state-of-the-art compiler, particular attention

72
was not paid to the resources required for even longer before models would be available into the 370 instructions which are then
compilation. Thus, the compiler demands a in sufficient quantities to allow general executed. For example, the ROMP instruction:
significant amount of computer resources. availability to programmers. In order to allow
early testing of the compiler, a simulator for cas r5,r6,r9
Program Binder the ROMP was implemented to run on 370.
Data integrity and early error detection have will expand into the following 370 instructions:
always been elusive goals in programming. The simulator allowed verification that the
Hardware engineers provided us with code generated by the compiler was correct r1,disp_r6(b}
protection keys and supervisor state, while and complete. This gave the software and al r1,disPJ9(b}
language designers raised the level of the hardware engineers more confidence that the st r1,disp_r5(b}
source languages. In the PL.8 compiler, as in architecture changes to the ROMP were bct time,continue
some other compilers, run-time checking was needed and could be used by the compiler. bal ric,end
introduced to protect the programmer from The knowledge that the code generated by
obvious errors like indexing out of an array the compiler was correct allowed errors in the The Load instruction gets the contents of the
bound, or beyond the end of a string. The first prototype hardware to be identified and simulated ROMP register 6 into a 370
ROMP instruction set has trap instructions corrected without going through the tedious register. The Add Logical gets the contents of
that allow such run-time checking to be determination of hardware or software fault. ROMP register 9 and adds it to what is in
implemented at a very low cost in both space register 6. The Store then sets ROMP register
and execution (approximately 100/0). However, A primary factor in the usability of the 5 to its new value of register 6 plus register
a compile time option is provided to eliminate simulator was its fast execution. This is 9. The Branch on Count instruction
checking code generation. accomplished by what we term decrements the number of ROMP instructions
"compulation." Compulation is a simulation left to be executed before halting execution,
In addition to run-time checking code, the technique of translating the simulated and then branches to the next simulation
P~.8 language requires the declaration of all instruction into a sequence of native instructions. If the number of instructions
external procedures along with the instructions. These "compiled" sequences of goes to zero, the Branch and Link instruction
description of their arguments. This insures native instructions are kept for subsequent re- branches to the code that re-materializes the
that the data types of the actual parameters execution of that simulated instruction. Each ROMP condition codes, program counter, and
specified on a procedure call actually match 256 bytes of the simulated ROMP memory is other system information before returning to
those parameters specified on the procedure mapped into 4K-byte areas of 370 memory. the user interface.
definition. Moreover, the PL.8 compiler These 4K-byte areas are divided into "cells"
generates symbol cards in the text deck for of 32 bytes, each cell corresponding to a half- This "compulation" requires additional
both the entry declaration and the subroutine word of ROMP memory. These cells hold the overhead when an instruction is executed for
definition. This allows the binder [8] to 370 instructions to simulate the corresponding the first time, but most work done by
perform type checking at bind time for ROMP instruction. The 4K-byte areas are computers is done by looping, so that a
separate compilations. reusable; more available 4K-byte areas significant amount of time is spent re-
results in more ROMP code maintained in its executing the same instruction, without any
Design and Use of Simulator "compiled" form. Each cell is initialized as a further decoding of the ROMP instruction.
As the ROMP version of the compiler was branch to a routine to "compile" a ROMP
being developed, it was necessary to ensure instruction. All simulation execution is a Another factor in the simulator that allows
that the code being generated was correct branch from one cell to another. If the cell very fast execution is that the condition code
This was at a time when the hardware des~gl contains a compiled instruction, that ROMP bits for the ROMP are not calculated until
was not yet complete, and it would be at least instruction is simulated. Otherwise, the needed, e.g., until a bit is tested by a
a year before a prototype of the ROMP corresponding ROMP instruction is compiled conditional branch or the simulation is
processor would be available. It would be stopped and control is returned to the

73
command processor for interaction with the
user. As part of the simulation of instructions C PL.8
source
1 C~ource 1 ( Pascal
source 1
that modify a condition status bit, the
operation and operands are saved. Then,
, , ,
when a bit is tested by a conditional branch
just that bi~ is reconstructed for use by the ' Text
PL.8 optimizing compiler
branch. This re-materialization of the needed editor

condition code bits provides a performance

benefit because the 370 condition codes do
not have to be remapped into the ROMP
, , , ,
condition codes which take many 370
ROMP S/370 S801 M68000
instructions. It can also be observed that the S/370 ROMP
condition codes set as a by-product of
instruction execution are seldom used, and
Figure 1 Three Source Languages, Four Target
then usually only a single one of the Machines
conditions will be tested. Link edit Link edit

was especially valuable when early processor

These simulation techniques allow execution
samples were received. One sample of the
of large amounts of ROMP code at very low
processor had a defective register 2, which is Execute Execute Simulate
cost on the 370. The first time cost of
the function return value register and first on on on
"compiling" the ROMP instruction is on the S/370 ROMP S/370
paramete~ register. Within a couple of days,
order of 100 370 instructions. But once the
the co~pller was changed and all applications
ROMP instruction has been "compiled", the
recompiled to not use register 2. If a
execution time is only 5 to 10 370 instructions
significant amount of assembler code existed
executed per ROMP instruction simulated.
such flexibility would not have been POSSible.'
Code Development Support Figure 2 Code Development Process
Using the 370, backend programs cou!d be
The availabiiity of good software tOOlS IS often
written in any of the three ianguages
as important as the processor itself. The cycles are counted manually to produce
supported by the PL.8 compiler. They were
R~MP was ~o exception. The PL.8 compiler summarized results that are often
then compiled, modified, and tested natively
which compiles three different languages qu~st!onable at best, due to the difficulty in
on 370, taking advantage of all the VM tools
(PL.8, Pascal, and C) and produces code for verifYing that a given program does in fact
long before the ROMP processor was '
four different machines (370, ROMP, M68000, perform the specified function. However,
availabl~ (see Figure 2). Once a program was
and 801) (see Figure 1), along with a fast much easier procedures existed for ROMP.
tested, It could then be simulated on the
simulator, binder, and a host of other tools Since we were confident that the PL.8-
ROMP fast simulator, or executed on the
provided an excellent code development ' generated ROMP code was comparable to
ROM P model itself when the model became
environment that was to show the advantages the best handcode, all coding was done in a
available.
of the ROMP over other microprocessors. HLL. Compilation and testing was all done on
370. The compiler listings provided us with
Tools are also important in measuring the
The presence of a compiler from the code and data size information, while the
p~rf~~mance of a microprocessor. When only
beginning of the processor design allowed simulator gave us the cycle count. The
primitive tools are available, bench marks are
most of the code written for the ROMP co~~ariso.n res~lts, though almost always
coded in assembly language, and bytes and
processor to be in a high-level language. This positive, did at times highlight some

74
inefficiencies in the hardware architecture, 7. George Radin. "The 801 Minicomputer." Proceedings
and/or the compiler-generated code, which of Symposium on Architectural Support for
Programming Languages and Operating Systems, Palo
were then corrected.
Alto, California, March 1-3, 1982
8. G.J. Chaitin and C.C. Hoagland, "A Compiler Output
Conclusions Format and Its Binder and Loader," Paper to be
The unique design and early availability of the published.
ROMP simulator allowed development and 9. Thomas G. Lang, Mark S. Greenberg, and Charles H.
extensive testing of tools such as the PL.8 Sauer, "The Virtual Resource Manager," IBM RT
compiler and application prototype code Personal Computer Technology, p. 119.
before any hardware was available. The
hardware and software engineers designing
the ROMP processor together produced a
full-function, general processor without
unnecessary complex instructions that would
be unused by software and expensive to
implement in hardware. The presence of a
compiler from the beginning of the processor
design allowed most of the code for the
ROMP processor to be written in a high level
language. The VRM [9] was mostly written in
PL.8. When some assembler code was
required for performance, the PL.8 compiler-
generated code was used as the starting
program for hand tuning.

References
1. D.A. Patterson, "RISC-1: A Reduced Instruction Set
VLSI Computer," Proceedings of the Eighth Annual
Symposium on Computer Architecture, May 1981.
2. D.E. Waldecker and P.Y. Woon, "ROMP/MMU
Technology Introduction," IBM RT Personal Computer
Technology, p. 44.
3. M. Auslander and M.E. Hopkins, "An Overview of the
PL.8 Compiler," Proceedings of the SIGPLAN '82
Symposium on Compiler Writing, Boston, MA. June
23-25, 1982.
4. M.E. Hopkins, "A PL.8 Overview," Paper to be
published.
5. M.E. Hopkins, "Compiling for the RT PC ROMP," IBM
RT Personal Computer Technology, p. 76.
6. P.O. Hester, Richard O. Simpson, Albert Chang. "The
RT PC ROMP and Memory Management Unit
ArChitecture," IBM RT Personal Computer Technology,
p.48.

75
Compiling for the RT PC ROMP

M.E. Hopkins

Introduction us.) Examples of compilation techniques will One of the more expensive operations on
The IBM RT PC ROMP architecture is be given later. We also have a certain bias to many computers is branching. As long as
relatively low level and simple. A natural simple hardware solutions. Part of this is instruction execution proceeds sequentially it
consequence is that the primitive instructions aesthetic, but we also have a suspicion is possible to prefetch and decode
should execute rapidly on most grounded on experience that the next instructions ahead of their actual execution.
implementations. Does the choice of such a language just may not match the complex This overlapping is usually termed pipelining.
low level interface make sense given that operation which is built into an elaborate When a branch is encountered a new
almost all programming today is, or should architecture. instruction stream must be found.
be, done in a high level language? Could Conditionality and computed branch targets
compiler writers do a better job if the CPU The discussions that follow are based on the complicate the decisions that must be made
was somewhat more elaborate, with Pl,8 compiler, which accepts source in hardware. Very-high-performance machines
additional functions tailored to the constructs programs written in C, Pascal and Pl,8, a do prefetch on multiple paths and retain
commonly found in high-level languages? Of systems dialect of PL/I. A description of the branch history tables to avoid "flushing the
course it is clear that code can be generated compiler is given in Auslander and pipe." Most one-chip processors simply
for any execution model. Examples of Hopkins[1]. Pl,8 produces optimized object accept expensive branches as a fact of life.
execution models are register transfer, stack, code for System/370 and MC68000 as well as The ROMP solution is to define a family of
and storage-to-storage. Unlike human coders, ROMP and the 801 minicomputer [2]. The execute branches that perform the next
compilers will tirelessly and accurately compiler largely relies on global optimization ("subject") instruction in parallel with the
generate long sequences of code to map one and register allocation to produce good object branch. Implementing this facility only
model of a language onto a machine with code, The VRM and various ROMP tools complicates the hardware a little, It thus
another model. The hard task is to obtain were developed using Pl,8. Originally, the becomes the responsibility of the compiler to
efficient code for a particular machine. compiler was an experimental vehicle used to produce execute branches. Through most of
build software for the 801 minicomputer, but compilation, the compiler only deals with
Which style of machine is best? Our in recent years it has been used in a number branches in the familiar non-execute format.
preference for a machine like the ROMP is of internal IBM projects. It is not presently At one point a scheduling process is run
based partly on fundamental engineering available to customers. which rearranges code between labels and
constraints and partly on our ability to use branches. (This unit is termed a basic block.)
well understood compilation techniques to Hardware/Software Cooperation One of the goals of scheduling is to place an
obtain high quality code. An example of a Both hardware and software affect system instruction that could become the subject of
fundamental engineering constraint is that performance. The compiler writer must accept an execute branch just in front of the branch.
operations that are internal to the CPU, such his share of the responsibility. The ROM P (The main constraint is that the branch cannot
as register-to-register add, run faster than architecture divides the task in ways that lead depend on the result of the subject
instructions that reference storage, even on to better performance without excessive instruction.) Other optimizations are unaware
machines with caches. (The fact that some burden on either hardware or software. A few of the compilation of execute branches. Final
machines slow down basic arithmetic to examples will indicate how responsibility is assembly then looks at the instruction that
memory reference speed should not concern shared. precedes every branch and flips the pair if it

76
is valid to convert a normal to an execute register allocation. The ROMP makes these temp = a + b
branch. Branches tend to constitute over 20% operations easier and more profitable. x = temp
of all instructions executed. Even if only half
of all branches can be transformed to the Let us examine these optimizations in the y = temp
execute form, a modest increase in hardware light of machine models and how they
and compiler complexity has resulted in the evaluate expressions: The added storage references may well make
effect of a 10% reduction in the path length or commoning counterproductive. We shall say
number of instructions executed. • Stack computation no more about the stack or memory model.
Whatever their virtues for simplifying
A similar situation exists with loads. Loads • Memory-to-memory compilation, they seem to guarantee more
tend to take substantially more time than storage references and thus worse
register-to-register (RR) ops, but it is possible • Memory-to-register performance than the other two models.
for the hardware (in Real mode) to overlap
the load with execution of the following • Register-to-register The storage-to-memory model is shared by
instruction if the next instruction does not 370 and MC68000. At first glance a 370-type
require the result of the load. The scheduling Consider the source code fragment: approach seems attractive.
process also rearranges code to facilitate
such overlap. If loads constitute 15% or 20% x = a + b; x = a + b; L R1, a
of all executions, it is easy to see that (a few statements, which destroy x, leaving A R1,b
another 10% or greater reduction in effective a and b) ST R1, x
path length may be achieved here. Notice that y = a + b;
a machine that bundles the fetch of an y = a + b; ST R1, Y
operand from memory with a computation If the iecomputation of a + b is to be
cannot easily overlap fetching with some avoided on the stack machine, an explicit On the ROMP we get:
other function. copy in storage must be made and then the
value must be refetched from storage when x = a + b; L R1, a
Of course the object code that comes from assigning to y. The trouble with this strategy L R2, b
such a compiler looks strange. In some is that "remembering" is very costly. On the CAS R3, R1, R2 Add
sense, you are seeing the equivalent of the ROMP an RR Add costs one cycle, while ST R3, x
internal state of a very costly high- Loads and Stores take between three and
performance pipelined processor. Writing five cycles depending on whether the machine y = a + b; ST R3,y
optimal assembly language code requires is in real or virtual mode and whether or not it
some care on the ROMP. It is rather like is possible to overlap another instruction with The ROMP takes one more instruction. (It
microcoding. However, on the ROMP the the load. Unless an operation is very does have some opportunities to obtain
process is systematic, if tedious, making it expensive, it is often as efficient to recompute overlap on the Loads by inserting unrelated
fortunate that most programming is done in a as to "remember" on a stack machine. On a instructions, but let us ignore that benefit). If
high-level language. memory-to-memory machine one must often the example is changed slightly to:
pay for an explicit copy as in the following
Compilation Strategies code for a hypothetical memory-to-memory x = a + b;
The most important optimizations performed machine: Y = a - b;
by the PL.8 compiler are probably moving
code out of loops, the elimination of
redundant computations (commoning), and

77
We then get on 370: % of The reference to e(i) includes the following
Instruction execution factors:
x = a + b; L R1, a
C: compare 1.74
A R1, b • The address of the structure a
N:and 1.26
ST R1, b
AL:add logical 1.07
• The displacement of e within a
CL:compare logical .44
y a - b; L R1, a
A:add .39
S R1, b • i times the stride of c.
S:subtract .37
ST R1, Y
O:or .36
In PL.8 and Pascal, subscript range testing is
CH:compare half .33
After the first statement, neither a nor bare normally done even on production code. Thus
AH:add half .24
available and they are the operands of the there is also a trap to ensure that the value of
SH:subtract half .10
next statement. On the ROMP, both are i is between zero and ten. The fetch of e(i)
MH:multiply half .07
available and so there is no need for an may be commoned or moved out of a loop,
expensive refetch. Of course we can turn the but there are many other opportunities for
If all such ops are included, the percentage, of
370 into a ROMP-style, register-to-register optimization. The load of the address
executions is less than 6.5%. Modest as this
machine. The problem is that the 370 Add . constant to locate the structure need not be
figure is, it overstates the advantage to be
instruction destroys one of its operands, while repeated when a reference is made to b.
gained from memory-to-register ~ps, .as many
CAS, an Add that doesn't set the condition Storing into d(i) requires no additional
of these instructions are addreSSing literals.
code on the ROMP, is three-address. The instructions. Programs are filled with
On the ROMP they would be immediate ops.
PL.8 compiler goes to considerable effort to opportunities to reuse portions of this
In light of frequency of usage, potential
give 370 code the benefits .of both the. administrative type code. The higher the level
performance improvement, hardwar~ , ,
storage-to-register and reglster-to-reglste~ of the machine, the less chance there will be
requirements and compiler comple.xlty It IS
approaches. It is not clear that the effort IS for reuse, as one factor may change.
hard to believe that storage-to-reglster ops
worth it. On some 370 models, two Loads
are cost effective.
and an Add Register may be as fast as Load, An example of this phenomenon is in
Add from Storage. In any case there are ..,..J • _ .a. 1-..- ,,:.a.L-..
:"""""""'~""'-I!"'t""".... ......
subscript computations. As the ROMP does
The i6au6i may IIOL uo IIlltJl o;:);:)ou VVILII
....

relatively few storage-to=register not have a built-in multiply instruction, the

optimizing a + b, and would be corre~t if the
computational operations in a typic~1 , compiler generates a series of shifts, adds
only benefit of optimization was a rewnte of
snapshot of 370 execution. One tYPical mix and subtracts when the stride is a constant.
the user's program at the source level. Th~
shows the following most frequently-executed Thus a multiply by 24 is implemented as:
most potent effects of an optimizin,g .c0m~ller
storage-to-register ops.
are derived from reducing the administrative
code used to implement high-level constructs.
shiftl(i, 4) + shiftl(i, 3)
Consider what it takes to implement the
If somewhere else in the program there is a
following code fragment in PL.8.
multiply of i by 8 or 16, one of the Shi~ts
already used to compute i*24 will suffice. By
1a static ext,
systematically exploiting the many small ,
2b integer,
opportunities for optimization that occur In
2 c (0:10),
real programs, the PL.8 compiler can produce
3d integer,
programs that execute very rapidly on the
3e integer,
ROMP.
3f char (16);
x = e(i);

78
It is now necessary to discuss register of instruction were available, implementing a While the ROMP does have some minor
allocation. So far we have tacitly assumed multiply by an arbitrary constant using shifts irregularities in its register scheme, it is a
that there would be enough registers to hold and adds would often require intermediate substantial improvement on our past
all the intermediate results which optimization copies. Rather than introduce a 4-byte architectures, resulting in few problems for an
creates. A large number of registers require, nondestructive shift instruction, the paired optimizing compiler whose goal is to retain
not only more hardware, but more bits in the shift was introduced. Every register has a many available quantities in registers.
instruction to name the particular register. twin whose name is obtained by
Compiler studies showed that, while 32 complementing the lOW bit of the name (e.g., Checking and Linkage
registers were beneficial, 16 were a the twin of R2 is R3 and vice versa). The PL.8 In recent years programming languages have
reasonable compromise. A PL.8-type compiler register allocator handles this in the following attempted to guard against programming
approach would probably not be very manner. The internal form of the program errors and raise the level of the source
effective with substantially fewer than 16 used by optimization has shifts with separate language. The ROMP instruction set supports
registers. The code would tend to look like target, source and shift count fields. Prior to both.
the memory-to-memory model of computation. register coloring an attempt is made to
The PL.8 compiler uses a graph coloring coalesce the source and target. If this fails, The trap instructions provide an economic
algorithm [3] to assign the infinite number of an attempt is made to coalesce the source method to test for unusual or erroneous
symbolic registers used during optimization to and target onto a particular pair of real conditions during execution. Pascal and PL.8
the 16 available on the ROM P, but other registers. Other cases, which seem to be both customarily run in production with
methods can be used. rare, result in an extra load register. checking enabled. However, it is possible to
eliminate these checks. By having separate
It is particularly important that a machine not On machines like the 370 there are a plethora checking ops and then optimizing code, the
restrict the register allocation by typing of problems associated with registers: compiler writer can ensure that the
registers or otherwise constraining their use. correctness criteria of a wide variety of
Implicit usage is also undesirable. Even the • The 370 really has fewer than 16 registers languages are efficiently enforced.
ROMP has some minor problems here, but because at least one must be reserved for
they are easily overcome. Register 0 cannot program addressability. The efficient implementation of a language
be used as a base because the CPU like C, in which primitives are coded as basic
assumes this means the value zero. The • The fact that integer multiply destroys a functions, clearly depends on linkage.
register allocation phase of the compiler pair of registers introduces complications. However, higher level languages which
overcomes this problem by introducing an implement data abstractions also depend on
interference in the coloring graph. Each • The PL.8 compiler has never really the subroutine mechanisms. In implementing
symbolic register used as a base interferes exploited 370 instructions that use register procedure call, the ROMP convention is to
with real register zero; thus, the compiler will pairs such as the loop closing BXLE op and load the first four parameters into registers.
not assign such a symbolic register to RO. double length shifts. (We are not alone in The invoked procedure may then use them in
Branch and Link implicitly uses R15. This was not using BXLE. It has a frequency of less place or copy them into other registers. The
chosen by the compiler writers to match the than .01 % on most execution samples.) important point is that they seldom need to be
proposed linkage conventions. The most copied into storage, an expensive operation.
bothersome constraint is paired shifts. Normal • The fact that some arithmetic and logical Longer parameter lists must be put in
shifts on the ROMP are of the form: instructions work on less than a full word is storage, but these are relatively infrequent.
a constant problem. It takes a lot of special This strategy is much more efficient than the
Shift RA, shift amount analysis to decide when a short op can be traditional 370 or UNIX type linkage, which
used. passes parameters in storage. When invoking
The value to be shifted is in RA and is a procedure, it is not normally necessary to
returned to the same register. If only this form load its address. System routines such as

79
multiply or the primitive storage allocator are /*move to a byte of zeros. */ tend to have a very expensive multiplier. Low-
kept in low memory and the 24-bit absolute move (t, s) end machines implement the multiply
branch can be used to access them. Relative char *t, *s; instruction with a microcode operator that is
branching within a bound module, which is as the functional equivalent of the ROMP
large as a megabyte, is also possible with a while (*t+ + *s + +); Multiply Step instruction. It is hard to see how
single instruction. On entry to a procedure it return; the ROMP solution results in significantly
is merely necessary to do a Store Multiple to worse performance. Sometimes there may be
save any registers that will be used and bump Object Code for ROMP better performance. Constant multiplies can
the stack pointer. Stack overflow is normally 2: 000000 PDEF
be done with adds and shifts. Some
caught by an attempt to reference a protected 5: 000000
5: 000000 Les 4003
1.6:
LCS rO, $MEMORY+*s (r~;) applications may not require a full 32-bit
page. (For procedures with large stack frames 5: 000002 INC
5: 000004 INC
9131
9121
INC
INC
r3,r3,1
r2,r2,1 multiply. If the multiplier is only 12 bits long,
an explicit check is made.) Exit from a 5: 000006 CIS
5: 000008 BNBX
9400
89AF FFFC
CIS
BFX
cr-,rO!!,O
cr,b26/eq,%6 then it is possible to get a product with six
5: OOOOOC STC
procedure consists of loading the return value 7: 000010 BNBR
DE02 FFFF
E88F
STC
BFR
rO, $MEMORY+H-1 (r2)
24,r-15 rather than 16 multiply step instructions. Once
in a register, restoring the saved registers again the basic instruction set permits the
and executing a branch register. Figure 1 Example user or compiler writer to do exactly what he
wants with great efficiency rather than
In practice, there are many variations on this multiply, divide and storage-to-storage move. depending on the foresight of some computer
theme, depending on the language, system On 370 instruction traces, move constitutes architects. (Those of us who participated in
conventions, and the user's program. For about 2% of all executions, making it, by far, the development of the ROMP architecture
example, in Figure 1 we see the object code the most important complex instruction. It are constantly grateful that we did not
for a function that performs the typical C tends to consume close to 10% of the enshrine our more exotic requirements in
storage-to-storage move. Because it is able execution time. On large 370 machines 2 silicon.)
to work entirely out of registers that are, by bytes are moved per cycle. (A cycle is taken
convention, not saved over a call, it has no to mean the time for a minimum op such as a One of the sadder sequences of code is to
prologue and an epilogue that consists of a register add.) For aligned moves, the ROMP see a divide by two in a binary search or
branch register. As source programs and can achieve close to this rate by means of an heap sort implemented with a divide rather
languages become more complex, procedure "unrolled" loop. For unaligned moves, a than a shift instruction. Even on high-
call overhead \A'/i!! increase, but the compiler carefully handcrafted subroutine has been performance machines, divide can take
writer can always choose the minimum code written. It uses ops which are of otherwise almost ten times a shift. That is a big loss of
sequence for the task at hand. One marginal utility, such as MCxx. There are performance in a loop that is likely to be very
interesting consequence of the MMU relocate even some compensations for not having the important. This doesn't occur because
is that, given inverted page tables, many 370 MVC op. The ROMP move subroutine compiler writers are unaware that a right shift
systems will want to allocate a very large has been tailored to make moves of can sometimes replace a divide by a power of
contiguous stack when a process is created. overlapped data nondestructive, thus two. The problem is negative numbers as
There is no reason to maintain the stack in satisfying the PL.8 rule. Once again we note dividends. ( - 1)/2 is 0 on 370. - 1 shifted
disjoint sections, as the mere existence of that high-level instructions never quite do right one bit is still - 1. The substitution of a
address space does not degrade performance what they are supposed to do, but lOW-level shift for a divide only works for positive
as is the case with conventional page tables. ops can be specialized to the specific dividends. For the PL.8 language we decided
requirements. to implement a true twos complement divide
High-Level Functions subroutine using the Euclidean algorithm that
High-level functions on the ROMP are The various versions of multiply on 370 rounds down rather than toward O. Thus
implemented with subroutines rather than constitute about .1 % of all instructions replacing divides with shifts gives the same
microcode. The most obvious examples are executed. High-performance 370 machines result. In this case a lOW-level instruction set

80
gave us a new view of source language of the time. Most of the above have direct average length of a ROMP instruction varies
semantics. We simply implemented the divide counterparts in the ROMP instruction set. from application to application, but is usually
subroutine that we wanted rather than Other than move, it is hard to think of any well under 3 bytes. In some cases, the ROMP
accepting built-in semantics. 370 instruction which might have improved does require an added instruction but it is
ROMP performance if it had been relatively infrequent and an easy decision for
The ROMP does have Load and Store implemented. the compiler.
Multiple ops. It would be possible to get along
without them. However, this is one case Code Size and Path Length Details
where a high-level instruction improves The 801 minicomputer was designed to have A number of small details contribute to
performance. This is because they permit the the shortest possible path length, and code making the ROMP a good target for
CPU to send one address to the memory size was sacrificed to achieve this. This is compilers.
subsystem and then do a series of Loads or highly appropriate on a machine with a cache.
Stores without the interference of fetching a In a machine with a storage hierarchy, most • Condition codes tend to be an awkward
series of instructions and sending effective of the faults come from referencing data. match for many systematic methods of
addresses to the memory subsystem. Doubling the size of the code only marginally compilation. In the ROMP, those
increases the number of faults. However, the instructions that set the relational bits of the
The ROMP approach to implementing high- ROMP does not have a cache. In order to condition register set them in the same way
level function frees the compiler writer and multiplex the 32-bit memory channel with as a compare with zero. This permits the
user from the tyranny of instruction sets instructions and data, it helps to have short compiler to eliminate al\ compares with zero
without giving up any significant performance. instructions. that are preceded by an instruction that
Furthermore, the engineer can concentrate on sets the same register as the register
making Load, Store and Branch run wei\. For this reason the ROMP has short forms of comparand. It is also important to not set
Here is the frequency of execution of the top many commonly occurring full-function the condition register on Load, Store, or the
ten instructions in a typical snapshot of 370 instructions. In addition, a compromise was basic Adds that compute addresseS:. This
execution. made such that, of the register-to-register permits code to be inserted, or rearranged
operations, only CAS, the form of add that without worrying about the conditio~
% of does not set the condition register, is fully register. The condition register test bit
Instruction Executions three-address. Shifts have the paired form provides an efficient means to move and
while subtract and the logical ops destroy one compare arbitrary bits even when their
BC:Branch Condition 20.2
operand. This is a compromise. Add occurs position in a word must be computed at run
L:Load 15.5
so frequently that a 16-bit, three-address time. This makes it very efficient to
TM:Test Under Mask 6.1
format has a big benefit. There are not implement packed arrays of bits and
ST:Store 5.9
enough code pOints to have all the other RR Pascal-type sets.
LR: Load Register 4.7
instructions in 16-bit, nondestructive format.
LA:Load Address 4.0
Because the register allocator was able to • Load instructions that fetch bytes and half-
LTR:Test Register 3.8
coalesce operands most of the time, a 16-bit, words from storage either set the
BCR:Branch Register 2.9
two-operand format was chosen for the other remainder of the register to zero or fill it
MVC:Move Characters 2.1
RR ops. Similar reasoning led us to have with sign bits. This makes it easier to treat
LH:Load Half Word 1.8
short-form increment and decrement partial words as algebraic or logical
instructions. quantities. On 370 one of the most common
Together these constitute 67% of all
instructions executed. Clearly the vast idioms is a subtract of a register from itself
All in all, the ROMP is surprisingly space followed by an insert character. LC does
majority of the over two hundred 370
efficient without undue performance loss. The the entire job on the ROMP.
instructions occur a good deal less than 1%

81
• The Load and Store Multiple instructions Conclusion are much less powerful than an alphabet of
can be used to do block moves or zero The ROMP architecture provides the high- twenty-odd characters. Fast, primitive
large areas in an efficient manner. level language compiler writer with the right operations will be required to efficiently
set of implementation primitives. Its strength implement the high level languages of the
• Sometimes constant data will not fit into the is the ability to combine the basic operations future.
ROMP 16-bit immediate field. Instructions in new ways suited to the task at hand. In
are provided that treat the immediate field Figure 1 we have an example of how a References
as a left-justified quantity. It is thus possible common idiom in C is efficiently implemented. 1. M. Auslander and M.E. Hopkins, "An Overview of the
PL.8 compiler," Proc. of the Sigplan '82 Symposium
to follow either of two strategies. Use two It is hard to see how the most specialized
on Compiler Writing, Boston, MA, June 23-25, 1982.
ops if either the upper or lower form is instruction could improve very much on this.
2. George Radin, "The 801 Minicomputer," Proc. of
insufficient. The alternative is to After all, there will have to be a fetch and Symposium on Architectural Support for Programming
manufacture the constant in a register, store, as well as a test and bumps for each Languages and Operating Systems, Palo Alto,
which requires two instructions, but then character moved. A high-level instruction California, March 1-3, 1982.
the constant may be reused many times by would be further complicated by 3. Gregory J. Chaitin, Marc A. Auslander, Ashok K.
short, fast RR ops. considerations of crossing page boundaries, Chandra, John Cocke, Martin E. Hopkins, and Peter
running too long, etc. If we build in this W. Markstein, "Register Allocation via Coloring,"
Computer Languages, Vol 6, No 1,1981,47-57.
Other Methodologies instruction we are tailoring the machine to C;
Not all source languages will be implemented other languages such as Pascal, ADA,
with optimizing compilers like PL.8. FORTRAN and COBOL that do not share the
C convention that character strings are
Where high-quality object code is not crucial it terminated with a zero, will find the op
may pay to have a very fast compiler that useless. However, even C may not find this
produces mediocre object code. A number of the best strategy for character movement all
features make this a reasonably easy task. the time. Large buffers should not be moved
Even code from a very naive compiler is quite 1 byte at a time. Then there are other idioms
compact. The large number of general- in C, for searching tables, scanning input
purpose registers means it is easy to reuse forward and backward, looking for other
vaiues over shon stretches. The iarge characters and an infinite number of other
displacement means one can reserve large tasks. Is each of these to be a special op?
areas for intermediate results without fearing Will the compiler have to look for complicated
overflow. High-level function can be invoked patterns trying to match a complex function to
via subroutines with a reasonable in-line a complex instruction? The ROMP permits the
overhead. Finally, code can be addressed and compiler writer to combine primitives to
constants can always be manufactured on- efficiently solve the particular problem at hand
the-fly without establishing or maintaining for a wide variety of source languages.
addressability to code segments and a literal
pool as is required on 370. As the programming community moves
toward languages that are more powerful
Another method of implementation is than C it becomes even more urgent to rely
interpretation. The ROMP is a very good on basic constructs. Only the simplest
interpreter. This should not surprise us as it languages can be based on complex, high-
is really a general-purpose micro engine. level messages. Thousands of hieroglyphics

82
Advanced Interactive Executive (AIXTM) Operating System Structure

Larry Loucks

Introduction incorporated into the Advanced Interactive adopted a policy of continuous performance
When we set out to design the IBM RT PC Executive (AIX) an application development assessment of the operating system, starting
system, we realized that the RT PC needed a environment suitable for many existing higher with the earliest availability of hardware and
full-function operating system with the ability level language programs, as well as the ability software. The performance group had to
to support continuously-running applications. to process most PC DOS commands and develop new tools and procedures to assess
In the increasingly interconnected world of data. the performance of the system while it was
advanced microcomputers, it is no longer still immature, but the results of that effort are
acceptable to dedicate the computer to a The AIX operating system kernel was derived visible in the performance of the completed
single application. There must always be an from AT&T's UNIX System V. In light of our product.
operating system presence to respond to requirements for application diversity,
external requests. operating system stability, and exploitation of Although the VRM and the AIX kernel have
the RT PC's advanced hardware features, we been "tuned" for each other, we have not
Obviously, an architect who sets out to build felt that the best approach was to provide precluded the ability to run other operating
a "disciplined" environment, also takes on enhancements below, within, and above the systems in the VRM virtual machines.
the responsibility for making that environment karnaL This lad to the software structure Similar!y, the techniques we used to virtualize
functionally complete and flexible enough to shown in Figure 1. The Virtual Resource existing types of devices would work for new
satisfy the full range of applications. We took Manager (VRM) [1] controls the real hardware device types as well. Both the VRM and the
a three-level approach to the problem: make and provides a stable, high-level machine kernel are deliberately open-ended, to allow
the built-in functions powerful enough to interface to the advanced hardware features the straightforward addition of new functions
satisfy most applications, provide controlled and devices. The kernel received and device support.
access to the hardware interfaces for corresponding enhancements to use the
occasions when the built-in functions aren't services of the VRM and to provide essential Creating the Right Environment for the AIX
sufficient, and make the operating system additional facilities. The application Kernel
open-ended enough to allow for extensions to development extensions above the kernel The existing structure of the AIX kernel was
cover situations such as new types of were integrated into the existing operating not well suited to exploiting the advanced
devices. system structure. In some cases, the features of the RT PC hardware. Rather than
extensions were packaged and priced making major changes to the architecture of
We wanted to give users the widest possible separately, but they are designed to operate the kernel, we built the VRM to provide a
choice of applications to run on the RT PC, as integral parts of the operating system after more comprehensive real-time execution
so we provided ways of moving applications they have been installed. environment (see Lang, et al.[1 ]). This
from the IBM Personal Computer, other UNIX environment includes multiple preemptable
environments, and IBM mainframes into the Because we were dealing with a new processes, process creation and priority
RT PC environment. At the same time, we hardware architecture and with large control, dynamiC run-time binding of code,
wanted to give those applications the quantities of new and modified software in direct control of virtual memory, millisecond-
maximum possible benefit from the the system, we felt that special efforts were level timer control, multiple preemptable
capabilities of the advanced hardware, so we required to ensure excellent performance. We interrupt levels, and an efficient interprocess

83
 S The VRM provides the operating system with
Application Program(s) E
R an extensive, queued or synchronous
Communications Usability V
I
interface to the I/O devices, insulating the
Data Management SQL/RT Data Base
C kernel from the details of specific devices and
Enhanced Terminal Support Command Processing E the management of shared devices. The
S
correct device handler is selected on the
(Kernel Interface) K
1--- - - - - - - .,...----- - - - basis of the currently-installed hardware or
Enhanced: Local Terminal Support - G;neric Dev-;e Dri~r;- - E
Virtual Storage R
A the configuration files and is dynamically
I
File System N bound into the VRM. The devices that the
E X
Config.uration
L application sees are generic devices such as
generalized fixed-disk drives ("mini-disks") or
(Virtual Machine Interface) RS232C ports. In those cases where the
1--- - - - - - - --r---- - -- ---.--- - - r----- V generic devices are not appropriate, or where
Virtual I/O Minidisk Virtual Communications Coprocessor
Memory Device
R the real time capabilities of the VRM
Manager Terminal Services
Manager Manager
M
Manager
environment are needed by the application,
RT PC Hardware the user or a third-party programmer can
write C or Assembler language code to
Figure 1 Overall Structure of AIX Operating System implement the necessary function, and can
dynamically add that code to the VRM while
communication mechanism for main and high-function terminal to obtain controlled the VRM is running (i.e., without re-IPL).
interrupt-level processes. The VRM scjware access to all of the functions of the real
uses these features to control the ROMP display. Most of the basic operating system Problem determination in system or user-
processor, Memory Management Unit (MMU), functions - kernel, command processing, added code is supported by VRM
and I/O hardware, and provides the kernel and usability - make use of the simulated serviceability facilities that include trace
with interfaces to these functions. ASCII terminal, so that their functions are capabilities, dumps, and a debugger.
available on real ASCII terminals as well.
The key to the ability of A!X to support The VRM supports the PC AT coprocessor
muitiple simultaneous interactive appiications The ROMP/MMU virtual memory architecture, option as though it were another, rather
is the virtual terminal (see Baker, et al.[2]). A in combination with the VRM, gives the RT speciaiized, virtual machine (see Krishnamurty
virtual terminal is a virtual counterpart of the PC a demand-paged virtual memory of one and Mothersole[4]). The coprocessor runs
real RT PC display(s), keyboard, and mouse. terabyte, consisting of 4096 256-megabyte concurrently with the execution of programs
Each application initially gets a single virtual segments. The VRM performs page fault in the ROMP, but it only has access to the
terminal to work with. The application can handling and manages the allocation of real keyboard, locator, and display when the
request creation of additional virtual terminals memory, paging space, and virtual storage coprocessor virtual terminal is the "active"
at will. The virtual terminals time share the segments (see O'Quin, et al.[3]). It provides virtual terminal, that is, when it has control of
use of the real displays and input devices. A the AIX kernel with interfaces to control these the display. The input from the keyboard and
virtual terminal can function as either a functions and to respond to a page fault by locator are presented to the coprocessor as
simulated ASCII terminal or a high-function dispatching another process. The VRM can though they had been produced by the
terminal equivalent in power to the real also map memory pages within a given corresponding PC AT devices. If no display
hardware. The simulated ASCII terminal segment onto disk file blocks, creating a has been dedicated to the coprocessor, the
resembles a typical "glass TTY," enhanced "single-level store" that makes DASD and display interface emulates a PC display on
with functions to control sound, multiple fonts, memory equivalent. the system display. The VRM manages the
and color. Advanced applications can use the shared system resources to ensure that the

84
ROMP and coprocessor operate system, unique sets of utility commands to be Because we expected RT PC's to be used
cooperatively. learned, and a general increase in the both as single-user workstations and as
complexity of the system. We wanted to traditional UNIX time-shared systems, we felt
The VRM resides on a minidisk of its own in provide an integrated environment, so the that some changes were required to support
a standard AIX file system. Installation and kernel file system services were extended to the workstation user. We have made some
space management on that minidisk are provide the necessary facilities to allow us to alterations to reduce the number of situations
performed with standard AIX utilities. add data management and relational data in which user has to exercise superuser
base support that is built on top of the file authority. We added the ability to define more
Building a Firm AIX Base system (see Bissell[6]). The enhancements than one group to which a user belongs at
The structure of the AIX kernel has been included the ability to perform space any given time. This allowed us to define
modified to allow it to operate in a VRM management within a file, buffer cache single users as members of the "system"
execution environment (see Loucks [5]). New synchronization on a file basis, and file and group. System group members can perform a
device drivers for devices such as disk, record-level locking. number of operations that previously could
diskette, tape, and asynch were written to use only be performed by superuser. Only the
the device interfaces of the VRM. The device- The complex multi-process applications that most hazardous commands are still restricted
driver interfaces have been extended to allow we envisioned being run on the RT PC to superuser authority. This technique gives
dynamic binding of a driver to a VRM driver. required more robust interprocess control the user of a private workstation a simpler
facilities, so the signal (asynchronous event environment to work in, while preserving the
The kernel has been enhanced to use the notification) package has been superceded by existing AIX authority structure for multiuser
VRM virtual memory services. The kernel now a new package that provides for more signals environments.
provides a demand-paged virtual memory and cures a number of race conditions that
system that fully supports the 1024-gigabyte were inherent in the original package. The Configuring a UNIX system has historically
address space. The kernel occupies one (256- standard Signa! package remains available for required an understanding of the internal
megabyte) segment. Each process is compatibility with existing application structure and logic<of UNIX. We felt that it
allocated three segments: one for program programs. was unrealistic to impose such a requirement
text, one for data, and one for the stack. on our prospective users, so we set out to
Additional segments can be obtained for use The local terminal (displays, keyboard, and simplify the installation and configuration
with private or shared data, or for mapped mouse) now has two modes. To allow processes (see Lerom et al.[7]). For those
files. The VRM map page service is used at existing applications to run unchanged and devices that can be identified internally, such
run time to dynamically map the program text new character-oriented applications to use as displays, the system performs an
and initialized data, as well as to provide the the RT PC facilities fully, we extended the automatic configuration process. For devices
application with the ability to map a user file ASCII character-oriented terminal model via that require explicit description, such as
into a virtual memory segment. This provides private escape codes in the data stream and printers, we built a menu interface that
the effect of a "single-level store." The kernel a new set of 10CTLs to access features such obtains the necessary information from the
uses VRM page fault information to control as fonts, character sets, color, sound, and user and makes the required coordinated
process dispatching, as well as allowing the mouse input. For applications that need the changes to all of the affected VRM and AIX
kernel itself to be paged. APA capabilities of the displays, or more system files. These menus use the same
direct communication with the keyboard and VRM facilities that were provided to allow
Historically, UNIX-based data base programs mouse, we developed a new mode for the users to add device and real-time application
have used only the low-level disk 1/0 services terminal driver that makes the full capabilities support. The interfaces to this menu structure
of the kernel because the standard UNIX file of the console hardware available in a have been documented so that users or third-
system lacked several key features necessary controlled manner. The application selects the party programmers can add devices to be
to support them. This resulted in data base mode in which it will use the virtual terminal. selected and described via the menus.
programs that were not integrated with the

85
UNIX has a dual-purpose command language. The higher level language compilers for the the dialog manager a high-level, device-
The commands have been designed from the RT PC were chosen on the basis of the independent interface on which to build.
beginning to be primitives of a command number and types of programs that have
procedure programming language, sometimes been written in those languages. We selected Programmers developing applications for the
at the expense of ease of use when individual dialects that would facilitate propagation of local terminal can have the full power of the
commands are submitted from the terminal. programs from the IBM Personal Computer, RT PC APA displays available to them.
This makes the management of files and the other IBM mainframes, and other UNIX
performance of common operations systems, with language extensions where As a base for lAN-based applications, we
unnecessarily complex. Many UNIX necessary to support the AIX environment. In included a set of primitives to support the PC
installations solve this problem by building some cases the compilers have two modes Network.
sets of procedures that effectively constitute - one for programs from the PC, and one
a command meta-language. We chose to for programs from minicomputer or Conclusion - A Good Beginning
combine the solution to this problem with the mainframe environments. We developed a In its Release 1 form, the RT PC software can
construction of a full-screen interface to AIX new subroutine linkage convention (see be installed and used for production work
(see Kilpatrick and Greene[8]). The usability O'Quin[10]) that supports multi-module without a large investment in learning the
package provides a full-screen file programs written in several languages. internals of AIX or the peculiarities of a new
management utility and the ability to request command language. It is a base to which
the most common AIX commands via a panel AIX also includes a new shell that processes existing applications can be moved and on
interface. The dialog manager that is included PC DOS commands, conversion programs which new applications can be built. Perhaps
in the usability package is general enough to that transform data from PC to RT PC format, more important, AIX and the VRM provide a
serve application programs as well as AIX and subroutines that allow applications -to system that has been architected to be
commands (see Murphy and Verburg[9]). read DOS-formatted diskettes and minidisks extendable.
(see Brissette, et al.[11 ]).
To simplify the diagnosis of problems in AIX From the beginning of the project, we have
we added several debugging tools: a trace The Files and Tools applications of the known that we could not include in Release 1
mechanism, logging of errors and system usability package can be extended to cover all of the functions we wanted, and that users
messages, and a memory dump capability. new types of files, new actions that can be and other developers would have needs that
performed against those files can be defined, \"/9 did not anticipate. The open-ended ness of
Enhanced Application Development and new tools - including complete full- the system results from our awareness of the
Environment screen applications - can be added. The limitations of prediction.
To be able to support the full range of dialog manager in the Usability package can
modern applications, AIX needed several also be used to provide new full-screen Clearly, we still need to look at the function of
functional extensions. One of the most critical applications with an interface that is the system in several areas. We are not yet
was the need for an indexed access method. consistent with the interface presented by satisfied with the communications capabilities
We added a B-tree based data management Files and Tools. of AIX and its ability to function in a
program that permits either record-level or distributed environment. There are aspects of
field-level access. Although it is packaged The "LlBCUR" package, which supports the compiler technology that could make more
separately from the operating system, data presentation of full-screen menus on ASYNC effective use of the capabilities of the ROMP.
management becomes an integral part of the terminals, has received performance Additional opportunities will undoubtedly arise
file system when it is installed. Similarly, we enhancements and has been compatibly as more people use the system.
added a data base program supporting the extended to provide access to the extended
Structured Query language (SQl) to provide font and other functions of the RT PC native
both users and application programmers with displays. We also added functions such as
relational data base facilities. screen division and "layering" logic to give

86
References
1. Thomas G. Lang, Mark S. Greenberg, and Charles H.
Sauer, "The Virtual Resource Manager," IBM RT
Personal Computer Technology, p. 119.
2. D.C. Baker, G.A. Flurry, and K.D. Nguyen,
"Implementation of a Virtual Terminal Subsystem,"
IBM RT Personal Computer Technology, p. 134.
3. J.C. O'Quin, J.T. O'Quin, Mark D. Rogers, T.A. Smith,
"Design of the IBM RT PC Virtual Memory Manager,"
IBM RT Personal Computer Technology, p. 126.
4. Rajan Krishnamurty and Terry Mothersole,
"Coprocessor Software Support," IBM RT Personal
Computer Technology, p. 142.
5. Larry Loucks, "IBM RT PC AIX Kernel -
Modifications and Extensions" IBM RT Personal
Computer Technology, p. 96.
6. John M. Bissell, "Extended File Management for AIX"
IBM RT Personal Computer Technology, p. 114.
7. Shirley Lerom, Lee Terrell, and Hira Advani,
"Configuration Methods for a Personal Computer
System," IBM RT Personal Computer Technology,
p.91.
8. P.J. Kilpatrick and Carolyn Greene, "Restructuring the
AIX User Interface," IBM RT Personal Computer
Technology, p. 88.
9. Tom Murphy and Dick Verburg, "Extendable High-
Level AIX User Interface," IBM RT Personal Computer
Technology, p. 116.
10. J.C. O'Quin, "The IBM RT PC Subroutine Linkage
Convention," IBM RT Personal Computer Technology,
p.131.
11. Leonard F. Brissette, Roy A. Clauson, and Jack E.
Olson, "PC DOS Emulation in a UNIX Environment,"
IBM RT Personal Computer Technology, p. 147.

87
Restructuring The AIX User Interface

P.J. Kilpatrick and Carolyn Greene

Introduction Naturally, we were exacerbating these • The ability of the RT PC system to run
When the UNIX kernel was adopted as the problems by porting UNIX to an environment multiple concurrent interactive sessions
core of the IBM RT PC operating system, our for which it was never intended: a workstation should be an inherent part of the user
User Interface Design Group received an supporting multiple virtual terminals for a interface.
interesting challenge. UNIX was designed as single user on an all-points-addressable
a powerful and flexible tool for computer display. Our objective was to preserve the In other words, we wanted to satisfy a user
science experimentation. To users for whom functional power of UNIX while presenting the set ranging from UNIX experts to novice
a computer is a means and not an end, user with a consistent and straightforward users. Rather than adopt a Procrustean, one-
however, the UNIX command language can terminal interface. size-fits-all solution, we chose to provide a
seem complex and unpredictable. The very family of several related user interfaces with
open-ended ness that has allowed the Ground Rules different objectives.
continual expansion of UNIX's functional Our user interface design was subject to a
power over the years, has resulted in a wide number of constraints, some architectural and Windows with Personalities
variety of syntaxes and semantic some practical. A virtual terminal running an application
characteristics. In a number of cases, too, the constitutes a "window" onto the output of
need to make a command useful in Shell • Users who wanted to use the RT PC to run that application. Our user interface currently
scripts as well as from the terminal has one or more specific applications should be provides five kinds of windows, each running
resulted in quirky responses to given an interface that would enable them its own specialized application.
unsophisticated terminal users. to install and configure the system and
applications, manage their files, and • The Windows window; shown in Figure 1, is
The UNIX user interface also shows its age, perform routine system functions without the operator's console. It is the first thing
in that it was originally designed for being exposed to the complexities of the displayed when the user logs on, and it is
typewriter-like terminals connected to a full command language. the base from which all new windows are
minicomputer via low-speed lines. Many of created. The Windows window contains a
the characteristics that detract from UNIX's • Except for the installation and configuration list of the kinds of windows that can be
usability today, such as extreme terseness of interface, all of the system user interfaces created, and a list of the windows that
command language, result from design had to be available to users in substantially already exist.
decisions intended to improve the the same form on the RT PC display and
performance of the early UNIX systems. on attached terminals. Applications, of • A Files window (see Murphy and
course, would operate only on those Verburg[1]) is a full-screen display of a
The process of installing and customizing a terminals capable of satisfying their directory in the user's file system. Selecting
UNIX system is also somewhat complex, functional requirements. a file causes the user to be presented with
requiring an understanding of UNIX internal the set of actions that can be performed on
structures and processing. • The user must be able to exploit the full that file.
command language when necessary.

88
; !)_~-~ S""" i. j,,,~,~ •.:..j.L
- - - - - -----~-WINDOWS---~~~----
J }~ ~
r----, help information, appear in pop-up panels
La<)t tPD~-E ,-"t 03.0£ I Console I
I I that overlay parts of the application area.
I
»~PPLICATIONS Run programs for SI><lCiflC jobs
I
»FILES Wot'k with yout' files Windows _...J When the user selects something in the
"TOOLS Select c.-ads Window
»"IX Type "IX COlI_Dds application area, the command bar displays
.. DOS Type DOS COMaDds
all of the commands (or sets of commands)
that are valid for use with that selection.
Some of the commands are very close to
specific command-language counterparts.
Others are generic commands that result in
Files,
Files,
Tools,
the invocation of different AIX commands
Tools,
or Shell or Shell depending on the type of object being
manipulated. The unifying principle is that the
Figure 1 A WINDOWS Window After Two Other user should see the system as consistent. It
Windows Have Been Created is the system programmer's problem to deal
with the underlying nonuniformities (see
• A Tools window is a hierarchically arranged Murphy and Verburg [1] for a more detailed
list of commands and application programs Files, description of the Files and Tools
that can be invoked via a panel rather than Tools, applications).
or Shell
a command-language interface.
We have not attempted to provide all of the
• An AIX Shell window is the equivalent of a Figure 2 The Ring of Windows commands via the usability interface. Instead,
single instance of the AIX Shel! running on we have supported the most common tasks
an ASYNC terminal. move directly to the desired window by in simplified ways. The Files and Tools
selecting it in the Windows window and application programs have deliberately been
• A DOS Shell window is identical to an AIX selecting the ACTIVATE command. left open-ended to allow us to support tasks
Shell window, except that it has been that we may have overlooked and to allow
preconditioned to submit commands to the The "Usability Package" Interface inclusion of new applications being added to
PC DOS compatibility interface of AIX. In architecting the full-screen user interface AIX.
for AIX, our objective was to increase the
After logon, the user can determine which productivity, self-confidence, and satisfaction Conclusions
interfaces are most appropriate to the tasks of the user. We also wanted the benefits of In attempting to simplify use of UNIX while
to be performed and then create several the new interface to extend to users of preserving its power, we have inevitably
windows of suitable types. The windows form terminals, not just to users of APA displays. created a family of user interfaces rather than
a ring, as shown in Figure 2. This precluded, perhaps fortunately, the use a single, unified interface. We believe,
of the cute techniques of some recent however, that we have provided a selection of
The user can move around the ring of products. We divided the screen into two tools that is appropriate to the diverse users
windows with the Alt-Action (forward) and areas: 1) the command bar at the top of the of RT PC.
Shift-Action (backward) key combinations. If screen, and the application area taking up the
the user has created a large number of remainder of the screen. All other types of Naturally, the user interface will evolve along
windows (up to the maximum of 28), he or information, such as panels requesting with the rest of the RT PC. We hope to see
she can go directly to the Windows window command parameters, error messages, and increased integration of applications with the
with the Ctrl-Action key combination and then usability package and with each other. We

89
also expect to correct some "rough edges"
that were detected late in the development
cycle, such as a rather ponderous procedure
for keeping a displayed directory
synchronized with changes to the directory
made by other terminals. We are convinced,
however, that the new interfaces represent a
substantial improvement over the existing
command language and provide a good base
for future development.

References
1. Tom Murphy and Dick Verburg, "Extendable High-
Level AIX User Interface," IBM RT Personal Computer
Technology, p. 110.

90
Configuration Methods for a Personal Computer System

Shirley Lerom, Lee Terrell, and Hira Advani

Introduction current and future device drivers, protocol device drivers, or build and install a new
RT PC AIX configuration is designed to procedures, and device managers. (See kernel. This is acceptable for large, mUlti-user
exploit the features of the AIX operating Figure 1.) systems with a full-time system operator or
system (see Loucks [1]) and the Virtual knowledgeable UNIX programmers, but in
Resource Manager (see Lang, et al.[2]) as A second design problem was to surface all sma" operations with no reliance on
well as overcome some traditional problems configuration information to the user in an mainframe systems, it may not be affordable
one encounters while building a typical UNIX accessible and modifiable format. What we to have a system operator to maintain and
system. wanted to achieve, where possible, were upgrade the system. Upgrading a system to
"table-driven" routines that could be support a new peripheral or software
One of the design objectives had to be ease- extended to cover future device drivers, package is particularly important, since it is
of-use. Configuration of a typical UNIX device managers, and/or protocol procedures such a common occurrence. In typical UNIX
system can be very complex and error prone in an integrated way, as though they had systems, it is also one of the more difficult
for a novice user. AIX configuration is easy to been part of the original configuration. tasks, since it involves rebuilding the kernel.
use, leads the user to supply all needed
information, and handles complex tasks Configuring in a Typical Pre-RT PC UNIX Process Steps: Building, Testing, Integrating,
without bothering the user with the details. Environment - The Problem New Kernels
The user is also warned of error situations. Device drivers in the UNIX kernel are the
The "Privileged-User" Philosophy funnels through which all Input/Output
Other design objectives covered in this article A typical UNIX system, with its multi-user, operations must pass. When reading a file,
are those of flexibility, availability and multi-tasking nature, has conceptually built-in the disk (or diskette) device drivers are
extendability. AIX configuration is flexible in certain large system philosophies. One usually involved. When printing a file, the
that it supports the open architecture of the philosophy involves a system administrator or printer device driver is used. When initiating
RT PC system. It is dynamic in that most system operator requirement. Merely an I/O operation to device 'x', the device 'x'
changes take effect immediately, as opposed browsing a UNIX System Manager's driver must be used. The device driver
to generating and then starting a new system. reference book reveals chapters of 'knows' how to deal with the specific device
It is available, since generally the system information containing recommended for which it was written. A device driver for
remains usable by logged in users during the procedures, guidelines, and mandatory steps device 'x' most likely will not work with device
configuration steps. Most important, AIX with which 'super' user should comply. In 'y'. Therefore, if the new printer you wish to
configuration is extendable to future fact, almost a" UNIX systems have a add is device 'y', in a classic UNIX system
peripherals and program products. superuser login id ('root' in many cases) for you must follow some or all of the following
the purpose of system maintenance. steps to install device 'y':
One of the critical design problems was to Programs often check the user id (uid) or
provide a structure that could be used effective user id of the person attempting to 1. Code and compile the new device 'y'
dynamically to link kernel device drivers to execute them to make sure the authority is device driver.
VRM device drivers by issuing system service that of superuser (or root). For example, only
calls (SVCs). The structure had to be defined root can 'mount' a file system, install new
in a generic sense so that it could handle
91
 r---------,
I /etc/ddif... I and the kernel routines necessary to write a
_J device driver. This is seemed to us to be a
AIX
configuration /etc/system great deal of work for an ordinary user who
files simply wanted to add a printer. We tried to
overcome such limitations in the AIX
Define code (protocol proc.)
- Define_device (stanza name) configuration design.

/etc/vrmconfig Overall Configuration Scheme

Our goals for the configuration mechanism
Kernel were:
interface

1 Ease of Use A need existed for a simple

I user interface to configure the
peripheral devices. The user is
assumed only to know
Kernel characteristics of the peripheral
Kernel configuration
device rc---- device device, not about AIX. In the
driver driver most simple form, all the user
(fdev /config)
needs to know is the class and
type of peripheral device and
Virtual
machine the adapter port to which the
interface device is to be connected.

Usability The user interface to the

____ {Define_device (IODN) configuration routines needs to
Define_code (IOCN)
guide the user through the
VRM
device information in a 'leading

ylL.,__ d_riv_e_r_ .....

prompt' fashion. It is essential
that the user not need to know
in advance what to do. Device
Hardware configuration profiles should be
interface ..
initialized to their nominal state
Figure 1 AIX Configuration Interface Structure
to minimize the need for user
intervention.
2. Archive the driver in the library 6. Repeat steps 1 - 5 as necessary till
Flexibility While keeping the design
appropriate to your system. device works satisfactorily.
simple and easy to use, it was
important to preserve the
3. Modify the appropriate configuration files. 7. Replace the current kernel with the new
power and dynamic capabilities
debugged version.
of AIX. That is, when the
4. Build a new kernel (to include the driver).
configuration is completed, the
The above steps, while not specific to any
device should immediately be
5. Boot the new (test) kernel and debug the system, do reflect a general flow and are non-
available to the user. This
new device 'y' driver. trivial even if one assumes a working
dynamic re-configuration is
knowledge of the C programming language

92
 essential in a multi-user drivers. Unique characteristics of the user has simply to plug in a second fixed
system. multitude of hardware adapter cards are kept disk, for example, and it is ready to use. This
in configuration files. is because the diagnostic program will sense
Availability The configuration operations, the presence of the new fixed disk and install
when possible, should not Modification of Basic UNIX Concepts a VRM device driver to handle it. Second, the
make the system unusable by portion of the AIX operating system running
the other logged-in users. Architecture of the VRM at the VMI installs VRM device drivers for all
Because of its architected Virtual Machine 'non-core' devices (e.g., printers, plotters).
Extendability Equally important, the design Interface (VMI), the VRM maintains a constant
must not be obsoleted by new calling interface for the kernel device drivers Generic VRM Device Drivers
technology, devices or program (KDD). Since the kernel device drivers no The VRM device drivers in RT PC are written
products. The design is such longer deal directly with the hardware, the so as to be table driven. Information in a
that all configuration drivers are not as susceptible to changes in Define_Device Structure (DDS) is created at
information is maintained in the hardware. As a result, the kernel device system startup and contains characteristics
English text files. Critical driver for the printer (for example) does not for the driver to use. A single VRM device
information is not buried within have to be rewritten or even modified when a driver is therefore capable of interfacing to
software, but rather in user- new hardware adapter card (attachment multiple hardware adapters.
readable files. As new devices mechanism) is available. Any differences in
become available, these files new versus old hardware are contained in the Kernel Driver Initialization Routines
are updated or new files VRM device driver. This brings us to a A further improvement is the addition of an
created to reflect the second improvement. initialization routine to each of the kernel
characteristics of these device drivers. Many kernel device drivers
devices. This technique is Instal/able Device Drivers have most of the following routines:
used, for example, by program The VRM allows for device drivers to be
products to add device installed using calls at the VMI in a run-time • Open routine
support. (dynamic) environment. Specifically the • Close routine
Define_Code Service Call (SVC) and the • Read routine
Adaptation of the Goals to RT PC AIX Define_Device SVC provide a means for • Write routine
These goals would not have been attainable device drivers to be installed in the VRM. • loctl routine.
in a UNIX-only environment. The re- When installed, the driver is assigned an 110
configurability of the VRM was critical to Device Number (IODN) which is a 'tag' for An additional routine was added to AIX kernel
adding and deleting devices dynamically. interacting with the driver. drivers to set up (configure) key parameters.
Included in the parameters passed to the
The architecture of the Virtual Machine VRM device drivers can be installed in two KDD are:
Interface (VMI) was also key to reducing the ways. First, there is a set of device drivers
number and complexity of the kernel device known as 'core' or 'nucleus' devices that are • 10DN, a 'tag' for interfacing with the
drivers. By providing a constant interface at installed at VRM Initial Program Load (IPL) corresponding VRM driver
the VM I, a single kernel device driver is time. These devices are installed by hardware
capable of handling all printers regardless 0" diagnostic programs that run during each IPL. • Virtual Interrupt Level
the hardware attachment mechanism. If the diagnostic program determines that the
'core' device is actually present in the RT PC • KDD unique information (optional).
Externalizing the configuration information system, it installs the VRM device driver for
into files was important in reducing the that device. This is true for fixed disks, By way of this initialization routine, the KDD is
number and complexity of the VRM device diskettes, displays, and the tape devices. A informed which VRM device driver to use.

93
The printer KDD, for example, will attach and in the system. It issues the Configuration A significant enhancement of
communicate with one of two VDD's Define_Code and Define_Device API the RT PC system is the
depending on the type of printer in use - VMI SVC's and initializes the inclusion of library routines
parallel or serial. kernel device drivers. that provide interfaces to
manipulate the configuration
File Driven Configuration devices The 'devices' command is the files. These application
Another key improvement in the AIX design is software program that programs are used as a
that all key characteristic information about provides the user interface to common mechanism for
the peripherals and hardware adapters is the configuration files. These updating/modifying the
contained in configuration files of English text. files contain all information configuraion files by the
More specifically, all information contained in about peripheral devices and 'devices', 'minidisks', and
the Define_Device Structure (DDS) for the the hardware adapter cards to 'installp' programs. Likewise,
VRM device driver as well as associated which these devices attach. user-written routines could be
information for the kernel device driver (KDD) Additional information in these linked to these programs (in
resides in files in the '/etc' directory on the configuration files controls the librts.a) to deal with the
root file system. flow and logic of the devices configuration files.
command itself. This control
Open-endedness of Adding Peripherals information is used to present Summary
The RT PC product supports a wide latitude the user with the minimum RT PC system configuration offers the user
of capability in adding peripherals. The cases number of information an interface that manages the complex, file-
for consideration are listed below in an requests necessary to describe driven elements and functions of the system
ascending order of difficulty. the device being added. and ensures that file interaction is complete
and error free. In most cases, this eliminates
1. Adding an IBM Base Operating System minidisks The 'minidisks' program is the the need for a system administrator with a
(BOS) Device user interface for partitioning special set of technical skills to do
the fixed disk into AIX file configuration.
2. Adding IBM Licensed Program Product systems.
(LPP) Devices RT PC configuration is a dynamic program
installp The 'installp' function provides that can be used during run time to alter the
3. Adding OEM Printers and Plotters ease of installation of new system to user needs at a specific moment in
program products. If the time. Much of the underlying complexity is
4. Adding Similar (to IBM) Devices program product contains transparent to the user. Flexibility is derived
support for a new device(s), from the generic VRM device drivers that
5. Adding New Device Drivers the configuration files are also handle a multitude of hardware adapter cards.
updated. The AIX kernel is
Configuration Routines New to the Product conditionally re-built (if a new Configuration is also extendable. Licensed
There are several new AIX functions kernel device driver is part of Program Products (LPPs) offered by IBM will
introduced with the RT PC system. the program product). In many automatically use the configuration function to
cases the installp program add software and hardware to the system.
vrmconfig Vrmconfig is the software completely handles the These programs and procedures are not
routine responsible for reading installation of new software as limited to IBM. Third-party programmers may
information in the configuration well as readying new devices likewise use the AIX open system architecture
files to define and initialize the for operation. to develop and install programs on the RT PC
VRM and kernel device drivers product. Any future peripheral or program

94
product can likewise use the configuration
programs and APls to present new software
or hardware to the system. If software and
hardware have been added using AIX
configuration programs, they will appear as
an integrated part of the AIX system.

Acknowledgments
Our thanks go to the entire configuration
department for their dedicated team effort -
for the technical leadership provided by
Nancy Springen during the architecture phase
and by Grover Neuman in all subsequent
phases and redirections; to Liz Hughes for
assuming many key configuration routines
and the complex VRM configuration
component, to Terry Bouknecht for her work
on DEVICES, to Lynne McCue for her work in
MINIDISKS, to Carolyn Brady for later
enhancing and maintaining configuration
components, to Emily Havel for her work
controlling the files, and finally to Sylvia
Staves, who tested to ensure that our quality
goals were met.

References
1. Larry Loucks, "Advanced Interactive Executive (AIX)
Operating System Structure," IBM RT Personal
Computer Technology, p. 83.
2. Thomas G. Lang, Mark S. Greenberg, and Charles H.
Sauer, "The Virtual Resource Manager," IBM RT
Personal Computer Technology, p. 119.

95
IBM RT PC AIX Kernel - Modifications and Extensions

Larry Loucks

Introduction to be automatically logged on at the system logs onto the system, the setgroup system
At the heart of the Advanced Interactive console when AIX is IPLed, without having to call is used to specify to the kernel all of the
Executive (AIX) operating system is the AIX enter a login name or a password. This groups of which the user is a member. When
kernel. The kernel provides the operating facility is intended for those users who are the user attempts to access a file, the
environment for application programs and using AIX as a single-user system or for standard permission checks based on the
commands. The structure of the AIX kernel those users who are the only ones to logon user's 10 are made for read, write, and
reflects our response to several key at the system console. The user to be logged execute/search. If the user would not
objectives of the RT PC program: on automatically is identified to the system normally be granted access to the file on that
when it is being installed. basis, the user's group access permissions
• A primary use of the RT PC was expected are checked. If the user is a member of the
to be as a personal workstation, rather than When Auto Logon is in effect, powering the group that owns the file, access to the file is
as a host for a multi-user configuration. system on is all that is necessary to cause granted.
the user to be logged on at the system
• We had to ensure that the performance console. Auto Logon is performed when the No overt actions have to be taken by the user
potential of the ROMP/MMU combination file /etc/autolog contains the name of a valid to enable the Multiple Concurrent Group
was not lost in performance bottlenecks. login name as its first or only entry. This facility. It is a part of standard AIX operation.
causes the system to process as if the user The group whose 10 appears in the /etc/
• The system had to be tuned to operate has entered a login name and password in passwd file is the primary group of the user.
effectively in a virtual memory environment. response to the login and password prompts. This is the group whose 10 will be given to all
files created by the user, The primary group
• The kernel had to be made functionally and The name of the user to be auto logged can will appear at the head of the list when the
structurally robust enough to be the center be changed by editing the /etc/autolog file group membership is queried with the groups
of a production operating system, rather and changing the login name in the file. Auto command. The primary group can be
than an experimental vehicle. Logon can be negated by deleting the temporarily changed by use of the newgrp
contents of the /etc/autolog file or simply by command.
The following sections describe the various deleting the file itself.
changes and additions that were made to The system makes extensive use of this
meet our objectives. Multiple Concurrent Groups facility in controlling and permitting access to
The Multiple Concurrent Groups facility allows certain privileged system files. This is
Appropriate Interfaces for a Personal a user to access files that are owned by any particularly true for those commands that are
Workstation Environment of the groups in which the user has considered to be for superuser or "limited"
membership. A user 10 can be specified as superuser use only. These commands are
Gary Miller belonging to more than one group. The owned by superuser and are assigned to the
"primary" group is specified in the /etc/ system group. Read and execution
Auto Logon passwd file. Any additional groups are permissions are given to the owner and
The Auto Logon facility of AIX permits a user specified in the /etc/group file. When the user members of the system group, with execute

96
permissions denied for all other users. The system determines that the file system on • Facilities to allow the user to connect to
System group membership can be given to the removable media should be "unmounted" another RT PC and invoke IWS on that
those users who are to be allowed to execute when the directory on which the file system is system to connect to a third system
these commands. to be mounted is not the current directory and
no file is open on the removable media. • Facilities to allow two users on a given
Reduce Superuser Dependency system to concurrently use IWS
The AIX system is configured to allow a user Interactive Workstation
on a single-user user system or multiple • Facilities to allow the user to invoke IWS or
users sharing a system to perform many of Evelyn Thompson XMODEM from another RT PC or terminal
the superuser functions without having to log by dialing into an AIX logger.
on to the system as superuser or to issue the The Interactive Workstation (IWS) program
su command to gain superuser authority. allows the user to easily connect, via the The menu-driven interface to IWS consists of
asynchronous ports, to another computer several menus. The main menu is first
This scheme is based on the use of the AIX system, such as The Source, or another AIX displayed when IWS is invoked. This menu
file permissions, making extensive use of system from either the AIX system console or allows the user to:
group permissions, multiple concurrent an attached terminal. The connection can be
groups, and set user ID. initiated via a command interface or a menu- • Initiate a connection to another system by
driven interface. The following functions are an asynchronous communication link
Each of the files (commands, data, etc.) is provided:
assigned to a particular group, and users are • Request a phone directory menu from
assigned to corresponding groups depending • The necessary transformations to make the which he or she can make the connection
on the authority to be given to the particular system console keyboard appear as either
user. As users are added to the system, they an RT PC or an async terminal to the ~ Request help information
are placed into the Staff group (group of remote system
general users). Users can then be given • Request the "modify local terminal
additional authority by assigning them to • Two protocols to transfer files to or from variables" menu
additional groups, such as the System group. the remote system
• Request the "alter connection values"
Removable Media • Facilities to allow the user to capture menu
The removable mount facility of AIX is received data in a system file as well as
intended primarily to be used with diskettes display the data on the user's screen • Execute an operating system command
which contain mountable file systems. With
this facility mountable diskettes may be • A phone directory function which is • Quit the IWS program.
inserted in and removed from the diskette maintainable by the user
drive without doing an explicit mount or The Connection menu, is similar to the Main
umount command. • A menu by which the user can alter the menu and can be invoked by the user any
local terminal characteristics time after the connection to the remote
The system determines that the file system on system has been established by executing a
the removable media should be "mounted" • A menu from which the user can alter the controLv key sequence. The only differences
when the directory on which the file system is data transmission characteristics between the Main menu and this menu are
to be mounted is the current directory and that the initiation and directory request
media containing a valid file system is • Facilities to allow the user to utilize any of functions are replaced by:
inserted in the drive or when a file is opened the supported asynchronous
on the removable media. communication adapters • Send a file over an established connection

97
• Receive a file from an established with the high-order 4 bits selecting a segment paging of both users and the kernel, and a
connection register and the low-order 28 bits providing a process fork enhancement.
displacement within the segment. The
• Send a break sequence segment registers contain a 12-bit segment Segment Register Model
10. The 12-bit ID plus the low order 28 bits of The segment register model for AIX is as
• Terminate the connection. the effective address yield the 40-bit virtuar follows. At any given time, the IDs of up to 16
address. A virtual machine may have many segments may be loaded into the segment
The Directory menu is invoked by the user segments defined. To access one of these registers. Each of the 16 segments may be up
from the main menu. This menu displays segments, the virtual machine loads a to 256 megabytes. Each page in a segment is
phone number entries from which the user segment identifier into one of the 16 segment individually protected for kernel access and
can initiate an auto-dial sequence. registers. Segments are private to a virtual user access. The AIX kernel occupies
machine unless the virtual machine that segment register O. Most of the kernel
The Alter menu is invoked from either the creates the segment explicitly gives other segment is page-protected no-access for the
Main or Connection menu. This menu allows virtual machines access to that segment. The user. A few kernel-segment pages used to
the user to specify or alter data transmission 16 segment registers represent part of the transfer data from the kernel to a user
characteristics, such as the number of bits context-switching aspect of the multiple- process are protected read-only for the user.
per character or the line speed. It also allows process model in AIX. Each user process is allocated three
the user to specify the TTY port, dialing segments. Segment register 1 is used for the
prefix, and file transfer mode. In addition to segments, there are two other user text segment. The text segment is
types of virtual memory objects: pages and protected read-only for the user and read-
The Modify menu can be invoked from either bytes. Pages consist of 2048 bytes. A write for the kernel (so that the kernel can
the Connection menu or the Main menu. This segment can contain from 1 to 131,072 modify programs being debugged). The user
menu allows the user to change the capture pages. Protection is available at the page data segment occupies segment register 2,
file name. It also allows the user to toggle level. Protection information is stored for and has read-write access. Segment register
some IWS features such as async emulation individual pages and then some specifics of 3 is used for the user stack. The top of the
mode. the protection mechanism are selected when stack holds the user "u-block," which is
a segment register is loaded. protected no-access for the user and read-
Efficient Operation in a Virtual Memorj write for the kernel. The u-block is used by
Environment Pages are brought into active storage the kernel for process management. The rest
(operating system memory) on a demand of the stack is protected read-write for both
Anthony D. Hooten basis via page faults. A page fault is a the user and kernel. Segment registers 4 thru
memory exception caused by a program 13 are used for shared-memory segments
The Virtual Machine Environment of AIX trying to reference data that is not currently in and for mapped data files. Shared-memory
The AIX operating system kernel executes in real storage. segments provide a means for sharing data
a virtual machine maintained by the Virtual among multiple processes. Mapped data files
Resource Manager (VRM). The VRM provides Virtual Memory Program Management are described in the following section.
virtual machines with paged virtual memory, Extensions Segment register 14 is used by the VRM to
with paging support logically hidden from the The AIX kernel has been enhanced to use the perform DMA operations. Segment register 15
virtual machine. A virtual machine may treat VRM virtual memory services. This section is used to address the 110 bus directly.
the memory as if it were physical memory will discuss three AIX program management
with highly variable access times. The VRM extensions which take advantage of the Demand Paging of Both Users and A/X Kernel
40
supports a large virtual memory, up to 2 or advanced virtual memory support. These are Both the users and the kernel execute in
one terabyte. The effective addresses the AIX segment register model, demand demand-paged virtual memory. When a user-
generated by instructions are 32 bits long, process reference to a page results in a page

98
fault, the VRM notifies the kernel, so that AIX and Mapped Data better position to control disk contention
another process can be dispatched. This and paging
page fault notification results in improved Mapped Page Ranges
overall system performance, since process Simple paging systems usually suffer from • Simplification of the data addressing model.
switching can occur when a process is conflicts between file I/O and paging I/O. For
waiting for a page fault to be resolved. The example, a file device driver may read disk The VRM supports a means by which AIX can
kernel is only preempted when a page fault data into a memory buffer, then the paging map the disk blocks of a file to a virtual
occurs on user data. All other page faults system might write that buffered data out to memory segment and have phYSical I/O
which occur for a kernel process are handled disk. Obviously, some coordination is required performed by the memory management
synchronously, with no preemption of the between the AIX operating system kernel and component of the VRM. This mechanism is
kernel process. the VRM to prevent this. known as "mapped page ranges."

Process Fork Enhancement Potential duplication of effort also exists with The AIX kernel takes advantage of VRM
The AIX "fork" system call creates a new program loading. A loader may read a mapped page range support, and applications
process. The new process (child process) is program into memory from the program in AIX benefit from this mapped page range
an exact copy of the calling (parent) process's library part of the disk, then the paging support both impliCitly and explicitly.
address space. The address space consists system uses another part of the disk to store
of text, data, and stack segments. Typically, the program when it is paged out. Having the Mapped Executables
when executing a new command, the "fork" VRM page the program directly from the Implicitly, the AIX kernel implements mapped
system call is followed by an "exec" system program library saves having to explicitly load page range support in the form of mapped
call to load and execute the new command in programs and also eliminates space wasted executables. When a program is loaded, or
the new copy of the address space. This by copying the program out to a page area of "execed" in AIX terminology, the AIX kernel
resuits in replacing the forked address space the disk. maps the program's disk blocks to distinct
with the address space of the new command, virtual memory text and data segments. The
thus undoing much of the work of the fork. Carried to the extreme, only the paging AIX kernel performs very little phYSical I/O to
system would need to be able to do physical load the program. Only the program file
Copying the current process's address space I/O. The AIX file system manager could tell header is "read" by the kernel. All remaining
is expensive and time-consuming - too the VRM the mapping between data on the disk I/O is demand-paged as the program is
much so to waste, if it is to be subsequently disk and virtual memory pages, and the executed. This results in a significant
deleted by the "exec" system call. The VRM paging system could then perform all the performance increase for large programs,
"copy segment" SVC creates a new segment, phYSical disk I/O. which without mapped page range support
but delays the actual copying of the data until would have to have been read entirely into
one of the sharing processes actually The close interaction between the AIX kernel memory, and possibly paged out by the
references the data. Therefore, most of the and the VRM offers several distinct paging supervisor.
data will not have to be copied when an advantages:
"exec" system call follows, thus saving the Mapped Data Files
time and memory required for the copy. The • Reduction in secondary paging space since ExpliCit AIX mapped file support consists of a
AIX "fork" system call uses this VRM copy- many permanent objects, such as program system call interface to the data file map
segment facility to create the segments of a text libraries, can be paged directly from page range facilities. The "shmat" system
new process. This enhancement of "fork" their permanent virtual disk location call, with the SHM_MAP flag specified, is used
reduces wasted effort. to map the data file associated with the
• Improvement of performance since the specified open file descriptor to the address
centralized VRM paging supervisor is in a space of the calling process. When the file

9&
has been successfully mapped, the segment descriptors (resulting from multiple "open" applications a consistent interface to work to
start address of the mapped file is returned. system calls). However, a file can not be for virtual terminals and communications
The data file to be mapped must be a regular mapped both read-write and copy-on-write by sessions, improve the performance
file residing on a fixed-disk device. Optional one or more users at the same time. characteristics of the system, make additions
flags may be supplied with the "shmat" to its application-development capabilities,
system call to specify how the file is to be When a file is mapped onto a segment, the and simplify the amount of development
mapped. If the flag SHM_RDONLY is file may be referenced directly by accessing required to support new devices.
specified, the file is mapped read-only. If the the segment via Load and Store instructions.
flag SHM_COPY is specified, the file is The virtual memory paging system I/O Management
mapped copy-on-write. If neither of the flags automatically takes care of the physical 110. We restructured the 110 Management area of
are specified, the file is mapped read-write. References beyond the end of the file cause the kernel to make effective user of the
Before a file can be mapped read-write or the file to be extended in increments of the VRM's 110 facilities. Instead of a specialized
copy-on-write, the file must first have been page size (2K). device driver for each distinct device, we
opened for write access. Before a file can be created a family of generic device drivers that
mapped read-only, the file must first have Experience with AIX has demonstrated that are capable of supporting a number of unique
been opened for read andlor write access. significant performance benefits can be devices of a given class. For example, a
derived from the judicious use of mapped file single "async" device driver handles async,
All processes that map the same file read- support for data file manipulation. A RS-232C, and RS-422 interfaces. Truly
only or read-write map to the same virtual significant amount of system overhead is device-specific considerations are left to the
memory segment. This segment remains eliminated by mapping a data file and VRM device drivers, which can be added or
mapped until the last process mapping the file accessing it directly via Load and Store replaced dynamically without bringing down
closes it. operations, rather than conventional access the system.
via "read" and "write" system calls. "Read"
All processes that map the same file copy-on- and "write" system calls are still supported, Multiplexing
write map the same copy-on-write segment. even when the file being accessed is mapped. We added a facility to allow dynamic
Changes to the copy-on-write segment do not AIX mapped file support determines whether extensions to a file system. If the multiplex bit
affect the contents of the file resident in the or not a file is mapped when a "read" or in the special file inode is on, the last qualifier
file system until an "fsync" system cal! is "write" system call is requested for the file, of the file name is passed to the character
issued for a file descriptor for which copy-on- and accesses the file appropriately if the file device driver. The driver looks for the file
write mapping was requested. If a process is mapped. An additional level of efficiency outside of the nominal file system. This facility
requests copy-on-write mapping for a file, and has been found to result from use of the is used to deal with virtual terminals and
the copy-on-write segment does not yet exist, processor-architecture-specific "memcpy" communications sessions as files.
then it is created, and that segment is subroutine in conjunction with mapped file
maintained for sharing until the last process support. This subroutine takes advantage of File System
attached to it detaches it with a "close" Load Multiple and Store Multiple instructions
system call, at which time the segment is to perform fast data movement. Alan Weaver
destroyed. The next request for copy-on-write
mapping for the same file causes a new Building a "Production" Operating System The AIX file system takes advantage of the
segment to be created for the file. A number of enhancements were needed to virtual device interface provided by the VRM.
make AIX suitable for the wide variety of To improve performance, we increased the
A file descriptor can be used to map the customer environments and applications that block size of the file system and the buffer
corresponding file only once. A file may be we expected it to support. Generally cache to 2048 bytes. To permit AIX to
multiply-mapped by using multiple file speaking, we felt that we needed to give accommodate an indexed data management

100
feature and a data base manager, we added user more control over the data on the disk Process/Program Management
the ability to synchronize the buffer cache and permits an application such as Data
with the fixed disk on a file rather than a file Management Services to force writing of only Deb Blakely, Carolyn Jones, Conrad Minshall
system basis, added locking facilities, and those buffers that really need to be flushed.
incorporated facilities to recover space in Signals Enhancements
sparse files. Dynamic Space Management In addition to the standard set of System V
AIX has two system calls to recover space signals, AIX provides an enhanced signal
Use of Minidisks within once-sparse files. The calls are facility. This facility allows a program to mask
The VRM provides the ability to divide a given "fclear" and "ftruncate." and block each type of signal while it is
fixed disk into a number of minidisks. This executing. If a signal is received while it is
permits the separation of file systems for • fclear - zeroes a number of bytes starting blocked, it is queued up and handled after
different purposes onto different virtual at the current file position. The seek pOinter that signal type is released. However, only
devices. is advanced by the number of bytes. This one of each type of signal will be queued.
function is different from the write operation Except for the SIGCLD Signal, all subsequent
AIX will let a user make 1 to "n" file systems in that it returns full blocks of binary zeroes signals of the same type will be ignored. All
on a physical disk, where "n" depends on the to the file by constructing holes and SIGCLD's will be queued and processed. Up
size of each file system and of the disk returning the recovered blocks to the free to 32 different signals are supported by the
device. Each file system is built in a separate list of the file system. enhanced signals package, but only those
VRM minidisk. defined in file /include/sys/signal.h can be
• ftruncate - removes the data beyond the used. These are the same signals used by the
AIX uses 512-byte blocks for diskette file byte count in a file. The blocks that are standard facility. The following are brief
systems and 2048-byte blocks for disk file freed are returned to the free list of the file descriptions of the system calls that make up
systems. With the larger block size the system. the enhanced signal facility:
number of interrupts to be handled is
reduced, resulting in faster effective transfer File/Record-Level Locking sigblock Adds specific signals to the list
of data to real memory. AIX file and record level locking extensions of signals currently being
allow an individual file to be locked in either blocked from delivery.
The space on each minidisk that contains a an advisory or enforced form. The advisory
file system is divided into a number of 2K- lock notifies the caller of 'Iockf' if the sigsetmask Sets the signal mask (the set of
byte blocks, logically addressed from 0 up to requested region of the file is locked. Signals to be blocked from
a limit that depends on the size of the Enforced lock protects the locked region from delivery) to a specified value.
minidisk. A corresponding cache of 2K-byte access by readers and writers even if they
buffers is used to reduce re-reading of have no knowledge of the locking facility. If sigpause Sets the signal mask to a new
blocks. the object being locked is a directory or a value, pauses until a signal not
special file, only advisory locks can be blocked by the mask is received,
Buffer Cache Synchronization obtained. and restores the signal mask to
Cache buffers are normally only written to its original value.
permanent storage before the buffer is used Records may be of any length ranging from
again or with the "sync" system call. AIX has, one to the maximum of the file size. The data sigstack Allows users to define an
in addition, the "fsync" system call that works for a locked record does not need to exist in alternate stack to be used for
on an open-file basis to force the modified order to obtain a lock on the record. Locks signal handling or get the state
data in the cache buffer to permanent storage may be applied beyond the current end-of-file of the current signal stack.
and does not return until all of the buffers or over an area that has not been written
have been successfully written. This gives the (sparse file regions).

101
sigvec Allows users to specify how a buffer headers, pointing into user space record to that of queue = directory and
specific signal is to be handled. instead of kernel buffers, maintains state message = file. This means that the same
The user can specify whether information, allowing process switch. A given kind of information found on a file can be
the signal should be blocked, call into rdwri will end up allocating a ring of found on an IPC message: user ID, group 10,
ignored, or processed by a these buffer headers, one of which is a ring time, etc.
handler routine, and whether the header. The parallel asynchronous operations
signal should be processed on permit the VRM disk driver to schedule for Applications and servers can use the
the current stack or a special minimum arm movement and helps lower the additional information found in the extended
stack. interblock overhead, so that physically IPC message structure to check permissions
adjacent blocks can be read without waiting and send time. Servers can now validate
execve Starts a new program in the an entire rotation. requests based on the information in the
current process, resets all extended IPC structure, rather than starting
signals that are being caught by Buffer bypass has not been made available new processes that take on the properties of
the original program to terminate above the kernel. In a virtual memory the program being served. The timestamp can
the new program, resets the environment, we consider mapped files be used to make sure the message is not an
signal stack state, and leaves the superior. For small transient processes that old one or to perform other tasks based on
signal mask untouched. reference all or nearly all of their pages, time priority.
buffer bypass may have a performance
Buffer Bypass Variations advantage. But how small is "small" and how Terminal Support
"Buffer Bypass" is a form of disk I/O which, transient is "transient?" That is, where is the
like raw I/O and mapped files, bypasses the breakeven pOint and how is it dependent on Rudy Chukran
kernel's buffer cache, transferring data current memory load? In the presence of
directly between the VRM disk device driver these unresolved questions, it was decided to AIX terminal support is tailored to work in the
and AIX user processes. This offers direct use mapped files wherever possible - buffer VRM environment, where terminals are virtual
and indirect performance gains when it is bypass has been limited to use by the exec constructs rather than real devices. It permits
unlikely that the data will soon be re- system call for programs whose segment applications to use multiple virtual terminals
accessed. The direct gain is the lack of a alignment disallows mapped execution (I.e .. and to access their virtual terminals in either
memory-to-memory copy of the data. The for programs linked without the - K option). extended ASCII mode or in "monitored"
(more substantial) indirect gain is the mode.
generally improved cache hit ratio which IPC Queue Extensions
results from not replacing useful cache blocks System V interprocess (IPC) message Console Support
with data that is unlikely to be reused. services have been extended to give more In order to take advantage of the unique
information when receiving IPC messages. functions provided by the Virtual Terminal
The implementation of buffer bypass is not The new function call is "msgxrcv". Manager subsystem of the VRM, a console
device-specific. Requests are in terms of a device driver was created and modeled on
file offset and a count, unlike raw I/O The msgxrcv function returns an extended the RS232 terminal device driver (tty). This
requests, which are in terms of contiguous message structure that contains the time the new device driver is referred to as the HFT
physical blocks. Within the rdwri loop we message was sent, the effective user 10 and device driver. It provides support for a
detect when we need all of a block and (if group 10 of the sender, the node ID of the console consisting of a keyboard, mouse or
buffer bypass has been requested) we call an sender or zero if the sender was on the local tablet, speaker, and up to four displays.
asynchronous block I/O routine which node, and the process 10 of the sender.
bypasses the buffer cache. After exiting the Multiple Virtual Terminals
loop, we wait on all outstanding The IPC design model has been changed Some device semantics were established to
asynchronous operations. A separate pool of from that of queue = file and message = allow programs to create new virtual terminals

102
and access existing ones. If a program Since the hardware protects the I/O bus from The program is now ready to access the
wishes to create a new virtual terminal, the access by user programs, a program must display. The hardware registers and refresh
open system call is issued on the device request bus access by opening the /dev /bus memory are stored into by dereferencing a
/dev/hft. That special file is designated as special file. This open sets the bits in the pointer which contains the appropriate
multiplexed by setting the "multiplex" bit in control register which disable bus access address in the I/O space. When the program
the inode. If an existing virtual terminal is protection. This control register is saved and is permanently finished with the display, it
desired, the program opens the device /dev/ restored for every process dispatch, thus would reverse the steps just described, thus
hft/n, where n is the character representation maintaining security of the bus from leaving the virtual terminal in the same state
of a decimal number. This number is referred unauthorized programs. as when the program began.
to as the channel number, which may also be
interrogated by issuing an ioctl system call on Next, the program puts the terminal into Even though operating a terminal in
the file descriptor in question. monitored mode with a control in the output monitored mode is complex, the speed of
stream. The control may optionally specify direct hardware access is attained, and the
If a program needs to know about and control that key data be entered directly into a user protected environment of a multiuser system
activity on all the virtual terminals associated buffer, thus bypassing clist processing. is preserved.
with the console, it opens the device Otherwise, key data is read through the
/dev/hft/mgr. This gives the program access standard read system call. Printer Support
to the screen manager component of the
VTM subsystem. The program may now The program next does an ioctl to set the Jim Chen, Larry Henson
query the state of all the virtual terminals, signaling protocol. Since other virtual
activate any terminal, or hide any terminal by terminals may be activated at any time via the Device Driver
issuing an ioctl. Next Window key, a program operating in The printer device driver provides the
monitored mode must relinquish the display interface to the VRM from the kernei
Extended ASCII Mode hardware to the operating system upon environment. Up to eight concurrent printers
The default mode for a virtual terminal request. This request mechanism is done with (fdev/lpO through /dev/lp7) are supported.
simulates an enhanced version of the signals. When the program is ready to begin Enhancements have been made to provide
standard ASCII terminal. It permits programs display activity, it issues a Screen Request better error recovery procedures. Errors, as
built for that interface to run with minimal control in the output stream. When the they are discovered, are returned to the
change. It also permits new versions of such system determines the display is available, it application environment only if the application
programs to access the sound and mouse sends the program a signal denoting display requests that they be returned. A new set of
functions. availability. The program can now change the ioctls has been defined to allow printer
hardware settings without interference from control from the application. LPRVRMG and
Monitored Mode the system. When the Next Window key is LPRVRMS get and set the VRM define device
In order for a program to operate a bit- pressed, the system sends the program a structure associated with a printer. This
mapped display in bit mode, the program signal to relinquish the display. The program configuration information and error status
deals directly with the hardware display now has a fixed length of time to output a allow the user to control the error processing
adapter by storing to the memory-mapped I/O Screen Release control, which signifies that and printer setup. LPRUGES returns the AIX
bus. This is done for reasons of speed. Some the program has saved whatever states need device driver's view of the error situation.
rules were established which are to be to be saved. If the program does not respond After the error has been determined,
followed for programs which operate a with a Screen Release, all processes in the LPRUFLS allows currently queued buffers to
display in bit mode and still allow other tty group are sent the SIGKILL signal. be flushed. LPRURES will tell the VRM to
programs to operate using other virtual resume printing the job. LPRGMOD and
terminals. LPRSMOD get and set the synchronous vs

103
asynchronous printing modes and the option messages are routed back to the user for
Applications/users
to be signalled when an error occurs. both fatal errors and intervention conditions.
After the intervention condition is corrected,
Printer performance has often been a printing resumes automatically. A generic data
problem when high speed printers were used. stream will print on any of the supported
The device driver now supports both printers. Applications are simplified by ha~ing
synchronous and asynchronous. write ~ystem to deal with a single printer type. Formatting
calls. The device driver returns Immediately for the specified margins, justification, and
after an asynchronous write is queued. A image graphics support help the user to get
synchronous call returns after the write is the output needed.
finished. Where feasible, buffers are output
without making a copy. Each of these print queue How can a user attach a printer that is not
functions is performed for both serial and Backend top layer supported by the IBM backend? If the printer
parallel printers. Backend formatter
uses the 5152 data stream, that printer can
be configured to run through the IBM .
Previously, serial printers have been run backend. If the data stream is like 5152 With
through the tty device driver. Since tty is extensions, the relevant functions can be
optimized for terminals, getting the right defined as being on the printer and used as
function for printers has been difficult. By desired. If a dissimilar printer is desired, the
adding serial printer support to the printer user can write his own backend to be used
Figure 1 Print Subsystem Structure
driver, the full performance and error with his printer. This user-written backend can
recovery enhancements can be utilized. loctls still be used concurrently with the IBM
one of the new IBM printers without knowing
LPRGETA and LPRSETA allow the baud rate, backend.
the details of how it works. When the system
character size, parity, and number of stop bits
is set up, the customer describes the printers
to be queried and set. The splp(1) command Extended Character Set
that are to be used, including such factors as
has been extended to do a stty-like setting of The use of the 7-bit ASCII code definition in
paper size and default print quality. If on~­
these options. 8-bit-bvte machines has created some
time changes are reqUired, a command line
proble~s. For simplicity, most applications
parameter will override the configuration
Replaceable/Addable Backends have adhered to the 7-bit standard when
already set up for a single job. These
The print command allows user access t~ the writing portable code. While avoiding the
configuration options allow printers to ?e. set problem of how to use the 8th bit, it allowed
queuing environment (see Figure 1). ~ultlple
up for different types of jobs. Thus, .exlstlng
queues per printer allow the same ~nnter to applications to use that bit for whatever .
applications will work on the new pnnter~.
be used for different job types. Multiple purpose they wished. This "usable" 8~h b~t
without changing the application. The ability
printers per queue can keep the output solved many a sticky problem for applications
to add new printers in a transparent way
flowing in case one printer is unusable. T~e that needed "tricks" in their data stream, but
simplifies Change-over requirements.
qdaemon provides background control of the it also created a portability probiem between
queues. Started up by the qdaemon, applications. Applications that did not use a
A multiple queueing environment provides for
backends do the work of getting the data to pure 7-bit data stream could not ~nderstand
using several printers concurrently.
the device drivers. applications that had polluted their data
Replaceable backends for different p.rinters
stream with a different 8-bit variation.
associated with a queue allow the pnnt
The user should not have to know the details
subsystem to function as needed in different
of how each printer works. By providing a With the advent of the IBM PC, many new
situations. We have provided a backend to
more general printer-support structure, we programs have been writte~ to con~orm to the
support appropriate IBM printers. Error
made it easier for the user to install and use PC code page mapping. ThiS mapping uses

104
the 8th bit to map graphics for code points applications. The display and printer and Pascal compilers for all floating point
from 128 to 255. This extension has allowed subsystems provide controls for accessing operations. Floating point operations can be
programmers to print and display many these code pOints. Data stream controls further enhanced with the addition of the
scientific and international graphics not provide switching to one of three code pages. hardware Floating Point Accelerator
previously available to them within the These code pages are designated: PO, P1, feature.[1 ]
definition of 7-bit ASCII codes. We considered and P2.
it important to establish a code set definition The compilers perform floating point
that could support applications from both The base code page, PO, is based on the IBM operations by making subroutine calls to the
worlds. AIX display and printer support for PC display font with the exception that the set of floating point routines located in the
8-bit codes was implemented to help meld PC first 32 code positions contain controls kernel's segment O. The interface to these
applications into the world of AIX. The 8-bit instead of graphic characters (which were routines is via a vector of entry points at a
support is compatible with 7 -bit ASCII moved into P1). This base code page allows fixed location in memory. Although these
applications and provides an additional most applications PC compatibility without routines are part of the kernel, they are
degree of commonality with a large number of any changes. In order to access graphics on executed in user mode to avoid the overhead
PC applications and files. code pages P1 or P2, application programs of a system call. This area of the kernel is
need to imbed switching controls for the read-only protected by the page protect
While the 8-bit extension is useful in printer or display in the output data stream. mechanism to prevent modification by user
integrating PC applications, there still exists a The application program also needs to use programs.
large problem in representing all the graphics switching controls to return to the original
needed for scientific and non-U.S. code page. Each entry in a code page can be The floating point routines provide an
applications. Over the years, we have selected by its 8-bit offset value in the code environment of six floating point registers,
identified and documented most of the page. For displays, the 8-bit offset is added to with a status register that controls exception
character-graphics requirements for scientific a code page offset value in order to access a and rounding modes. The floating point
and international applications. These particular code point. For printers, once a registers may contain either a single-precision
character graphics have been organized and code page has been selected by an ASCII or a double-precision floating point number.
standardized across IBM. Each code page is escape sequence, 8-bit code pOint offsets Basic operations are in a two-address
a set of 256 graphics, usually grouped by select graphics in the active code page. (source-destination) form, allowing either
countries (e.g., UK English, France, Germany, register-register or immediate-register
Spain) or major application (e.g., PC or The extended graphic characters defined in operations. A no-result flag allows a routine
Teletext). These code pages, if handled PO, P1, and P2 fulfill the major support to return to the caller without bringing the
independently, represent thousands of requirements for the US, Europe, Teletext, result out of the destination register and
characters and graphics. However, there are and scientific symbols. returning it to the caller. This allows the
many redundant characters and graphics ROMP processor to continue executing
(mainly alpha-numeric and punctuation Floating Point Support instructions in parallel with the Floating Point
characters). This presents a sizable problem Accelerator. The Accelerator can be given a
for applications to store and process these Richard Eveland second operation to perform before the first
character mappings to provide extended is complete, e.g., an Add followed by a
support for scientific and international The RT PC system provides enhanced Multiply, further increasing throughput.
symbols. services for floating point arithmetic. These
services are disigned to support the The Floating Point Accelerator has 32 sets of
To aid programmers in dealing with this Institute of Electrical and Electronic floating point registers available for user
problem, the AIX system provides a canonical Engineers' (IEEE) new standard for Binary processes. These are allocated to a process
mapping of the most widely used IBM code Floating Point Arithmetic (754). The floating by the kernel only if the process actually
pages required by scientific and international point package is utilized by the C, FORTRAN, performs a floating point operation. This way

105
the user program does not have to implement all of the functions required by the One of the major challenges of the AIX RAS
specifically ask for a hardware register set. IEEE floating point standard, e.g., handling design was to provide a consistent set of
When there is no Accelerator, floating point denormal operands. When such an event user interfaces and information across all
subroutines emulate the floating point occurs, the hardware causes a Program components - VRM, kernel, and
registers in a reserved area on the user's Check interrupt which is handled by software applications.
stack. emulation routines in the VRM. The VRM
routines put the correct result back on the AIX error messages emphasize problem
The kernel provides two sets of floating point card so that the event is transparent to the resolution. The user should be able to
routines: one set that implements the running program. diagnose any "non-catastrophic" problem
functions entirely in software and another set without resorting to offline documentation.
that utilizes the Floating Point Accelerator Reliability/Availability/Serviceability (RAS) "Catastrophic" may be defined as any
hardware for most of the floating point problem for which there is no visible means
operations. The kernel installs pointers to the Ellen Stokes of doing problem determination with the
appropriate set of routines into the vector of online facilities (e.g., system fails to IPL) and
entry points at machine initialization time. The IBM RT PC system RAS support is which results in the user being unable to
Thus programs using this interface will designed to provide a coherent and continue the work session. Problem
automatically use the Floating Point consistent set of error detection and determination may be approached in several
Accelerator card when it is present, but will correction schemes. Wherever possible, ways in the IBM RT PC environment, but the
use the software emulation subroutines when functions and components are self-diagnosing essence of problem determination is to give
there is no card. Programs compiled to use and correcting; that is: the user the necessary information for
this "compatible" mode have the ability to run problem correction at the highest possible
on any machine, regardless of whether or not • Error messages with clear unambiguous level within the system. The user will generally
the Accelerator option is present. meaning are generated. be able to rely on a single message for the
information required to manage a function to
Although the presence of the Floating Point • Formatted error logs are automatically successful completion. If the level of user
Accelerator will significantly speed up the generated. sophistication or problem complexity requires
floating point operations in user programs the exposition of additional information, a
compiled in "compatible" mode, the maximum ~ Dump facilities are provided. help file can be displayed by the user if one
benefit is achieved by compiling the program exists. If additional information is required by
to drive the Floating Point Accelerator directly • Error analysis routines support software the user, diagnostic tools are available in
with in-line code. For C and FORTRAN and hardware problem determination. IBM-supported LPPs which provide detailed
programs this may be done by compiling the execution time flow and error analysis. Dump
program with the "direct" option ( - f). This A primary objective of the RT PC system RAS process execution may be initiated by the
results in maximum speed for floating point support is to provide problem determination user to view the state of the system at the
operations by avoiding the subroutine and correction for the customer, for a time a repeatable error occurs.
interface for most floating point operations. customer service vendor, or for IBM at the
However, the Floating Point Accelerator card request of the customer. As such, the system The following sections describe the various
must be present for these programs to run. must be reliable in all respects, but in the problem determination facilities in the RT PC
Direct mode versions of the C and math event that there is a failure, the system must system.
libraries are provided to be linked with user be easily and quickly diagnosed and
programs compiled this way. recovered. Note that "the system" is defined Trace
as that portion of the system which is IBM The trace function is intended to provide a
The Floating Point Accelerator's hardware developed and/or controlled. tool for general system/application debug and
floating pOint unit, the NS32081, does not system performance analysis. Trace monitors

106
the occurrence of selected events in the the trace points in the VRM and double application trace minor device
system. Important data specific to each of buffers them. When a buffer reaches a (/dev/appltrace).
these events is recorded on disk. When the threshold number of entries, the VRM trace
user needs to view this data, a trace report collector notifies the VRM trace process and The trace stop command (trcstop) terminates
program formats the trace data in an the VRM trace process sends that buffer to tracing by sending software termination
intelligible form. The report program sorts the the trace application to be written to the trace signals to the active trace daemons.
disk file by date and time, providing a file. The trace process is terminated by a
chronology of the system's behavior. The Send_Command SVC (trace off). Trace data is formatted and displayed in a
trace function may be started either by the readable format with the trcrpt command.
user or by an application. In AIX, the kernel trace device driver is the Because each record is time-stamped, the
central control point for trace functions. This trace log file is sorted chronologically and
The user has two commands for controlling trace device driver /dev /trace has three minor then formatted according to the data saved
the operation of trace: start and stop. When devices which correspond to the three levels by the trace point which generated it. The
starting trace, the user should specify a of the system's software. The application data trace report generator is driven by an external
profile. This profile is an AIX file that contains is handled by /dev/trace, kernel data by table of trace format templates which are
a list of all the classes of events the user has /dev/unixtrace, and VRM data by /dev/ found in the file /etc/trcfmt. These templates
selected to trace, listed by event type with a vrmtrace. The trace device driver controls the describe the data layout of the trace data
descriptive label. Any number of trace profiles allocation of buffers to collect all trace data from each individual trace point. The template
may exist in the file system. There is a default and handles the reading and writing of the file may be modified by invoking the trcupdate
profile in /etc/trcprofile. This default profile is data in the buffers. It also issues the command to include trace points in newly
used if no profile is specified when trace is Send_Command SVC which initiates trace in installed programs or in third-party programs.
invoked. However, it is advantageous for the the VRM. The trace device driver has an To improve readability and information
user to tailor a profile to his own needs. interrupt handler which receives the interrupt content of the report, the template file also
from the VRM trace process indicating that a allows for substitution of meaningful
The trace function takes additional VRM trace buffer has reached its threshold mnemonics for trace points, predefined data
information about the trace session from the and needs to be emptied. AIX kernel entries values, etc.
RAS configuration file /etc/rasconf. This file are written to the AIX trace minor device
contains configuration data for all RAS /dev/unixtrace by the trsave macro. Dump
functions. The entry for trace includes the file The IBM RT PC system provides a system
name where trace data is to be stored On the application level, the trace daemon is level dump capability to enhance the user's
(default /usr/adm/ras/trcfile), the maximum the primary process for trace activity. The ability to do problem determination and
size of the file name (default 80 blocks), and process issues the ioctl command which sets resolution. In the IBM RT PC, a "DUMP"
the trace buffer size (default 2 blocks). the trace points "on" in the application, environment may be characterized in several
kernel, and VRM according to the ways:
Trace can operate at all levels of the system: specification in the selected trace profile. It
below the VMI, in the kernel, and at the also forks two child processes (as needed) • The VRM or virtual machine ceases
application level. which gather trace entries from the VRM and execution.
kernel trace buffers and write them to the • The VRM or virtual machine abends.
Below the VMI, trace functions are handled trace log file. The parent trace daemon reads
by the VRM trace collector and process. The the application-level buffer. For both AIX These failures may occur in an application,
trace process is initiated by a Send_Command extensions and applications, trace entries are the base operating system, or the VRM.
SVC (trace on) which sets up the trace collected by the AIX trace collector, which is
environment and starts the process. The VRM an AIX run-time routine. The AIX trace When a failure occurs, the user may choose
trace collector receives trace information from collector writes these entries directly to the to initiate a dump. The user presses a dump

107
key sequence: CTL-ALT-NUMPAD8 for a Error Log contains configuration data for all RAS
VRM dump. The target for a virtual machine The error log function is intended to provide a functions. The entry for error logging includes
dump is the dump minidisk (allocated at AIX tool for problem determination of hardware the file name where error log data is to be
install time) and the data placed on that dump and some software errors. Data specific to a stored (default /usr/adm/ras/errfile) and the
minidisk is defined by UNIX System V. The problem or potential problem and certain maximum size of the file name (default 100
target for a VRM dump is a high-capacity informational data (e.g., IPL/shutdown time) is blocks).
diskette. recorded on disk. When the user needs to
view this data, an error report program Error logging "on" means that all errors
The VRM dump program is permanently formats the error log data in an intelligible reported are recorded on a disk file. When
resident in memory. It has its own diskette form. The report program sorts the disk file error logging is "off," errors are kept in
device driver. It is self-contained and does not by date and time, providing a chronology of memory buffers but are never recorded on a
depend on any VRM resources. The dump the system's behavior. The error log function disk file.
program is intelligent; it does not dump all of can be started by superuser, but is generally
real or virtual memory. The first 32K of real started by /etc/rc. Error logging can operate at all levels of the
memory, NVRAM, tables, control blocks, page system: below the VMI, in AIX, and at the
o of virtual machines, error log entries, etc., The user has two commands for controlling application level.
are dumped. Each component (other than the operation of error log: start and stop.
base VRM) that resides below the VMI can Error logging is generally started by /etc/rc by Below the VMI, error log collection is handled
identify to the dump program the location of invoking the executable file /usr/lib/~rrdemon. by the VRM error log collector and process.
its dump table - a table containing relevant This error daemon process is the focal point The error log process is initiated by a
control structure addresses of data to be for gathering error records. The error log file Send_Command SVC (error log on) which sets
placed on the dump diskette. This specified in /etc/rasconf is implicitly two files up the error logging environment and starts
identification is normally made at device with extension .0 and .1. When the .0 file is the process. The VRM error log collector
initialization time, but can be updated at any full, the .1 is written; when the .1 file is full, receives error information from the VRM and
time. The dump program does not pick up the .0 file is then overwritten. This allows a its components. The VRM error log collector
any dynamic structures from components quasi-circular file to be kept with minimum notifies the VRM error log process and the
other than the base VRM unless the structure data loss. Any data that cannot be written to VRM error log process sends that error entry
is defined in the component dump table. the log file (e.g., disk adapter failure) is to A!X to be written to the error log file. The
written to NVRAM. Likewise, at error daemon error log process is terminated by a
The VRM dump formatter utility, invoked with invocation, NVRAM is emptied and the data Send_Command SVC (error log off).
the command dumpfmt, presents the dump written to the log file. Data in NVRAM is in an
information by name and hexadecimal abbreviated form because there are only 16 In AIX, the kernel error log device driver is the
representation with ASCII interpretation. The bytes available for error logging. But those 16 central control point for error log functions.
header information for a dump consists of a bytes are mapped to provide all types of error The error log device driver controls the
concise set of data defining the nature of the entries. Error logging can be stopped with the allocation of buffers to collect all error data
dump, such as failing module name and errstop command. It issues a software and handles the reading and writing of the
failure address. This header information termination signal which is caught by the data in the buffers. It also issues the
becomes part of the customer information error daemon. Error logging is normally Send_Command SVC which initiates error
provided to the IBM service personnel for implicitly stopped at shutdown. logging in the VRM. The error log device
problem resolution. The dump formatter can driver has an interrupt handler which receives
be run interactively or in batch mode. The error log function takes additional the interrupt from the VRM error log process
information about error logging from the RAS indicating that a VRM error entry has been
configuration file /etc/rasconf. This file generated and needs to be written to disk.

108
AIX kernel error log entries are written to the contains a one-line entry for each error Acknowledgments
AIX error log device (fdev/error) by the formatted. Optionally, the user can request a The porting, modification, building, testing,
errsave macro. detailed report which includes the one-line and documentation of AIX have involved
summary plus the data associated with that hundreds of people. The authors of the
For both AIX extensions and applications, entry. various sections of this article wish to thank
error log entries are collected by the AIX error their colleagues inside and outside of IBM for
log collector which is an AIX run-time routine. For each hardware entry in the error report, their ideas, support, and just plain hard work.
The AIX error log collector writes these an analysis of the error is appended. This
entries directly to the error log device specifies the probable cause, the error, what References
(fdev/error). hardware pieces to suspect as bad, a list of 1. Scott M. Smith, "Floating Point Accelerator," IBM RT
Personal Computer Technology, p. 21.
activities the user could perform for further
Error log data is formatted and displayed in a isolation, and a service request number. This
readable format with the errpt command. analysis is based solely on that error entry.
Because each record is time-stamped, the
error log file is sorted chronologically and Update
then formatted according to the data saved Updates for software products on the RT PC
by the component which generated it. The are packaged together on the same diskette.
error log report generator is driven by an A new "update" command provides a menu
external table of error log format templates interface to applying these updates. When an
which are found in the file /etc/errfmt. These update diskette is received, the user can
templates describe the data layout of the "apply," on a trial basis, the updates for one
error log data from each individual entry. The or more of the software products that are
template file can be modified by invoking the already installed on the system. The user can
errupdate command to include classes of then test the updated programs to ensure
errors in newly installed programs or in third- that they still function correctly in that
party programs. To improve readability and environment. If the updates have caused a
information content of the report, the template regression, the user can run the update
file also allows for substitution of meaningful command to "reject" (back out) the update.
mnemonics for classes of errors, predefined Otherwise, the user issues the update
data values, etc. command to "commit" the update as the new
base level of the program.
Error log entries are divided into classes
(hardware, software, IPL/shutdown, general Conclusion
system, and user-defined). Each class is We believe that we have successfully made
optionally divided into subclasses, and each AIX into an operating system that can be
subclass is optionally divided into masks. used without detailed knowledge of its
Because the error log file may become very internal structure. It takes advantage of the
large, the user can qualify what is to be functions of the Virtual Resource Manager to
included in his error report. The user can exploit the capabilities of the RT PC
specify a time span, a combination of hardware. It provides us with a general base
classes/subclasses/masks, error entries on which to provide support for additional
desired from a particular virtual machine, or devices, applications, and communications
error entries desired from a particular node. features without massive re-coding or user
The default report is a summary report that inconvenience.

109
Extendable High-Level AIX User Interface

Tom Murphy and Dick Verburg

Introduction be flexible enough to accommodate additions can be specified. Second was an object-
Including the UNIX kernel and command in the future without major rework to the oriented Files program. In this application the
language in the AIX operating system programs in the Usability program. user is first presented with a set of objects
presented us with both an advantage and a (files in the current directory). When one or
problem. The command language came Usability Definition more objects are selected, the user can then
complete with a wide range of functions The definition of the Usability program was, specify an action to be performed on the
already implemented. However, the large naturally, heavily influenced by the choice of object(s).
number of functions was a problem for the the user interface to be provided. The
new user. The names of the functions were interface chosen was to be a full screen To support these (and other) applications, two
frequently less than mnemonic, and there was interface on any of the terminals supported by additional components were defined as
little uniformity in the invocation syntax for the the system. The primary operator action was service packages. First, a dialog manager
various commands. Some accepted keyword to be a point-and-pick interface in which a was defined to provide the tools needed by
parameters, some used letter codes. Some selection was to be made from those applications to define and display successive
took their input from 'standard-input', others presented on the screen. When additional user-interface screens. Finally, libcur (an
accepted an input file name as part of their information was needed (beyond simple adaptation of an existing UNIX routine
invocation sequence. In short, the system selection) the user was to be presented with package) and terminfo were selected to
was designed for a programmer familiar with an overlaying window prompting for the provide control of the screen appearance and
the variety of commands and functions, rather required information. In addition, extensive supply an interface that masked specific
than for an inexperienced or casual user. 'help' information was to be available to the terminal device requirements.
user at most times, (More information on the
Objectives design and rationale for the user interface Implementation
The objective of the Usability program was to itself is contained in the paper by Kilpatrick While the components of the Usability
provide an alternative interface to the and Greene[1 ].) programs were defined and developed
operating system. This interface was to be independently, they share several attributes
oriented toward the user who was unfamiliar Two primary applications, as seen by the that can be seen when they are examined
with the details of the operating system. It user, were defined as part of the Usability closely.
was to be available to users on all terminals, package. First was an action-oriented Tools
those attached using the async interface as program. In this application the user is first Files Program
well as the system console. It was, however, presented with a choice of actions to be This application presents the user with a list
not to require creation of new commands to performed (e.g., print, copy, compile). After of the files in the current directory. While
provide function already provided in the selecting one of the presented actions, if there are options to limit the set of files
operating system by existing commands. additional parameters or 'object' presented, to sort the list, or to select other
Finally, while a particular subset of the specifications are required, the user is segments of the directory tree for display, the
operating system commands was defined for presented with an appropriate 'pop-down' primary operator action is to select the file to
the initial implementation, the system was to where the appropriate objects (usually files) be acted on. When a selection has been

110
 The determination of the file type is based on the application. The name of the commands
the suffix that is part of the file's name. A or command groups, the descriptive
table of information is maintained that relates information presented to the user, and the
the suffix to the set of actions that are valid names of other files associated with the
for files. For each file type there may be a commands are stored in these files. With this
special print program, compiler, editor, information stored outside the application,
interpreter, etc. For any of these entries the additional commands and command groups
specification may be either empty, indicating can easily be added to the application by
that the option is not valid for that file type, or simply changing the files, rather than by
may contain the name of the program that modifying the Tools program itself.
provides the support for the function. For
example, for most files the editor specified is Dialog Manager
ed, while for object programs no editor is The dialog manager provides application
specified. control and services to support the
Figure 1 Tools application uses action-object processing of interactive dialogs. Dialogs are
The description of a file type is carried named sets of field or record descriptors
outside the Files program. This provides a which can be presented within named screen
mechanism to modify file types without areas. The dialog manager monitors operator
modification of the Files program itself. New input and performs conditional processing
file types can be added in the system simply based on that input as specified by the dialog.
by adding a description for the new file type
(an interactive program makes this addition Dialog definitions were designed to minimize
easy). The main Files program does not the discrete number of times an application
require modification unless new classes of needed to be directly involved with screen
actions are added (in addition to print, edit, output and operator input. Dialog definitions
compile, etc). include information that allows the dialog
manager to direct the flow of control from
Tools Program one screen panel to another based on the
This application presents the operator with operator's actions.
lists of actions that can be invoked. The lists
Figure 2 Files application uses object-action of actions available are grouped into sets of Selectable fields, called buttons, can be
related actions. The first list presented is the defined within a dialog as can the actions to
made, the operator is presented with a choice list of available groups. After selection of a be performed when a button is selected.
of actions that apply to the chosen file. The group, the commands/actions that are part of Dialog actions include panel-to-panel
determination of what actions are valid for a that group are presented. Selection of a transition, presentation of a new object,
particular file is based on its file type and particular action generally will result in a assignment of a value to a named variable,
controlled by a file-type description that request for additional information to allow the removal of a panel, saving and restoring the
resides in a shared data area outside of the operator to specify the object to be acted on. dialog state, selection or de-selection of
Files program. another button, return to the application, and
The lists of commands are described in files linking to a user exit.
that are stored on disk, outside the code for

111
User exits are application routines to be Libcur and Terminfo
called by the dialog manager as specified in The libcur package of routines was adapted
Files Other Tools
the dialog definition. These routines are from a similar set of routines that existed in Program Programs Program
usually invoked to perform application-specific the UNIX system. This set of routines
tasks, for example, getting a new list of files. provides the structures and management
The dialog manager can be called recursively routines to control multiple, overlapping areas
from within user exits. on the display. Routines were provided to Dialog
Manager
allow the definition of such areas, assist in
Help text appropriate for the context of the managing the data that is presented in each
dialog can also be referenced from within the area and support presentation on the display
dialog. This help text is accessed using the with the appearance of overlapping papers. In Libcur/
system help facility to provide for flexibility addition, these routines use the system Terminfo
Routines
and translation, again without modification to terminfo routines, which provide access to
the programs using the dialogs. and processing for terminal description files
for each type of terminal being supported. Figure 3 Software Layers
Data entry is supported by character and
numeric fields, required entry fields, user The content of a terminal description includes Summary
exits, and a "blanks not allowed" option. the information about a terminal needed to At each level of the usability package, the
MUlti-line input fields are also supported. properly control and process that device. This programs have achieved a level of flexibility
Default values can be constant text, named includes information about the data ~tream primarily by moving significant amounts of
variables, or combinations of either. Operator that must be sent to the device for required control information out of the program and
entered data is stored into named variables functions (e.g., move the cursor to a selected into external data files. Each time this is done
as specified in the dialog definition. row and column, delete a character, clear the it extracts a penalty in performance since the
screen). Also included is feature information information must be accessed and must be
Applications can create, update and delete (e.g., which attributes are available, what interpreted. In order to minimize the penalty,
named variables. These variables can be local characters. should be used to construct each program described above has included
to a single process or shared at the activity, boxes). Finally, information about what control logic that minimizes the number of times the
user, or system level. Shared variables can strings will be generated by the terminal in data is extracted. Thus the penalty has been
be used independent of dialog applications. response to an operator action is described limited to a front-end cost when the
(e.g., Do key, PF1, Delete character key, etc). applications are invoked.
Note again, that the dialog is stored in a file
outside both the application and the dialog Again, the terminal descriptions are outside The structure outlined here does, however,
manager. The dialogs may be changed the application, and the addition of a new provide a reasonable degree of future
significantly without requiring any terminal type to support requires only the flexibility and the expense in the form of
modification, compilation, or reconstruction of addition of an appropriate terminal processing performance has not proven to be
the application. Dialog definitions are pre- description. excessive. Each layer has provided for future
processed from a readable and editable form extensions by including a flexible external
to one that is more efficient for run-time definition file. The capabilities of the system
processing. Separation of the dialog from the are thus not bound once and for all at the
application is still maintained. time the system is shipped, but can be
extended easily as future needs dictate.

112
References
1. P.J. Kilpatrick and Carolyn Greene, "Restructuring the
AIX User Interface," IBM RT Personal Computer
Technology, p. 88.

113
Extended File Management for AIX

John M. Bissell

Introduction consists of an application programming Field Access

Most major operating systems provide interface (API) and a set of AIX commands for Field access permits an application to define
sophisticated file access methods, with manipulating both AIX and Data Management the contents of a file to the field level. Such a
functions that allow the definition and files. file is a "table," where the rows are records
manipulation of records, structures, and and the columns are fields.
fields. Such functions speed and simplify the Data Access Methods
application programmer's task. Since many A key design decision was to provide both a The column is the basic structural entity in a
applications require random access to traditional record-level indexed sequential table. The creator of the table describes the
records, most comprehensive access access method, and a higher-level field characteristics of the columns of the table.
methods offer some form of indexed access access method which allows records to be The description must include a user name for
to data for improved performance. described and manipulated at the field level. each column and typing information. Column
Both types of files use the same underlying definitions are stored in a specially named
Base AIX file system calls provide only basic data and index structures, but are not totally index (SYSCOLUMNS) in the index file.
byte and string-oriented file manipulation compatible due to the control information that
functions. Applications with a need for more precedes the field data. A row represents a record in a table. A row
complex data structures and retrieval contains one instance of data for all of the
capabilities such as indexing must architect Record Access columns in the table. Field access functions
and implement their own access methods. Record access allows data structures of fixed are used to retrieve, insert, and update
This lengthens the product development or varying length to be stored and retrieved. individual fields within rows.
,.~ycle, cost, and risk. These private access This is the traditional method of file access
methods are typically proprietary and for languages such as PL/I, FORTRAN, and The DMS field access support provides for
unusable by other applications. This results in COBOL. It also lends itself very well to row selection based on complex selection
applications that cannot communicate or be applications development in C, where data criteria, including wild cards. These functions
integrated without some intervening file structures are easily defined and manipulated. provide many of the capabilities of a relational
transform function. In particular, it generally data base on a single table. Field access
makes file sharing impossible and parallel Records may be retrieved sequentially, in the functions automatically optimize query access
updating inevitable. order in which they were added to the file. using indexes where available.
They may also be retrieved directly by
IBM RT PC Data Management Services supplying the relative byte address (RBA) of Indexes
(OMS) extends the facilities of the base AIX the record within the file. By storing the RBA Indexed access for record and field functions
operating system and command interface. It of one record in another, complex data is provided using B-tree techniques [1].
builds on the AIX file system to provide both structures such as hierarchies and networks Integer, short integer, double preciSion
record and field-level access. The AIX can be built. Indexed sequential retrieval is floating point, and fixed and varying length
directory is also expanded to provide accomplished using the index techniques character data are supported as key types.
additional information about files. The product described later. Up to 16 key parts may be defined for each

114
index, with an ascending or descending • I/O errors in the index file can be recovered to contain an unlimited number of indexes.
specification on each part. An index may be by rebuilding the indexes from the data file. Each index block is identified by the RBA of
defined as unique or duplicate. Architecturally, its root node, which is kept constant.
any number of indexes may be defined on a Data Management files are specified by using
file, although a practical limit may be set by an AIX file system path name. This name Another design decision was to use the data
the maximum size of the index file. Each properly refers to an AIX path down through file algorithms for storing index nodes. Each
index is given a user-defined name which is all but the last name. Data Management uses index node is stored as a record in a data
then used to refer to the index in subsequent the path name through AIX to locate the AIX file. The records are chosen to be a multiple
functions. Indexes are automatically updated directory containing the file(s). The files are of the file system block size, minus the space
when insertions, modifications, or deletions always manipulated together as a data set. required by the record header and trailer.
are performed. Relative byte address pointers link the nodes
Data File Architecture of each index to form the characteristic
For record files, each key field is identified by Each data file is defined to contain either B-tree. This scheme allowed use of already
the starting byte displacement of the part fixed or variable length records. Records are available code for free space management
within the record, the type of data, and length located by their RBA within the file. Each and error detection.
of the data. For tables, the names of the record has a 4-byte header containing an ID,
column(s) that comprise the key are used. consistency counter, and a record length. Extended Catalogs
Following the data is a 1-byte ID and The AIX inode structure captures only very
Key compression and prefix B-tree matching consistency counter. When a record basic information about a file, such as
techniques [2] are employed to increase the is written out, its consistency counters are creation date, date of last modification, etc.
number of keys that can be contained in each incremented. Each time a record is retrieved, The only descriptive information that is
index block. The index block size is always its header and trailer consistency counters supplied by the user is the file name. No
chosen to be a multiple of the file system are compared to ensure that all of the record provision is .made for storing user-defined
block size (2K) to provide for efficient access. was written and read correctly. attributes, such as file type, profile, or eyen a
Index nodes are buffered to reduce I/O. An comment as to the contents of the file.
innovative concept called the "level table" is Free space management is done to reclaim
used to further minimize the tree traversals. deleted space. Free areas are chained by Data Management Services provides the
Leaf nodes are chained to provide next and relative size. A request to add a new record ability to create and manipulate an extended
previous sequential retrieval. always finds a free area within one access, or catalog for such information. API functions
else the file is extended. and several utilities are provided. The catalog
File Architecture structure for Data Management files and
Each Data Management file or table consists The RBA of a record never changes, even tables is an extension of the AIX file system
of a data file and an optional index file. Both when the record size is changed. (If a record directory structure. The user views Data
files are standard AIX files. The decision to outgrows its slot, it is moved and a pointer is Management files as being handled the same
use two AIX files instead of storing data and left behind.) This simplifies logic, since as AIX files.
indexes in the same file has several indexes do not have to be updated unless the
advantages: key of a modified record is changed. While extended catalog information is
provided implicitly for Data Management files
• Each file is smaller, which has some Index File Architecture and tables when they are created, normal AIX
performance advantage in AIX. All of the indexes defined on a particular file files and directories do not have any
are stored in a single index file. The file is associated extended information kept on
• Decisions on file strategy (such as whether managed as a "tree of trees" with the names them unless a specific request to catalog
to map or not) can be made independently of the indexes being stored in a B-tree at the such objects has been made through the API
for indexes and data. beginning of the index file. This allows the file functions or the "describe" utility. However,

115
API functions that read data from the catalog installed. The new command names are also addition, a brief comment may be entered
will supply the standard AIX status used by the Usability program [3] to further for the file. The comment is stored in the
information for the non-cataloged files. reinforce their acceptance by users. extended catalog and displayed by the list
utility.
A catalog file is given the special name These new utilities understand both ordinary
".SYSCATALOG". This file is created with the AIX files and Data Management files and • archive/retrieve - used to backup and
same uid, gid, and mode as the AIX directory tables. They also provide a means to query restore all types of files to removable
in which it resides. Thus, if a user has write and update the extended catalog. The utilities media. These commands maintain the
authority on a directory, he also has write give the user a consistent view of files, extended catalog information intact.
authority to add/update/delete entries in whether they are AIX, Data Management, or
.SYSCATALOG. The file structure in an AIX those created by the SQL/RT Data Base LPP. • create - allows creation of AIX, record,
directory containing Data Management files is Although the standard AIX commands are still and field access files.
shown in Figure 1. available, their functions are completely
subsumed by the corresponding OMS utility • recover - used only for Data Management
Utility Aspects of System commands. files that have been determined to contain
Integration of Data Management files and corrupted data, possibly from a system
ordinary AIX files is accomplished from a user The supplied utilities have the following crash.
perspective by the utility commands. Since functions:
Data Management files and tables can consist • condense - used to compress a Data
of two AIX files, the standard AIX utilities • copy - replaces the AIX cp command for Management file by removing imbedded
such as cp, mv, and Is do not understand the copying files. Copy is designed to detect free space.
relationship and special characteristics of file "holes" (blocks of all zeros) and avoid
these files. For this reason, several AIX . physically copying them. This prevents AIX Process Model
utilities. have been supplemented with new from actually allocating any physical space One of the major design decisions in
Data Management utilities. A user need only for the block, thus conserving disk. The developing Data Management Services
learn one set of commands for both types of block materializes as zeros when read. involved the selection of a process model.
files, and in fact does not even need to be The two alternatives examined were a
aware of the difference. The integration i~ = move - replaces the AIX mv command for subroutine library of Data Management
further carried out by having the new renaming files. functions, and a two-task interface. The
command names aliased to existing AIX decision was made to design a two-task
utilities when Data Management is not • delete - replaces the AIX rm command for interface, as shown in Figure 2.
removing files.
Each application process is supported by its
Any AIX
Directory Node • list - is an expanded version of the AIX Is own OMS process. Communication between
command. List provides information from the application and DMS is via the application
the extended catalog for cataloged files. If shared segment. Control is transferred using
the file is not cataloged, inode information semaphores. The reasons for chOOSing this
is printed in the manner of Is. deSign over the standard function library
~
~ L...-_-'
approach were:
• describe - a utility that not only displays
Data Mgmt Catalog Data Mgmt Files
detailed information on a file (including • AIX provides new facilities for interprocess
indexes and columns for OMS files and communication which greatly enhance the
Figure 1 AIX Directory Node with Data Management
tables), but also allows the user to do the ability for cooperating processes to share
Services Files
chown and chmod AIX functions. In data.

116
 Application
An application program containing DMS API 5. The application is enabled, and the return
Process functions is compiled and then linked to a code and any returned data is moved
ASS
P H E library containing the run-time code for the from shared memory to the application
P A G Data Management function calls. Each library address space. The run-time routine then
L R M
E E function is small, and serves only to returns to the application.
D N communicate between the application and the
Data T
Management DMS process. The first time one of these The DMS process resets a timer each time
Process
functions is invoked during execution, a Data the application is posted. If no further request
Management server process is started using is received within several seconds, the DMS
the fork/exec mechanism. A private shared process checks to ensure that its application
segment and a set of two semaphores are parent is still running. If it is not, the DMS
obtained. The DMS process waits on its process commits all updates in process and
AIX File Buffers
semaphore. closes all files. It then removes the shared
memory and semaphores and exits.
Figure 2 Process Model Subsequent interaction between the
application and Data Management processes There is no explicit communication between
• The size of executable applications on disk is as follows: DMS processes servicing different
is reduced, since the amount of linked-in applications. All communication is done
code is small. 1 . The run-time library moves the through data contained within the files
application-supplied parameters and data themselves. Locking using the lockf system
• Memory usage is reduced, since AIX shares buffers from the application address call is used to control concurrent requests for
the text segment of the DMS process space (stack and data segments) to data.. '
among all concurrently executing designated locations in shared memory.
applications. Use of' Extended AIX Features
2. The run-time library routine then posts the Several of the extensions to the base AIX
• Data integrity is enhanced. An abnormally- DMS process by setting one of the system have been utilized by Data
terminated application does not take down semaphores. It then waits on the other Management Services. These features are
the Data Management process. Signals, semaphore. discussed further by Loucks[4].
such as software termination or shutdown,
can be caught and processed without 3. The DMS process is awakened when its • lockf - this operating system call is used
leaving data in an inconsistent state. Also, semaphore is set. It looks in shared to provide file and record locking.
since the address spaces of the application memory to determine the function to be
and Data Management processes are performed, and calls the appropriate • fsync - this operating system call causes
different, application bugs are much less internal routines to process the request. all updated blocks for a specific file to be
likely to corrupt DMS data and control The input data is addressed directly from forced to disk. Data Management Services
structures. shared memory, and is not moved. uses this function to provide commit
processing.
• The model allows for such interesting 4. Upon completion of the request, a return
enhancements as asynchronous I/O, since code is placed in shared memory, and the • fclear - this operating system call is used
the application could be allowed to contir19 application is posted by setting its by Data Management when records are
processing while waiting for Data semaphore. The DMS process then waits deleted, to return blocks of zeros to AIX for
Management to store or retrieve the for another request. reallocation. This feature saves disk space
requested data. when files have many deleted records.

117
• ftruncate - this operating system call is Acknowledgments
used by Data Management to truncate the The author wishes to thank the past and
file size when records at the end of the file present members of the Data Management
are deleted, saving media space. development team for their support and
perseverance through the many requirements,
• mapped files - reads and writes data via design, and code changes which inevitably
the paging hardware and software instead result during an effort of this magnitude. The
of through AIX file buffers. System calls final product reflects the very best of their
with the attendant high overhead of the talents and abilities.
context switch are bypassed by using the
mapped file feature to directly access the I am indebted to Linda Elliott and Cheng-Fong
file as if it were a part of the DMS Shih for their assistance in architecting and
process's address space. designing the file structures and interfaces.
The other members of the development team,
Conclusions comprised of Jeanne Smith, Thuha Nguyen,
RT PC Data Management Services enhances Karen Depwe, Pierre Fricke, Albert (S.Y.)
the capability and application development Chang, and Richard McCue, ensured that the
environment provided by the AIX file system. design was implemented efficiently, and
The supplied API routines allow the definition offered many suggestions which manifest
and manipulation of data at either the record themselves in the quality of this LPP. The
or field level. Integration with AIX is achieved development effort would have amounted to
through a set of utilities that operate on both little without the diligent testing of Wayne
AIX and Data Management files. Wheeler. Many thanks also to Harry Sundberg
for the management direction, planning, and,
The use of Data Management Services frees inSight so necessary for a successful
the application programmer from the time- development project. The origins of the Data
consuming task of defining and implementing Management Services LPP trace back to
a proprietary access method. In addition, the ear!y product definition work done with Jack
application benefits from future function and Olson.
performance enhancements that may be
made to DMS. Extended AIX features are References
exploited to provide improved performance, 1. Douglas Comer, "The Ubiquitous B-Tree," ACM
Computing Surveys, Vol. 11, No.2, June 1979.
media utilization, and data integrity. The
resulting Data Management Services files can 2. R. Bayer and K. Unterauer, "Prefix B-Trees", ACM
Transactions on Database Systems, Vol. 2, No.1,
be shared by multiple applications.
March 1977.
3. Tom Murphy and Dick Verburg, "Extendable High-
The AIX file system is also available for new Level AIX User Interface," IBM RT Personal Computer
or ported applications. An application's choice Technology, p. 110.
of storing data will depend on the need for 4. Larry Loucks, "IBM RT PC AIX Kernel-
functional services: for simple structures, the Modifications and Extensions, IBM RT Personal
AIX file is all that may be needed; for other, Computer Technology, p. 96.
more complex structures, the Data
Management interface is more appropriate.

118
The Virtual Resource Manager

Thomas G. Lang, Mark S. Greenberg, and Charles H. Sauer

Introduction the IBM 5080 graphics hardware, which is • Maximize performance to support real-time
The Virtual Resource Manager, or VRM, is a designed to an IBM System/370 channel process control type applications.
software package that provides a high-level interface.
operating system environment. The VRM was • Allow users to easily customize the system
designed to build upon a hardware base The concept of RISC architecture is the to meet their needs by providing an
consisting of a Reduced Instruction Set minimization of function in hardware, extendable, flexible interface.
Computer (RISC) and a PC AT compatible I/O providing only a limited set of primitives.[2]
channel, although it is not limited to this This allows the processor to be designed with • Provide compatibility with IBM-PC
environment.[1] In fact, the VRM can be easily simplified logic and a corresponding increase applications by supporting an Intel 80286
extended to support different I/O hardware. in the speed of its instruction set. In this coprocessor.
An example of this is the VRM's support of environment, the software must provide
function that traditionally is provided in The approach used to accomplish these goals
hardware, such as integer multiply and divide was to design a Virtual Machine Interface, or
I
1 functions and character string manipulation. VMI, with a set of functions to facilitate the
The VRM builds on this hardware base to: use of a variety of operating systems. The
VMI has features that support concurrency of
'' ill
l~----,.lYAppl;cation pmgram
• Provide a high-level machine interface,
which simplifies the development and
multiple operating systems and applications,
while in'sulating them from most details of the
implementation of operating systems and implementation of the hardware, except for
Operating System their applications. the problem state instruction set. Also, the
l-
Virtual Machine I- VMI allows operating system programmers to
Simple Device Driver Model Device Manager/Driver Model
install extensions to the VRM to support
-VMI---------------
additional I/O devices, or even to replace the
I VM I IBM-supplied I/O subsystems.
s!c svc
Device Drivers and ---+---+----VMI----+---+--- Traditionally, virtual machine implementations
Device Managers have suffered in performance due to the
overhead of simulating hardware function.
Virtual Resource Manager Device Driver J The key to maximizing the performance of the
-Hardware I n t e r f a c e - - - - - - - - - - -
VRM is that the vast majority of instructions
issued by the operating systems and
Processor I I Memory
applications are directly executed by the
hardware. The VRM software is invoked
mainly to handle I/O operations at a relatively
Figure 2 Virtual Device Models high functional level.
Figure 1 RT PC Software Design

119
Fundamental to the design of the RT PC is takes advantage of these features to logically interface to I/O devices that is consistent for
that the VRM is the underlying support layer separate the address spaces of the virtual all devices. Also, the VM I includes provisions
for an operating system. In particular, the machines from each other and from the VRM for bypassing the VRM and accessing devices
UNIX kernel[6] was chosen as the principal address space. directly. The preferred method of using a
operating environment supported by the device from a virtual machine is to take
RT PC product, and the design of the VRM Another VRM feature, related to virtual advantage of the I/O support functions
was influenced by this selection. memory, is "mapped file" support. Mapped supplied by the VRM. But, there are graphics
files are a relation of logical disk blocks to applications, for example, which can gain
The concept of a virtual machine has been virtual memory addresses, such that a disk enough performance by writing directly to a
implemented on IBM mainframe computers file can be read from or written to simply by display device to offset the loss of flexibility
with a software product known as VM/370.[3] reading from or writing to its associated suffered when bypassing the VRM services.
The VRM is similar to VM/370 in that it memory addresses. Explicit disk reading and Another reason for allowing direct access to
supports the concurrent execution of multiple writing is not required. I/O devices was compatibility with existing
operating systems. However, there is a applications; for example, a BASIC language
significant difference. VM/370 provides a The AIX operating system contains a program written using the PEEK and POKE
complete functional simulation of the real complete file system, based on explicit disk functions to access an I/O device.
System/370 hardware, such that an operating reading and writing. When modifying AIX for
system built for the real hardware, like MVS, the VMI, it was desirable to salvage as much Extendable Virtual Machine Architecture
can run in a virtual machine. The Virtual software as possible. Also, the concept of Another feature that distinguishes the VRM is
Machine Interface supported by the VRM mapping files does not work well with the extendability of the architecture. Users of
provides considerably more function than the removable media, such as tapes or diskettes. microcomputers have become accustomed to
RT 'PC hardware; an operating system So, mapped file support is augmented with a plugging new devices into a machine's I/O
implemented to the VMI will not run on the minidisk manager in the VRM, providing more channel. However, getting the machine's
real hardware. The design of the VMI traded conventional file access support. software to use the device usually requires
off complete hardware compatibility for the some ingenuity. One approach is to design
benefits of a high-level, high-function machine The minidisk manager provides access to the new device such that it "looks like" an
definition. disks partitioned into separate spaces, or existing device, so that the existing software
minidisks. In turn, the minidisks are can recognize and use it. Another approach is
Along with the concept of concurrent virtual partitioned into logical blocks whose size is to run an application program that drives the
machines, the VRM supports virtual determined by the operating system, device directly, independent of the existing
memory.[4] The hardware memory independent of the characteristics of the operating system. For example, a program
management capabilities include a 24-bit physical disk. The minidisk manager also could communicate with a. device by sending
address space for real memory (Le., the includes functions not normally found in commands to its I/O port, then using a
ability to address up to 16 megabytes of real simple hardware access methods, such as software "spin loop" to poll its status port to
memory) and a 40-bit address space for error recovery and bad block relocation. determine when the commands complete. The
virtual memory (1024 gigabytes, or one Further, the VMI for the minidisk manager former approach limits the flexibility of the
terabyte).[5] The virtual address space is allows the potential for "remote" minidisks, new device, while the latter destroys the
comprised of 4096 segments of 256 accessed across a communication link such effectiveness of a multiprogramming
megabytes each. Sixteen segment registers as a high speed local area network. operating system by tying up the processor
are provided by the hardware, and one of during I/O operations.
them is permanently dedicated to addressing The "virtual resource" concept is also applied
I/O devices. Thus, up to 15 segments can be by the VRM to I/O devices, such as virtual The VRM allows a new approach, whereby
accessed simultaneously. The VRM software terminals.[7] The VMI includes a high-level software for a new device can be fully

120
integrated into the existing operating system. Attach Reserve a device and "gathered" from different buffers and output
Further, the reconfiguration of the VRM to allocate any resources its to a device.
add or replace software can be performed in software may require.
real time without disrupting the normal Another parameter for the two request
function of the machine. Detach Undo the function of functions is an operation option that
"Attach." determines if the request is to be processed
A data structure, known as a Define Device by the VRM synchronously or
Structure, or DDS, is included in the VMI so Send Command Send a command to a asynchronously. Implicitly, this also
that a programmer can describe the attributes device. determines how completion status is returned
of a new device and its related software to the virtual machine. For synchronous
support to the VRM. Information in the DDS Start I/O A variation on "Send requests, completion status is supplied as a
includes the I/O port address(es) used by the Command," which allows a return code from the requested function,
device, which channel interrupt level it uses, set of commands, or while the completion of an asynchronous
which DMA channel it uses (if any), whether it buffers, to be sent to a request is indicated by a "virtual interrupt".
has any resident RAM or ROM, etc. Also, the device. The VMI defines nine interrupt levels for a
DDS indicates which program module should virtual machine, which allows the assignment
be called to process such functions as: To use a device, a logical connection ("path") of relative priorities to interrupting conditions.
is established between the user and the When not processing an interrupt, the virtual
• Device initialization device. The Attach function is used to machine is considered to be on level 7. Seven
• Interrupt handling establish a path, and a path identifier token is levels can be assigned to interrupting I/O
• I/O initiation returned to the user. Subsequently, the path devices. In order of decreasing priority, they
• Timeout or exception handling identifier is used to send requests to the are levels 0 through 6. In addition, there are
• Device termination device. When the device completes the two other levels. The machine
request, it returns status information or an communications level is used for messages
Using information from the DDS, the VRM is interrupt to the user, using the path identifier between the VRM and the virtual machine.
able to determine which user-installed to route the data. The highest priority level is the program
program to call to handle an interrupt check level, which is used by the VRM to
generated by an installed device. The The VMI defines two ways to send requests report exception or error conditions to the
additional software required to support a new to a device, the Send Command and Start I/O virtual machine. The return code from a
device is added in real time, in contrast to functions. Parameters for these functions synchronous request provides 32 bits of
existing systems that require the use of an include the path identifier in addition to device status, while up to 20 bytes of status can be
off-line or stand-alone program to reconfigure specific parameters such as a request code supplied with each virtual interrupt.
the system. and buffer pointer. The difference between
the two functions is that the latter passes its Two types of programs can be installed into
To use devices, the VMI contains a set of parameters in a data structure, know as a the VRM: device drivers and device
functions including: Channel Control Block, or CCB, which allows managers. A device driver is a collection of
the specification of a chain of commands or subroutines that support a specific hardware
Define Code Install software into the buffer pointers. This can be useful, for device. The VRM synchronously calls the
VRM, or delete installed example, when using a device that supports subroutines to handle device-specific
software. "scatter/gather" functions. During a read functions, such as handling interrupts and
request data can be input from a device and time-out conditions, and processing I/O
Define Device Install a DDS into the VRM, "scattered" into different memory buffers. Or, commands from virtual machines. The VRM
or delete an installed DDS. during a write request data can be device driver support is intended to be

121
sufficient for implementing relatively simple the user. Output to virtual terminals is references by the coprocessor and routes
devices, such as printers, diskette drivers, updated in memory if that display is not them to the VRM's memory. Alternatively, a
and tape drives. selected. memory card can be plugged into the I/O
channel, and coprocessor memory references
Device managers provide an additional level Support of the PC AT coprocessor presented will be directed to it. This allows a great deal
of support for more sophisticated devices, some interesting challenges for resource of flexibility to trade off the lower cost of
such as virtual terminals or communications management.[9] The main constraint was that shared memory against the higher
subsystems (see Figure 2). These types of the VRM had to be transparent to the performance of dedicated memory. The trade
device subsystems typically have applications using the coprocessor. A off is not "all or nothing." For example, a
requirements to handle multiple asynchronous considerable amount of hardware support is 1-megabyte address space can be provided
events and to manage different types of dedicated to this purpose, in the form of for the coprocessor using a 512-kilobyte
resources. For example, the Virtual Terminal "trap" logic that monitors access by the memory card and sharing 512 K of system
Manager coordinates the activities of device coprocessor of I/O addresses.[8] For memory.
drivers for the keyboard, display, speaker, nonshared devices, the VRM reserves the
and locator to simulate a higher level device device for exclusive use by the coprocessor. Virtual memory is utilized by the VRM to
known as a "terminal." I/O operations using devices of this type eliminate arbitrary restrictions on resource
proceed with no further intervention required usage. It is not uncommon for operating
Allocation of System Resources by the VRM. When using shared devices, systems to restrict the number of processes
Resources in the VRM are categorized as however, the VRM must intercept each 1/0 in the system or the number of devices that
serially reusable or shared. Serially reusable operation requested by the coprocessor and are supported. The VRM defines internal
resources are those that can be used by simulate the function as if it were dedicated to control block areas in virtual memory that are
different applications, but only by one at a the coprocessor. For example, when the large enough to support thousands of
time. For example, multiple applications may coprocessor writes data to what it thinks is processes and device drivers. Thus,
use the printer but one application must finish the display screen, the VRM saves this data limitations are a function of the amount of real
before the next takes over. Otherwise, the in a memory buffer. And, when the memory, disk space, and I/O channel slots
result would be scrambled printer output. coprocessor's virtual terminal becomes the available on a particular machine.
Shared resources, though, may be used "active" terminal, the data is moved to the
"simultaneously," Examples include the disks actual display buffer. A!so, at this time Designs for Rea!-Time Performance
and memory, which are shared by dividing keystrokes are routed to the coprocessor The VRM was customized for the real-time
them into logical pieces (minidisks and when it accesses what it thinks is the processing environment, compensating for
segments), and the processor and keyboard adapter's I/O port. Notice that since the shortcomings of the kernel in this area.
communication lines, which are shared on a the coprocessor accesses nonshared devices Features of this design include:
time basis. directly, they perform at precisely the same
speed as they do in a PC AT. However, • Low overhead creation and deletion of new
The VRM manages several shared devices, shared devices suffer some performance processes and interrupt handlers
most notably the keyboard, locator, speaker, penalty since functions must be simulated by
display, and hard files. Virtual machines can the VRM software. • Efficient interprocess communication
have many logical terminals. The user
controls which logical terminal is associated Another resource that can be shared with the • Preemptable processes and interrupt
with the physical hardware via a set of coprocessor is memory. The VRM can handlers, to minimize interrupt latency time
reserved key sequences. Virtual terminal input reserve some of its own memory for use by
is routed by the VRM to the owner of the the coprocessor. In this mode, memory • Prioritized scheduling of processes and
screen that has been selected for display by translation hardware detects memory interrupt handlers

122
• Interval timer support with 1-millisecond process will remain executing until it "waits" program. The remaining time is spent saving
granularity. for some condition (such as the completion of the state of the current program and restoring
an I/O operation or the arrival of a new work the state of the next program.
Multi-programming is implemented in the request), or until it is interrupted. Among
VRM by dividing work into logical units, or processes with the same priority, "time The VRM was designed using top-down
"processes," which are scheduled by priority. slicing" is implemented; that is, if a process structured programming techniques. The
In addition, the VRM contains "interrupt does not relinquish control after a period of program code was written first in a high-level
handlers," which are invoked in response to time, the VRM will suspend it and pass language, using primarily PL.8 (an internal
interrupt signals from hardware devices. In control to another process. The default time IBM development language, derived from
"Extendable Virtual Machine Architecture" on slice interval is 16 milliseconds, and this value PL/I).[10, 11, 12] After the system was
page 120, programs in the VRM were may be increased in increments of 16 functioning to the point where meaningful
characterized as device managers or device milliseconds. If a sufficiently large increment applications could be implemented and run,
drivers. Device managers, and virtual is selected, time slicing is effectively disabled. the performance of the system was measured
machines, are represented as processes in in detail. The performance data was used to
the VRM, while interrupt handlers are among The design of the data structures for determine critical paths in the software, or
the subroutines that comprise a device driver. multiprogramming was influenced by "bottlenecks." These parts of the system
performance considerations. The processor were then tuned to maximize performance.
Processes and interrupt handlers can has a large number of registers (16 system The first step in tuning was to attempt to
communicate using shared memory, or by registers, 16 segment registers, and 16 make the PL.8 code more efficient. In many
using the VRM's interprocess communication general-purpose registers), which makes cases, this tuning turned out to be sufficient
functions, which include queues (for message context switching between applications a to meet performance objectives. However,
passing) and semaphores (for serialization lengthy job. In a typical operating system, some critical paths required recoding in
and synchronization). when an interrupt occurs, the state of the assembler language to achieve desired
interrupted program is saved in a known performance.
Particular emphasis was placed on supporting location, then transferred to a control block
high-speed devices, with stringent latency associated with the interrupted program if it The process of tuning the system was an
time requirements. Hardware interrupt becomes necessary to switch control of the iterative one for the measurement and
processing is the highest priority work in the processor to a different program. In the VRM, recoding steps. For example, one
system. Interrupts from devices are further this would require moving a large amount of performance objective was that the disk
divided into four priority classes, such that the data, so the interrupt handlers are set up device driver be able to handle a disk
servicing of an interrupt can be preempted by such that the state of an interrupted program formatted with a 2:1 interleave factor without
a higher priority interrupt. is saved directly into its control block. This missing revolutions, with enough of a margin
contributes to faster context switching. to allow for an interrupt from an Async
Also, an "off-level" interrupt handler communications adapter during the critical
capability is available that allows a device Another aspect of the control block design path. A factor that increased the difficulty in
interrupt handler to process time-critical that contributes to fast context switching is meeting this objective was the disk hardware,
operations without being preempted, and to that the "dispatcher," which selects which which does not support DMA for transferring
defer less critical processing to a lower program next gets control of the processor, data between the adapter and memory. The
priority level that can be preempted by other never has to search through queues of disk hardware, chosen mainly on cost and
device interrupts. control blocks. The control blocks for compatibility considerations, is similar to the
programs that are ready to execute are PC AT disk hardware. Using that hardware,
After all pending interrupts are handled, the always kept sorted by priority, thus only the PC AT supports a 3:1 interleave.
VRM selects the next process to execute about 1% of the total time required for a
based on 16 priority levels. The selected context switch is required to select the next

123
In pursuit of the 2: 1 objective, the VRM device drivers. In particular, the overlapped The third technique involved a logic analyzer
interrupt handling logic and disk device driver processing of queued requests increases the to monitor the output of signals from the
were measured and recoded numerous times, throughput of all devices. processor Chip. Using the analyzer, it is
each time squeezing out a few more possible to measure precisely the time it
microseconds from the path length, until the Critical to the job of performance tuning was takes to execute individual instructions or
objective was met. At several stages in the accurate measurement of the system. Three sequences of instructions. This is impractical
process, software ingenuity was required to different techniques were used. First, selected for measuring large programs, but is well
surmount hardware timing limits. Some of operations were executed repetitively, so that suited for analyzing small sections of program
these software "tricks" included: elapsed time could be measured. The code that are executed very frequently. For
measurement device was a stop watch, so to example, program context switching and
• Sorting the queue of disk requests eliminate reaction-time errors and to increase interrupt handling functions execute hundreds
according to sector/track number, accuracy, the repetition factors were chosen of times per second. In these critical paths, a
influenced by the current position of the to be very large (e.g., thousands or even few microseconds can be significant.
disk arm millions of iterations). Some of these "bench
mark" loops were internally developed, while A great deal of performance tuning effort was
• Looking ahead in the queue when one others were selected from bench marks spent maximizing the "pipeline" effects of the
request completed, to anticipate the published in trade journals. The latter type of ROMP processor. The pipeline effects result
requirements of subsequent requests bench mark was especially useful when from the processor's ability to overlap various
comparing performance of competing stages of instruction execution. Two different
• Sending the next command to the disk systems. situations illustrate these effects. First, if the
adapter before processing of the current next instruction(s) after a memory load
command is complete The second type of measurement was done instruction do not use the value being loaded
by inserting "hooks" into critical paths. These from memory, they may be executed in
• Using a table look-up algorithm to hooks consist of I/O instructions that output parallel with the memory access. By properly
determine how long a "seek" operation data to reserved channel addresses. To interleaving instructions, this effect can be
should take, based on current and future obtain measurements, a special I/O adapter is exploited to reduce the total execution time of
arm position. then setting a timer to wake plugged into the channel to monitor the a sequence of instructions. Second, when a
up the disk diivei just piioi to the operation output from the hooks. The data collected by branch instruction is executed, the processor
completing this adapter is saved on a tape. Afterwards, must reload its instruction pre-fetch buffer
the tape is input to a data reduction program with the new instruction stream. By using the
• Taking full advantage of the overlapped that generates a path flow analysis with processor's Branch-with-Execute instructions,
load, store, and branch capabilities of the timings. This technique allows very it is possible to overlap the execution of one
pipelined processor. sophisticated path analysis, but suffers the instruction with the pre-fetch buffer reload
drawback that the hooks themselves take a time.
In this extreme example, the large tuning small amount of time to execute. Although the
effort paid off when a difficult objective was hook execution time is relatively small, the The high level language compilers for the
met. Fortunately, most other tuning problems cumulative times can, in some cases, add up RT PC, in particular the PL.8 compiler, are
were easier to solve. Also, there were "spin- to a significant amount. Also, as the interval designed to take advantage of the pipeline
off" benefits gained in the disk driver tuning. between hooks decreases, the hook's effects of the processor. For assembler
The path length reductions in the VRM execution time becomes proportionately more programmers, the pipeline effects can be
common interrupt handling logic benefitted all significant. utilized, although usually at the cost of cleanly
device drivers, and some of the techniques structured programming. For the tightly
used in the disk driver were applied to other optimized critical paths in the VRM this has

124
been done, but the programming effort software was developed by Lynn Rowell's
required, contrasted with the high efficiency department. The RAS and Install were
of the compilers, has resulted in the majority developed by Hira Advani's department. The
of the VRM being implemented in high-level VRM device drivers were developed by Mark
language. Wieland's department. Special thanks go to
Joe Corso and each member of his
Conclusions department thoughout the VRM development
The VRM builds upon the low level RT PC for the VRM design, the testing methodology,
hardware interface to provide a high-function and the technical leadership for integration of
system environment. It brings to a desk-top the product.
microcomputer many features that formerly
were found only on much larger, more References
expensive systems, such as virtual memory 1. George Radin, "The 801 Minicomputer," IBM Journal
of Research and Development, 27, pp. 237-246,
and virtual 110 subsystems. It also includes
May 1983.
features, such as dynamic reconfiguration and
2. D.A. Patterson and C.H. Sequin, "RISC: A Reduced
an extendable architecture, which are unique; Instruction Set Computer," Proc. 8th Annual
and it allows for the migration of existing Symposium on Computer Architecture, May 1981.
UNIX and IBM PC based applications to a 3. R.A. Meyer and L.H. Seawright, "A Virtual Machine
new architecture. Time-sharing System," IBM Journal of Research and
Development, Volume 9 Number 3, 1970.
During the past several years of development, 4. J.C. O'Quin, J.T. O'Quin, Mark D. Rogers, T.A. Smith,
the RT PC hardware underwent several major "Design of the IBM RT PC Virtual Memory Manager,"
changes, but the Virtual Machine Interface IBM RT Personal Computer Technology, p. 126.

has remained relatively stable throughout this 5. P.D. Hester, Richard O. Simpson, Albert Chang "IBM
RT PC ROMP and Memory Management Unit
time, thus minimizing the impact of the
Architecture," IBM RT Personal Computer Technology,
hardware changes to the implementation of p.48.
AIX and its applications. 6. Larry Loucks, "IBM RT PC AIX Kernel -
Modifications and Extensions IBM RT Personal
The VRM's functions complement the Computer Technology, p. 96.
hardware instruction set, providing features 7. D.C. Baker, G.A. Flurry, and K.D. Nguyen,
such as virtual memory, virtual devices, "Implementation of a Virtual Terminal Subsystem,"
minidisks, and multi-programming. This IBM RT Personal Computer Technology, p. 134.
creates an environment for implementing 8. John W. Irwin, "Use of a Coprocessor for Emulating
operating system extensions and hardware the PC AT," IBM RT Personal Computer Technology,
p.137.
device support that has the flexibility to
9. Rajan Krishnamurty and Terry Mothersole,
evolve as the hardware technology evolves
"Coprocessor Software Support," IBM RT Personal
without forcing radical changes to existing Computer Technology, p. 142.
software. 10. M. Auslander, et aI., "An Overview of the PL.8
Compiler," ACM, 0-89791-074-5/82/006/0022.
Acknowledgments 11. Alan MacKay and Ahmed Chibib, "Software
The authors would like to acknowledge the Development Tools for ROMP," IBM RT Personal
efforts of the people who contributed to the Computer Technology, p. 72.
development of the VRM. The virtual terminal 12. M.E. Hopkins, "Compiling for the RT PC ROMP," IBM
RT Personal Computer Technology, p. 76.

125
Design of the IBM RT PC Virtual Memory Manager

J.e. O'Quin, J.T. O'Quin, Mark D. Rogers, TA Smith

Design of the RT PC Virtual Memory machines, the ability to define both the virtual in real memory is to be transferred to the
Manager address space and the effective address secondary storage device. The clock page
Support of a large virtual address space was space. The VMM provides services such as replacement algorithm is used by the VMM to
the main objective that guided the design of create segment and destroy segment that select this page. Here the real page frames
the Virtual Memory Manager (VMM). The allow a virtual machine the ability to define are examined in a circular or clock-like order.
VMM should take advantage of the large the valid subset of the virtual address space. A frame is selected for replacement if the
address space provided by the Memory It also provides services such as load data in it has not been referenced in the last
Management Unit (MMU) and the abilities segment register and clear segment register cycle through the page frames. The
inherent in the MMU's inverted page table. that control the relationship between the "referenced" indicator is reset if the data in
Furthermore, the VMM needed to be effective address space and the virtual the frame has been referenced, and the next
designed to minimize the overhead associated address space. frame is then examined.
with performing disk I/O. At the same time,
the VMM should not adversely impact system The MMU translates a virtual address into a The secondary storage device used by the
performance, especially in situations where real address within a 24-bit real address VMM is the disk. One or more disks may be
sufficient real memory exists to perform the space. The real address space may not be used for paging. Also, paging I/O may be
desired function. big enough to contain all of the pages defined concurrently active on each of the paging
in the virtual address space. Therefore, both disks.
Each instruction executed by the ROMP has real memory and a secondary storage device
direct addressability to a 32-bit address are used to contain all of the virtual pages. Virtual Memory Data Structures
space. This is referred to as the effective There are three primary data structures
address space. The effective address space A page fault interrupt results when an associated with the VMM. They are the
is divided up into 16 equal size segments by instruction references a memory location that segment table, the external page table, and
the MMU. The MMU converts an effective is not defined in real memory. The second the inverted page table (see Figure 1).
address into a virtual address by main function provided by the VMM is the
concatenating the 12-bit segment identifier page fault handler and it is the part of the Virtual memory is divided up into segments. A
associated with the selected segment onto system that is responsible for resolving page segment represents an objeet suph as a
the 28-bit segment offset in the effective fault interrupts. The job of the page fault program, a mapped file, or computational
address. This results in a 40-bit virtual handler is to assign real memory to the data. A segment identifier can be thought of
address space. Each segment in the virtual referenced virtual page and to perform the as the short form of an object name. The
address space is further divided up into necessary I/O to transfer its data into that segment table defines the objects that can be
2048-byte pages. This division of the virtual real memory. This is known as demand referenced at any moment. It contains
address space into segments and then into paging. information such as the segment's size and
pages is known as paged segmentation. the start of the segment's external page
All of real memory may become filled with table. The segment table contains one entry
One of the two main functions of the VMM is code and data. When this happens, the page for each segment and it is not pageable.
to provide its users, primarily virtual fault handler must select which page of data

126
Segment Table Real memory is divided up into 2048-byte makes it feasible to map a system's entire
Page 0 XPT page frames. A page frame can be thought of
Page 1
data base using a single set of virtual
for
Segment as a container for a virtual page. The Inverted addresses (the "one-level" store). With a one-
N Page Table (IPT) defines the virtual page that level store each segment can be large enough
Segment N
is currently associated with each page frame. to represent an entire file or collection of
Page 0 XPT The MMU uses the information in the IPT data.
Segment M Page 1 for
Segment when translating a virtual address into a real
M address and when determining if a protection This is possible because the address
violation has occurred[2]. The MMU will translation hardware only needs the location
respond with a page fault for any virtual of pages that are present in real memory. If a
Inverted Page Table memory reference that cannot be translated page is not present, the hardware must
using the information in the IPT. The IPT detect this fact, but it does not require the
contains one 32-byte entry for each page secondary storage address. The VMM does
Page Frame for Segment M
frame and is not pageable. need this information, however. Hence, the
VMM must keep this information in some data
Page Frame for Segment N Support a Large Virtual Address Space structure that is associated with the page. In
Virtual memory extends the power of the VRM this data structure is the external
computer memory by expanding the number page table. Unless this external page table is
of memory addresses that can be pageable, the advantage of the inverted page
Figure 1 Virtual Memory Data Structures represented in a system while relaxing the table is lost, because the pinned real memory
limitation that all addressable memory must requirements become proportional to virtual
A segment is divided up into 2048-byte virtual be present in real memory. The address memory size.
pages. A virtual page can be located in real translation hardware requires page tables
memory or on the disk. Each segment has an fixed in real memory to perform its function. Large and Sparse Segment Support
external page table (XPT) with one 4-byte The size of a conventional page table is The VMM supports segments of up to 256
entry for each of its virtual pages. The XPT proportional to the size of the virtual address megabytes. The VMM defines any segment
entries for a given segment are in contiguous space, placing a practical limit on the address that is one megabyte or larger to be a "large"
virtual memory and are therefore directly space size. segment. A large segment can be totally filled
addressable. An XPT entry describes the with data, assuming sufficient disk space. A
characteristics of its corresponding virtual Paged segmentation is a means of reducing large segment may also be lightly filled with
page, such as its protection characteristics this overhead. It takes advantage of the data that is scattered throughout the
and its location on disk. The XPT is pageable. grouping of related data in virtual memory by segment. This is known as a sparse segment.
representing page table data separately for
There is a pool of external page table entries each segment. This allows space savings for The external page table for a large segment
defined in the VRM [1] segment. The size of short or unused segments of the address can itself be fairly large. An XPT entry defines
this pool limits the size of the virtual address space. 2048 bytes of virtual memory. A page of XPT
space. The XPT for each defined segment is entries contains 512 of the 4-byte entries and
contained within this pool. The XPT for the An inverted page table further expands the defines 1 megabyte of virtual memory.
VRM segment defines each page in the VRM range of addressability by reducing the real Therefore, 256 pages of XPT entries are
segment, including the pool of XPT entries. memory overhead required to support a very required to define a 256-megabyte segment.
The subset of the VRM segment's XPT that large virtual address space. Since an inverted
defines the pool of XPT entries is referred to page table contains an entry for each page of Since the XPTs are pageable and reside in
as the XPT of the XPT. It is not pageable. real memory, its overhead is proportional to virtual memory, a subset of them describe the
real rather than virtual memory size. This XPT area itself. These are the XPT of the

127
XPT. One entry in the XPT of the XPT defines VM M critical sections are serialized by VMM, in the area of performance, is to
a page of XPT entries or one megabyte of executing them as the lowest priority interrupt efficiently schedule disk requests so as to
virtual memory. The XPT of the XPT for a handler. This places them lower in priority minimize seek time. This is done by
256-megabyte segment need only contain 256 than all I/O interrupts and higher in priority attempting to write pages to nearby disk
entries, which require only half a page of than all processes. Due to the characteristics blocks, and, when reading them back in, to
memory. Therefore, the size of the XPT of the of VRM interrupt handlers, this ensures that read more than one page at a time. The act
XPT required to define a large segment is paging I/O completion interrupts and VMM of writing pages out to nearby locations on
significantly smaller than the XPT for that services are serialized with respect to each disk may be called "pageout affinity", while
segment. other. the act of reading more than one nearby page
at once is called "prepaging".
The VMM takes advantage of the XPT of the In order to support a large virtual address
XPT in its support for large and particularly space it is desirable that some of the VM M Pageout I/O Affinity
for large, sparse segments. For example, only data structures are pageable. Therefore, the Page faults tend to happen in bursts; that is,
the XPT of the XPT is initialized for a new VMM interrupt handler was extended to when a process is first invoked, it will "fault
segment. This decreases the number of support the concept of backtracking with in" its "working set". It is desirable to have
pages that are initialized for a 256-megabyte careful update. A page fault within a VMM enough free page frames available to satisfy
segment from 256 to 1, thus decreasing the critical section causes the critical section to a "typical" burst of page faults. Not having an
overhead when creating large segments. be exited and makes the process that initiated available free page frame can cause a
the critical section wait for the page fault to process to wait on both a pageout to free a
Serialization be resolved. The process is allowed to retry page frame and a pagein to bring in the
It is useful to describe the VM M in terms of executing the VM M critical section upon desired page. The page replacement
the states of the objects it manages. The resolution of the page fault. This is algorithm will select more than one page at a
most important such objects are virtual pages backtracking. Careful update implies that all time to pageout, in order to maintain this
and page frames. Each of these objects VM M critical sections must be coded such threshold of available free page frames.
always has a well-defined state. Updates to that all VM M data structures that are changed
the data structures that record these states are left in a consistent state whenever the Careful management of paging space can
must be logicaiiy seriaiized with respect to critical section can be exited, either by take advantage of the above characteristics
system events that require that the data completing the service or by page faulting. of the page replacement aigorithm to reduce
structures be accessed or changed. Such Backtracking with careful update serializes the I/O time associated with writing out pages
events fall into three categories: the page fault handler with the VMM services. to disk. This is achieved by always allocating
paging space at pageout time. If a disk
• Page fault interrupts I/O Management address is already assigned to a page, that
• Paging I/O completion interrupts The VMM attempts to manage disk I/O in address is freed and a new one allocated.
• Calls to VMM services such a way as to compensate for the Furthermore, a circular allocation algorithm is
imbalance between the high speed of the used. This means that two pageouts in a row
Without this serialization, the VMM would be processor and the relatively low speed of the will most likely be to adjacent locations in
unable to use these data structures safely. It disk. This entails adding complexity to the paging space. This concept of "late
must ensure that all accesses to these data page fault handler and to the disk I/O routines allocation" also makes it possible for the
are made within a "critical section." On entry in order to decrease the average I/O time VM M to better know where the disk arm is
to a critical section all objects must be in well- required to perform a disk I/O or to eliminate located at that moment, and to find the
defined states. Code running in the critical disk I/Os altogether. paging space with the arm closest to it.
section can perform state transitions, as long Taken together these things tend to reduce
as it leaves all these objects in valid states on Disk Affinity the seek and rotational delays associated with
exit. One of the more important concerns in the VMM disk I/O operations.

128
 Prepaging stolen by the page replacement mechanism corresponding "page fault cleared" virtual
When a segment is written out via the purge when there are no free page frames available, interrupt when 110 is complete for the page
page range service, it is probable that the the size of the disk cache is directly fault. This allows the virtual machine the
data in this segment is related; that is, it is proportional to the size of real memory and ability to dispatch another task while the
data for a program, or it is a program itself. the level of system activity. faulting task waits for the "page fault
When this program runs, it will start page cleared" virtual interrupt. This is known as
faulting on the segment that was written out. The VRM allows the disk to be accessed via asynchronous page fault processing since the
Some, or all of these page faults may require minidisk manager[1] 110 operations and via entire virtual machine is not forced to wait.
disk reads. Since the pages were placed near the VMM. The VRM enforces the following
one another on the disk at pageout time, it is rules to ensure that the disk cache is Page fault notification virtual interrupts are
reasonable to assume that in a lightly loaded synchronized with minidisk operations. First, a under the control of the virtual machine.
system the disk arm would not have to move write to a minidisk may cause an entry to be Therefore a virtual machine that executes
much in order to read back all the pages. purged from the disk cache. Secondly, closing only a single task can disable page fault
This assertion breaks down if some other a minidisk may cause all of the entries in the notification interrupts and leave all page fault
disk 110 request is processed between the disk cache associated with the minidisk to be processing up to the VMM. Here the virtual
faults on the segment, thereby moving the purged. machine's page faults would be processed
disk arm away from the area where the synChronously. Similarly a multi-tasking virtual
segment resides. In order to counteract this Special Topics machine can disable page fault notification
problem, a "prepaging" policy is used in the The design of several of the functions interrupts in selected critical sections when
page fault handler. What this means is that provided by the VMM were greatly influenced preemption is undesirable.
when the VM M processes a page fault that by the virtual machine concept and by specific
requires a disk read to resolve, it will attempt attributes of the AIX operating system. Mapping of Files
.to read in pages that are nearby on the disk, Usually, the data in a segment does not
and in the same segment as the one faulted Asynchronous Page Fault Processing persist beyond the execution of a program.
on. Prepaging will also work for segments Typically in a paging system a process is The VMM allows the data contained within a
that are mapped to a file system, when the forced to wait until all 110 required to resolve segment to be associated with files in the
file system disk blocks are either contiguous, a page fault is complete. Other processes are virtual machine's file system, thus allowing
or close together on disk as is often the case. allowed to execute, but the faulting process that data to exist after the execution of a
must wait until it can successfully execute the program. This association of file data with
Disk Cache faulting instruction. This is known as virtual pages is achieved through mapped
The VMM maintains a write-through disk synchronous page fault processing. files.
cache that is under control of the page
replacement mechanism. This disk cache can Synchronous page fault processing is not The map page range service is provided to
be thought of as a dynamic RAM disk that is desirable when a multi-tasking virtual machine allow a virtual machine the ability to create a
managed by the VMM. Unmodified file system appears as a single process to the VMM. The "one-level store" environment or a subset,
pages, when released, are placed into the multi-tasking virtual machine may have other such as mapping an individual file. This
disk cache. When a page fault occurs that tasks that can execute while the faulting task service is necessary because neither the
might require a disk read to resolve, the page waits for the page fault to be resolved. The operating system executing in the virtual
fault handler first looks in the disk cache to VRM solves this problem by informing the machine nor the VRM have the capability by
see if the contents of the desired disk virtual machine about page faults via machine themselves to map a file. The virtual machine
address reside in the cache. If so, that page communications interrupts. The VMM does not have access to the VM M tables and
is "reclaimed" from the disk cache, and no generates a "page fault occurred" virtual the VRM is designed to be independent of the
110 is required. Since cache entries may be interrupt for each page fault and a virtual machine's file system structure. The

129
map page range service provides the virtual speed of the operation, the two address References
machine the ability to tell the VMM the spaces are equivalent to the virtual machine. 1. Thomas G. Lang, Mark S. Greenberg, and Charles H.
Sauer, "The Virtual Resource Manager," IBM RT
relationship between a logical entity, such as The data in the two address spaces need Personal Computer Technology, p. 119.
a file, and its location on the disk. only be equivalent during the time between
2. P.O. Hester, Richard O. Simpson, Albert Chang, "IBM
the fork and the exec. Much of the data may RT PC ROMP and Memory Management Unit
Scheduler Paging Control be un referenced when an exec follows a fork, Architecture," IBM RT Personal Computer Technology,
Thrashing is a term commonly used to and such data is never actually copied. p.48.
describe a system that is spending most of
the time paging and little time performing Conclusion
useful work. The VMM maintains information The VMM simplifies the design of advanced
in the virtual machine's page 0 that can be applications and operating systems, reduces
used by the virtual machine's scheduler to I/O costs, and complements the hardware's
detect thrashing. The scheduler can ability to support a large virtual address
periodically examine this information to space. Advanced applications and operating
determine how many concurrent tasks it will systems are supported by the following VM M
allow to be active. services:

The scheduler may determine that the system • Demand Paging in a Virtual Machine
is thrashing and decide to reduce the number environment
of active concurrent tasks by quiescing one • Asynchronous page fault processing
or more of them. The VMM purge page range • Mapped files
service provides the scheduler an efficient • Scheduler control information
method to swap out a task's current working
set. This can result in the pageout I/O affinity The cost of VMM disk I/O is reduced by:
benefits discussed earlier. Furthermore, the
task may also benefit from prepaging when it • Pageout I/O affinity
:- --,...-"": ... _.&.t"' .....
Ii:) I vClvLlVClLvU.

• Disk caching
Delayed Copy
Typically, the AIX operating system executes Finally, the VMM meets its major design
a program by using the fork system call to objective of supporting a large virtual address
copy the process's address space and the space. The VMM takes advantage of the
exec system call to load and execute the inverted page table by defining an external
program in the new copy of the address page table that has very small entries and
space. The copying of the address space can that is directly addressable. Backtracking with
result in unnecessary processing and I/O careful update allows efficient support of a
delays when followed by an exec system call, pageable external page table. Together, they
since the exec system call will overwrite the greatly reduce the VM M data structure
just copied address space with the new overhead associated with each page of virtual
program's code and data. Therefore, the memory.
VMM's copy segment service attempts to
delay copying data until the data is actually
referenced, and with the exception of the

130
The IBM RT PC Subroutine Linkage Convention

J.C.O'Quin

Introduction Good programming style suggests that stm r6, -save(r1) # save modified
A subroutine linkage convention is a set of programs be decomposed into small routines. non-volatile
rules concerning the machine state at System design should encourage this practice regs
subroutine entry and exit. Because these by providing an efficient call mechanism. This cal r1, -framesize(r1) # adjust stack
rules are generally understood by compiler is particularly important for "reduced pointer
writers and assembly language programmers, instruction set" machines, which emulate
it is possible to call separately compiled some higher-level instructions in software.
functions and get meaningful results. Since The IBM ROMP microprocessor uses
knowledge of these conventions pervades the "extended opcode" subroutines to perform 1m r6, framesize-save(r1) # restore caller's
system, it is important that they be carefully such functions as storage move, integer regs
evaluated before introducing a machine with a divide, and floating point operations. brx r15 # branch to
new instruction set. Mistakes in this area return point
usually cannot be remedied in future releases. A properly deSigned computer's performance after
is primarily limited by its memory bandwidth cal r1, framesize(r1) # restoring the
This paper discusses some important design requirements. One effective method of . stack pOinter
decisions reflected in the linkage convention eliminating storage references is to keep
used by the IBM RT PC system. Details of intermediate data in fast CPU registers. The The "Load Multiple and Store Multiple"
this interface are described in section 6 of the IBM ROMP microprocessor has 16 general- instructions (LM and STM) provide an efficient
IBM RT PC: Assembler Language Reference purpose registers for this purpose, and mechanism for saving some of the caller's
Manual [1]. The initial release provides instructions with only register operands are registers. By convention, registers r6 through
compilers for C, FORTRAN, Pascal and much faster than those involving storage r14 must be preserved across the call. The
BASIC, which all support this common linkage references. This is true of all existing stack pointer register (r1) must also be
convention. processors to varying degrees. Although restored. This avoids forcing the caller to
mainframes with very large data caches reload register variables and temporary data
Performance Considerations provide relatively inexpensive storage after every call. Research with the PL.8
The subroutine call mechanism materially references, their register operations are still compiler has demonstrated the benefits of
affects system performance. Studies have faster. A primary deSign goal of the RT PC preserving some, but not all, registers across
shown some UNIX programs spending as linkage interface is to minimize the number of calls.
much as 20% of their CPU time in call/return storage references when calling a subroutine.
linkage code [2]. Other factors, such as the The called routine will save only the registers
number of registers available for allocation Function Prologue and Epilogue it modifies. If it can perform its entire job
and optimization can have dramatic second- When the framesize is less than 32,768 bytes, using only registers rO through r5, no
order effects on the quality of compiled code. the function entry and exit code is very registers need be saved. If registers r13, r14,
straightforward: and r15 are modified, but r6 through r12 are
unused, then r13 would be specified in the
STM and LM instructions in place of r6.

131
Register r1 was chosen for the stack pointer Parameter Passing support programs like "printf". This is
because the Load Multiple and Store Multiple resolved by allowing C programs to view their
instructions address registers from the first C Language Compatibility Requirements arguments as a storage array with each
operand through register r15. This means that Languages that permit a linkage editor to argument aligned to a full-word boundary.
these instructions can be used within a ensure that actual parameters and formal Space for this array is allocated in the stack
routine without disturbing the stack pointer. parameters agree in number and type by the caller, but it does not store the first
These instructions are particularly valuable for improve not only program reliability, but also four words in the stack. Instead, these values
performing large block moves. performance, since the parameter passing are passed in registers r2 through r5. If the
mechanism can be tailored to specific subroutine takes the address of some
The fact that r1 is not saved and restored argument types. For example, it would be parameter, it must store these registers in the
across the call by the STM and LM in the possible to pass floating pOint arguments in stack space provided. Then normal C pointer
function prologue and epilogue is no the floating point registers. arithmetic will give the expected results.
disadvantage, because the "Compute
Address Lower" instruction (CAL) does the Unfortunately, the C language permits actual Some compilers may elect to store all
job more efficiently. In fact, the "Branch parameters to differ from formal parameters arguments except those explicitly declared
Register with Execute" (BRX) completely in both number and type. Some C programs "register". This is easy to implement, and
overlaps restoring the stack pointer with the address their arguments as an array in surprisingly effective. Most of the functions in
instruction fetch for the return branch. If a storage. This is an easy way to handle a the standard C library and in the AIX
subroutine does not require a stack frame, it variable number of arguments. The standard operating system kernel benefit from this
need not update r1 at all. This means that C library function "printf" is the archetypal simple strategy.
small routines can be coded with no prologue example of this, but there are others; and
or epilogue; the minimum call overhead is just UNIX System V provides a "varargs.h" The registers selected for passing arguments
a branch out and a branch back. The system include file in the standard distribution, which are not preserved across function calls
call interface routines and the "extended tends to encourage people to do this. Even because argument expression values are
opcod'es" (such as move and divide) fall into though this practice can be considered non- often not needed after the call.
this category. It is also possible for optimizing portable, there seem to be enough programs
compners to avoid prologues and ep!!ogues I)sing it to make supporting it worthwhile. FlJnctiOrl Values
for some smaii routines. Function vaiues are returned in a register,
Passing Parameters in Registers making them available for immediate use in
Note that there is no in-line check for stack Within a single source program, register the enclosing expression. A subtle advantage
overflow. The IBM RT PC AIX operating allocation is the compiler's responsibility, is gained by using r2 for this purpose. This
system uses page fault interrupts to detect although C programmers may provide register no longer contains any of the caller's
overflow. A 256M-byte segment of the guidance via "register" declarations. When a data, and it is not unusual to pass a function
address space is reserved for each process's subroutine call occurs, the linkage convention value as an argument to another subroutine.
stack. This segment is "inverted", meaning interacts strongly with register allocation.
that it grows towards lower-numbered Expressions have been evaluated as Functions return their values according to
addresses. The stack segment is arguments for the subroutine. We would like type:
automatically extended on demand, until a to pass their values in registers to avoid
1M-byte limit is reached, at which time the storage references in both the caller and the • int, long, short, pOinter, and char values
process receives a memory fault signal. subroutine. are returned (right justified) in r2.

There is a conflict between our desire to pass • double values are returned in r2 and r3.
values in the registers and the need to

132
• structures are returned in a buffer allocated able to gain substantial performance
by the caller, the address of which was improvements by further tuning the call
passed in r2 as a hidden first parameter. interface. This would have been impossible
This means that the first actual parameter had microcode changes to a high-level call
word will be in r3 and that all subsequent instruction been required.
parameters are moved "down" one word.
The fact that the deceptively Simple problem
This structure return scheme has the of calling a subroutine turns out to have many
advantage of being reentrant. A function hidden complexities may come as a surprise
returning a structure can be called recursively to some. The conflicting semantics of various
from a signal handler at any time without programming languages make it difficult to
mishap. It also permits optimization of arrive at a final solution to this problem that
assignment statements such as "s = foo(x);" can be etched forever in silicon.
to return the result in the desired location. Its
disadvantage is that a caller who does not Acknowledgments
want the returned value cannot omit the These ideas grew out of years of research
function declaration, since int would be and experiment on several different
assumed in that case. The advantages seem compilers. Major contributions were made by
to outweigh this disadvantage. Incompatible Marc Auslander, Jim Christensen, Martin
declarations are likely to fail nearly every Hopkins, Mark Laff, and Peter Oden:
time, whereas small timing windows in which
certain types of signal must not be received References
are much more difficult to discover and 1. IBM RT PC: Assembler Language Reference Manual.
IBM Corp., document number SC23-0815-0.
debug. In practice, these potential
incompatibilities do not seem to cause 2. S.C. Johnson and D.M. Ritchie, "Portability of C
Programs", The Bell System Technical Journal,
trouble. Vol. 57, No.6, Jul-Aug 1978, p. 2044.

Summary
It is possible to pass parameters in the CPU
registers and still maintain compatibility with C
programs that use techniques like those
provided in "varargs.h". The result is a
speed-up in CPU time for system code of
about 15% compared to an earlier
implementation that passed all parameters in
the stack.

Linkage interface experience on the RT PC

project points out a major benefit of reduced
instruction set machine architectures. Even
after years of research compiling to the
ROMP microprocessor and similar instruction
sets, as late as December 1984, we were

133
Implementation of a Virtual Terminal Subsystem

D.C. Baker, G.A. Flurry, K.D. Nguyen

Introduction controls to switch physical displays, fonts, devices have to be shared in some fashion to
This article describes the IBM RT PC Virtual and terminal characteristics. minimize system cost and maximize operator
Terminal Manager subsystem, which is part of convenience.
the Virtual Resource Manager. The The classic teletype model has several
subsystem provides terminal support for the limitations in the AIX environment. Consider The existence of multiple thread environments
RT PC virtual machine environment. multiple processes writing to the same as described above and the required sharing
terminal; with the classic teletype model, there of physical interactive resources lead us to
The terminal model for the RT PC must is no guarantee of atomicity in the output the concept of "virtual terminals" to provide
support the terminal requirements for the AIX streams. This has caused many unnatural terminal I/O in support of multi-tasking for an
operating system in a virtual machine contraints, most notably, blind background operating system running in a single virtual
environment. The IBM RT PC AIX operating processing, which is difficult for the user to machine and/or for multiple virtual machines.
system requires a "glass teletype" emulation monitor. One can envision that the problem is By virtual terminals we imply the appearance,
such as the Digital Equipment Corporation aggravated by the multiple virtual machine to a virtual machine or several virtual
VT-100 or the IBM 3161, which is an environment provided by the RT PC, where machines, of more terminals than physically
enhancement of the original keyboard there is even less possibility for synchronized exist on the workstation.
send/receive (KSR) teletype. This KSR use of the terminal.
terminal model provides support for the AIX The implementation of multiple virtual
"termio" model used in the shell and the One way to solve the multi-thread problem is terminals requires sharing of the available
majority of the current teletype based to add physical devices to the workstation. physical resources needed for interaction with
applications. The model also must support HO'v"v'8ver, there are obvious reasons that the user. Obvious!y, these resources must at
other users of the virtual machine many tasks and/or virtual machines cannot least be time-shared among the virtual
environment such as diagnostics, installation each have a unique physical terminal. The terminals. We considered the implementation
and various internal test packages. Although cost of multiple displays, keyboards, locators of space sharing of both the input (keyboard
these additional users did not control the and other interactive resources prohibits a and locator) and output (displays) devices,
choice of the terminal model, the KSR does profusion of such devices. A workstation resulting in a so-called "messy desk" model.
accomodate their requirements. generally restricts the number of devices it We rejected the latter for displays because
can support due to adapter slot or power the significant processing required to support
The KSR terminal model is an ASCII terminal limitations. The facilities (office or desk space, the "messy desk" is better spent in end-user
emulation in the spirit of the ANSI 3.64 electrical outlets, etc.) also place obvious application execution. Thus, virtual terminals
standard utilizing a PCASCII code set rather constraints on the number of devices that an simply time-share the physical displays,
than the ANSI 3.4/3.41 code sets. The ANSI individual can effectively use. Not so obvious resulting in a full-screen virtual terminal
3.64 data stream is extended, as specified by is the inconvenience of the physical management system. Our implementation of
the standard, to support enhanced sound- movement and refocusing of concentration time sharing in no way restricts application
generation capability, to handle the flow of required to use a multiplicity of interactive packages from space sharing the screen of a
locator events, and to provide various devices. Thus, one must conclude that these single virtual terminal among multiple

134
processes. As will be described later, Virtual Terminal Manager Subsystem
Virtual
however, we did choose to space-share the Structure Terminal Virtual
input devices. Figure 1 shows a simplified conceptual model Supervisor Terminal

of the Virtual Terminal Manager. It consists of Resource

The Concept of Virtual Terminals a supervisor, a Keyboard Device Driver Controller
The concept of terminal virtualization has (KDD), a Locator Device Driver (LDD), a
advantages classically associated with virtual Sound Device Driver (SOD), a Display Device
resources such as virtual storage or virtual Driver (ODD), and multiple virtual terminals.
disks. For discussion, let us consider the Keyboard Display
Device Device
analogy between virtual storage and virtual Each virtual terminal embodies the Driver Driver
terminals: characteristics of a single keyboard
send/receive terminal. That is, it recognizes
Figure 1 Virtual Terminal Manager structure
• A classical virtual storage system gives the and processes the data stream received from
programmer and or user the impression of the virtual machine causing the requested all physical display control to the application
having more storage than is physically actions to occur, for example, move the environment. In this mode, application
present. The concept of virtual terminals cursor or draw characters onto the virtual programs can enjoy a very short path to the
allows the virtual machines the impression display, insert or delete lines, clear the physical display and can implement, if they
that there are considerably more display screen, or change the attributes with which choose, arbitrarily complex graphics rendering
devices than are physically present, that characters are rendered. In addition to these algorithms, character algorithms, etc. The
there are more input devices than are actions, the outbound data stream can cause purpose of this mode is twofold. First, it
physically present and that these devices the generation of sequences of continuous allows the functional content of the base
have different characteristics than the tone sounds or cause the virtual display to be virtual terminal subsystem to be enhanced.
physical devices. rendered on any of the available physical Second, it reduces the performance overhead
displays. associated with device-independent display
• Virtual storage relieves the programmer of
virtualization.
clumsy mechanisms, such as overlays, for A virtual terminal receives input from a virtual
dealing with limited physical resource. keyboard and/or a virtual locator; it outputs to The supervisor comprises two components:
Virtual terminals relieve the programmer of a virtual display. Thus, the virtual terminal can the resource controller and the screen
developing his or her own mechanisms for always expect to get input from its virtual manager. The resource controller initializes
dealing with the limitations of the actual input devices and can always output to its and terminates the subsystem, allows a virtual
resources. virtual display. These virtual devices mayor machine to query and modify the
may not have physical devices allocated to configuration and characteristics of the
• In a virtual storage system, programs can them, however, so the virtual terminal may interactive devices (the real terminal) available
be written to be independent of the not actually get input or write to a physical to the user, and allocates and deallocates the
specifics of the physical resource, such as display. As each virtual terminal recognizes system resources required for the operation
the size of primary storage, types and and processes the data stream inbound from of a virtual terminal as it is opened and
formats of secondary storage devices, etc. the keyboard, it can, if requested,
closed.
With virtual terminals, a program can be automatically echo various characters and
written to be independent of the specifics of simple functions back to its virtual display. The screen manager is the analog of the
physical terminal devices, for example,
paging supervisor in a virtual storage system.
display buffer organizations, presence of The virtual terminal has a special mode of It performs the allocation of physical devices
optional input devices, etc. operation in which it handles virtualized input to the virtual devices used by the virtual
in an essentially normal way but relinquishes

135
terminals. The screen manager, in conjunction collection of virtual terminals is not. The The above restrictions enabled us to
with the keyboard and locator device drivers, virtual terminal subsystem supports up to four implement a virtual terminal system with the
implements the time and space sharing physical displays and any virtual terminal may following desirable characteristics:
required to virtualize these input devices. For use anyone of the four at any instant. This
example, we partition the physical keyboard restriction is due to the number of expansion • Multiple interactive threads with near single-
into two subsets, termed logical keyboards. slots in the hardware rather than an terminal performance
The first of the logical keyboards (the architectural restriction of the Virtual Terminal
alphanumeric keys, the function keys, and Manager subsystem. • Physical-device-independent terminal model
their shifted states) is allocated at all times to
one and only one of the virtual keyboards Resource Management • Application escape for direct physical
used by the virtual terminals; the other logical The virtual terminal supervisor provides for display access.
keyboard (the shifted states of the Action key) changing the physical environment. Global
is reserved for the screen manager. In a changes affect all virtual terminals. For The result is a virtual terminal environment
similar manner, the screen manager, in instance, a virtual machine may add or delete compatible with existing applications and
cooperation with the display device driver, physical displays, add a locator, a sound capable of supporting new, more
implements the space sharing required to device or fonts, and change the physical sophisticated applications.
virtualize a display. At any time, the display is characteristics of the keyboard and locator.
allocated to one and only one of the virtual
displays used by the virtual terminals. Local changes affect only a single virtual
terminal. Applications effect these changes
The screen manager allocates all the physical through the data stream sent to their virtual
devices en masse to the virtual devices of the terminals. Applications may change the
"active" virtual terminal; that is, the virtual current font, the current physical display and
terminal with which the user may interact. The various mappings and default operating
active virtual terminal can actually get input characteristics. Additionally, we provide an
and produce output on a display. The screen escape mechanism to allow the application to
manager also provides for reallocation of the re!ease a display on a !ocal terminal basis for
physical ieSOUices. The impetus fOi direct access to the dispiay adapter.
reallocation results from either user requests
(via the logical keyboard, or a similar logical Conclusion
mouse, allocated to the screen manager) or The virtual terminal system just described is
application requests. It involves deallocating deliberately restricted in order to reserve
the resources from the currently active virtual processing resources for application tasks.
terminal and the allocation to the newly active These restrictions take the following form:
virtual terminal. This allocation requires the
cooperation of both virtual terminals. As • No support for a multi-window, space-
mentioned above, the participation of the sharing approach to physical display
device drivers ensures synchronization of resource allocation
events such as keystrokes and work request
acknowledgments. • No built-in graphics or paint program
support
It is important to note that while a single
virtual terminal is restricted to a single • Primitive resource allocation via the virtual
physical display at anyone instant, the terminal supervisor.

136
Use of a Coprocessor for Emulating the PC AT

John W. Irwin

Introduction and accurate emulation of the PC AT over a keyboard and display. A combined hardware/
The IBM RT PC workstation, based on the wide variety of RT PC configurations.[2] software protection system safely isolates
ROMP processor, is a significant departure such unfriendly code from the balance of the
from previous small computer architectures The System Environment of the Coprocessor system.
and cannot run object code assembled or The PC AT coprocessor card was designed
compiled for older processors.[1] Users who as a feature card for the RT PC Input/Output Many adapter cards that may be installed on
are moving up to the RT PC from the IBM (I/O) channel.[3] The Intel 80286 runs the RT PC I/O channel may not have existed
Personal Computer (PC) may wish to continue simultaneously with the host ROMP when the PC AT code was written. An
using their present software library for processor, appears to the user as a PC AT, example is an all-points-addressable (APA)
reasons of economy and familiarity. Some and can use the RT PC diskette drive or display adapter. The same coprocessor
existing software for the PC may never be aSSigned minidisks in the RT PC disk space. hardware that protects the system against
rewritten for the new processor, particularly The keyboard and display(s) are time-shared improperly written PC code and supports the
software that was originally written in between the two processors under control of sharing of system resources between the
assembler. The PC AT coprocessor was the ROMP. coprocessor and the ROMP is used by ROMP
developed to provide continued use of such host software to emulate current PC AT
PC software products, including the popular The I/O channel in the RT PC is separate adapters while using the new adapters.
editor and spreadsheet packages. from the processor channel and is attached to
the ROMP processor by an I/O Channel Hardware Design Features
Even after most PC software is ported to the Converter (IOCC) as shown in Figure 1. The The coprocessor is packaged on a PC AT
RT PC, the vast support network of I/O channel is physically identical to the PC form factor adapter card. The heart of the PC
programming expertise, publications, and AT channel, has compatible signal timing, and AT system board is duplicated in the
programs that exists today for the PC AT may will accept most 16-bit PC AT adapter cards coprocessor architecture in that 65,536
never be equalled for the RT PC. The PC AT and many 8-bit PC AT adapter cards. The I/O distinct I/O addresses are possible using a
coprocessor makes this base of support channel does not support ROMP memory 16-bit subset of the 24 I/O channel address
immediately available to the RT PC user by access and therefore has unused bandwidth lines. Within this address space, 80286
emulating the IBM PC AT within the RT PC to support the coprocessor. access must be limited to those I/O devices
architecture. assigned to the coprocessor while access is
Like the other members of the PC AT family, blocked to those devices assigned to the
Critical to the use of Personal Computer the coprocessor will attempt to load and run ROMP. This is accomplished by an 8192 by
software in the RT PC was the development any diskette the user places in the diskette 1-bit Random Access Memory (RAM) on the
of coprocessor hardware for the purpose of drive. Neither the coprocessor nor the ROMP coprocessor card, which can be written to
protecting the system against improperly has any control over what code will be only by the ROMP. During I/O operations by
written PC code and for sharing system executed. Such "unfriendly" code may not the coprocessor, the trap RAM is addressed
resources between the ROMP and the follow approved access procedures to the I/O by the 80286 I/O address lines A 15-A3, so
coprocessor. When properly supported by a controllers, preserve critical memory that the corresponding access bit is read from
ROMP software driver, the result is a safe locations, or share I/O devices such as the the RAM. In the trap RAM, each bit controis

137
 Processor card
coprocessor for further operation. If the
trapped operation is an I/O read, the ROMP
System must read the trap address register, calculate
memory card(s) the emulated response to the read, then write
that response to the coprocessor data
register. The ROMP write to the data register
releases the coprocessor for further
operation.
System memory bus
Heavy load Interrupt Filtering
I/O
channel The I/O channel interrupt lines are shared by
converter both processors and certain conditions must
Coprocessor Memory & I/O
Light load card cards be met for the system to operate:

1. The coprocessor must not respond to

(PC AT) compatible channel interrupts from I/O devices assigned to
the ROMP. The code running in the
Figure 1 System Block Diagram coprocessor cannot be controlled;
therefore, such interrupts must be
access to a group of eight I/O addresses. As 5. The device address is being used as a blocked by hardware.
shown on Figure 2A, if the bit is on, the parameter passing port to synchronize
coprocessor can access the device normally, operations between the coprocessor and 2. The coprocessor must have free access
otherwise the coprocessor access is trapped the ROMP. The diagnostics use this to interrupts from I/O devices assigned to
and one of several conditions may exist: mechanism. it.

1. The device does not exist on the system. When an I/O trap occurs, the coprocessor is 3. The ROMP must force interrupts to the
stopped by assertion of the NOT-READY iine.
2. The device is currently assigned to the The coprocessor card I/O channel drivers are emulated devices.
ROMP. For instance, the printer might turned off so that the ROMP can use the
currently be in use by the ROMP and channel to access the coprocessor trap and The coprocessor card contains two 16-bit
unavailable to the coprocessor. filter registers and other I/O devices needed registers for interrupt control as shown in
to emulate the addressed I/O device. The Figure 2B. One register is used to mask I/O
3. The device may exist in a different form ROMP can set up the coprocessor to issue channel interrupts to the coprocessor, the
than expected by the coprocessor code an interrupt whenever an I/O trap occurs. other register is used to force interrupts to
and the ROMP will emulate the device the coprocessor. By the manipulation of these
expected by the coprocessor. The The ROMP responds to an I/O trap by two registers, the ROMP completely controls
keyboard is an example. reading the flag register of the coprocessor the interrupt environment of the coprocessor.
where individual bits show I/O read trap, I/O
4. The device is assigned to the write trap, and the I/O access width (8 or 16 The interrupt mask register contains a bit for
coprocessor, but the ROMP must track all bits). If the trapped operation is an I/O write, each I/O channel interrupt line. If the bit is set
changes made to the device by the the ROMP reads the coprocessor trap by the ROMP, that I/O channel interrupt is
coprocessor. A time-shared display address and trap data registers and emulates gated to the interrupt controller, otherwise the
adapter is an example. the hardware device. The ROMP read of the I/O channel interrupt is blocked and cannot
coprocessor trap data register releases the affect the operation of the coprocessor.

138
The interrupt force register contains a bit for
each channel interrupt. If a bit is set by the
ROMP, the corresponding interrupt is
asserted. Additional register bits are provided A I/O address Trap
to force the keyboard and non-maskable 80286 controls
interrupts (NMI) to the 80286 since these
interrupts do not appear on the channel.

Sharing Video Resources

The problem of sharing or emulating video Irq, address, data
to ROMP ,r-----------I
adapters is made difficult by the variety of to selected I/O
video configurations that are supported by the
PC AT code and the different set of display
options available in the RT PC. Video sharing
or emulation is accomplished by a
combination of ROMP code and video filter B 80286 8259
Interrupt Interrupt
logic on the coprocessor card. generator filter

If the user prefers to have a display dedicated

to the coprocessor, any PC AT compatible
display may be plugged into the channel for
this purpose, provided that there are no ROMP generated
emulated interrupts
address conflicts with displays assigned to
Bus interrupts
the ROMP. The I/O filters and traps are set
by the ROMP to allow the coprocessor
access to the coprocessor display and to
Memory addresses
prevent access to the ROMP display(s). and data

A lower cost configuration is a display time- c Video Video

shared between the ROMP and the 80286 control relocation
register logic
coprocessor, under operator control through
the keyboard. To properly restore the display
when the coprocessor regains control, the
ROMP must keep a record of coprocessor
video actions occurring during the time the Virtual video Real video
ROMP is using the display. Control actions to buffer buffer

the display adapter are trapped and recorded

using the I/O traps. The memory mapped Figure 2 I/O Traps and Filters
video buffer is recorded by video buffer
relocation hardware as shown in Figure 2C. Enhanced Graphics Adapter (EGA). At assigned to the Color Graphics Adapter (CGA)
OBOOOOh, there are 32K bytes assigned to the and also used by the EGA. The coprocessor
In the PC AT memory map there are 128K monochrome adapter and also used by the hardware can distinguish these ranges and
bytes assigned to video buffers. At address EGA. At OB8000h, there are 32K bytes process accesses to each range separately.
OAOOOOh, there are 64K bytes assigned to the

139
The ROMP writes to a control register on the occurs. This interrupt is issued without Video
display
coprocessor card to set each buffer address stopping the coprocessor. Since display 80286 Relocation
range to one of four modes: updates tend to occur in bursts, the interrupt code logic
is masked off during periods of high display
1. Assigned to the coprocessor activity and the ROMP then polls periodically
A
for buffer changes.
2. Made invisible Virtual
ROMP Real
buffer
The display may have a different pel density display buffer
in
sharing in
3. Relocated into a memory buffer or pel aspect ratio than the display supported system
code adapter
storage
by the coprocessor code, so considerable
4. Relocated into a memory buffer and the processing is required to map the virtual
addresses of the buffered data queued. buffer to the screen. If the ROMP had to
refresh the entire screen each time a change Address
Relocation
When a display is assigned to the was made by the coprocessor, emulation logic
coprocessor, the traps and relocation performance would be entirely unacceptable.
hardware for the corresponding address For instance, the coprocessor update of the
range are turned off. time of day on the screen might frequently B
write a single character to the screen. If the Virtual
Real
When a display range is made invisible, I/O ROMP could not easily determine which buffer ROMP buffer
in emulator
reads and writes are trapped, reads and characters were changed, this action could system code
in
adapter
writes to the video buffer are suppressed, result in an unacceptable ROMP processing storage

and the coprocessor is thus prevented from load to examine the entire buffer for changes
interfering with displays assigned to the or to recalculate the entire screen. Either Figure 3 Video Relocation and Queuing
ROMP. method would require processing several
thousand bytes of buffer data to make the The low-order 16 bits of the video address
When the installed display adapter is one of Single-byte change. are written into the queue area in memory
the common adapters used by the PC family, and the hardware queue input counter is
display control is not difficult. Control The video address queuing performance aid advanced. The input counter (queue tail) is
becomes much more difficult when the is used to inform the ROMP exactly which read by the ROMP, the data translated, and
installed display adapter is not supported by buffer bytes have been changed so that the output register (queue head) is advanced
the code running in the coprocessor (an APA minimum buffer data has to be processed. by the ROMP. An interrupt informs the ROMP
display) or when the processor display output This performance aid yields as much as a when the queue overflows during scrolling or
is mapped into a window on a shared display. 100,000 to 1 performance improvement. clearing the screen. When overflow occurs,
In these instances, the ROMP must translate the ROMP resets the queue pointers and
the virtual video buffer to the display. The queue is a memory area assigned by the regenerates the entire screen.
ROMP (Figure 38) that is organized as a
When the ROMP translates the virtual buffer circular buffer. The low-order address of the
Bus Arbitration
to a display (Figure 3A), the ROM P code must circular queue is provided by a counter on the
The separate memory and I/O channels of the
know when the video buffer has been coprocessor card and the queue size can be
RT PC system relieve the I/O channel of the
changed by the coprocessor. This may be set to 1024, 2048, or 4096 entries. When
ROMP instruction and data fetch load so that
accomplished by using interrupts or by relocation with queuing is selected, the
the channel is lightly loaded when the
polling. When the coprocessor display activity coprocessor card logic inserts a hardware-
coprocessor is not running, averaging about
is low, the ROMP allows a coprocessor generated memory write cycle immediately
10% usage. The coprocessor, when running,
interrupt to occur whenever a buffer write after each write to the virtual video buffer.

140
can use about 90% of the available bus can be installed at address 0 and additional References
1. P.O. Hester, Richard O. Simpson, Albert Chang, "IBM
cycles or all the available bandwidth. memory cards may be installed above one
RT PC ROMP and Memory Management Unit
megabyte. Architecture," IBM RT Personal Computer Technology,
An additional Direct Memory Access (DMA) p.48.
channel, using a special arbitration method, At the time of coprocessor initiation, the 2. Rajan Krishnamurty and Terry Mothersole,
was added to the system board logic to ROMP code tests for the presence of channel "Coprocessor Software Support," IBM RT Personal
service the coprocessor. In the channel memory at channel address 0 and again at Computer Technology, p. 142.
socket assigned to the coprocessor, the pins one megabyte. If memory is found at either 3. Sheldon L. Phelps and John D. Upton, "System
normally connected to DMA channel 7 are, location, all contiguous channel memory is Board and I/O Channel for the IBM RT PC System,"
IBM RT Personal Computer Technology, p. 26.
instead, connected to the special arbitration used by the coprocessor. With most of the
logic, DMA channel 8. Where the coprocessor memory access cycles taken
acknowledgment to normal DMA channel from the one wait-state channel memory, the
requests grant the channel to a secondary coprocessor performance approaches PC AT
master for an indefinite length of time, the performance. There is less system memory
special coprocessor arbitration grants the contention with the ROMP, so that ROMP
channel to the coprocessor only until another performance is increased as well.
user (or memory refresh) requires service. At
that time, the acknowledge signal for the Conclusions
coprocessor is dropped by the arbitration The RT PC's PC AT coprocessor card with its
logic to signal the coprocessor to vacate the ROMP programming support represents an
channel at the next possible point in the ambitious attempt to emulate a specific
cycle. The coprocessor drops the request and machine environment within a machine of
master lines to release the channel and then radically different architecture. This aim has
immediately requests service again to recover succeeded to the degree that, except for
the channel when it is free. The coprocessor processing speed, the user cannot ordinarily
DMA channel is the lowest priority, below distinguish the coprocessor from an actual
ROMP Programmed 1/0 (PIO), refresh, and all PC AT. The most important new features of
other DMA channels, so that other channel the coprocessor are the ability to provide true
activity is affected very little by the concurrent processing with system protection
coprocessor. against unfriendly coprocessor code and the
combination of coprocessor hardware and
System Memory Versus Channel Memory ROMP software that provides flexibility in 1/0
If channel memory is not installed, the adapter and 1/0 channel or system memory
coprocessor uses system memory that is allocation. Future expansion is provided by
pinned by the VRM and will not be paged out. the ability to emulate PC AT adapters using
This is the most economical coprocessor new RT PC adapters or future 1/0 device
configuration, but not the best performing adapters not known to the original writers of
one. Because of the long access path from the PC code. In addition, the coprocessor
the coprocessor to system memory, the features special arbitration for increased 1/0
coprocessor performs only slightly better than channel performance.
the PC XT and affects ROMP performance by
memory and 1/0 channel interference. If
better coprocessor performance is required, a
512K, 16-bit, PC AT channel memory card

141
Coprocessor Software Support

Rajan Krishnamurty and Terry Mothersole

Introduction user to select a combination of system

Compatibility with existing applications that PCST ART jPCEND resources that are to be attached to the
run on the IBM Personal Computer AT was coprocessor. The user may optionally save
deemed to be a significant enhancement to this configuration in a default profile to be
the RT PC ROMP-based product. The IBM S used in future initiations of the coprocessor.
RT PC Personal Computer AT Coprocessor
a PC Applications
F PCSTART also provides a prompting mode
Services LPP provides the user with a means T
DOS V
CP Virt. CP Dev.
for the casual user, in which the user is first
W R
to run PC applications on the IBM RT PC shown the current default value for a
I
A Terminal Manager
M
Personal Computer AT Coprocessor card in a R BIOS/BASIC CP Device Drivers parameter and has the option to alter its
E
way that is essentially the same as their value.
execution on a PC AT. The coprocessor card
consists of an Intel 80286 processor and There is no memory on the coprocessor card,
H 80286 Coprocessor ROMp·
hardware support to allow PC AT applications A so memory is provided as a mixture of
to be executed concurrently with ROMP R Trap/Control Hardware 10CC system memory and I/O channel-attached
D
applications[1]. Coprocessor software support W memory. Memory is first allocated from the
inclutles ROMP code executing in the Virtual A
R - I 1 - cards plugged into the I/O channel. If there is
Resource Manager, which provides several E I/O Channel not enough channel-attached memory (there
levels of device support and virtual terminal might not be any), the rest is provided from
ring support with ROMP virtual terminals. I II
I I
I
- . I II I
I
_.. I ROMP system memory and pinned to prevent
A!so, the Coprocessor LPP includes AIX Shell l;ommo. I I t'rlmer I I UISK I I page faults. This is accomplished by setting
code to allow the user to configure the PC AT
environment and start/end a coprocessor IOiLel ~ I Key~ard I up the 10CC to convert the I/O channel
addresses to the appropriate virtual
session. addresses. The virtual addresses use the
Figure 1 Coprocessor environment MMU segment register that is dedicated for
System Environment I/O device access to system memory.
The AT Coprocessor Services LPP, when running on the coprocessor. Most of the Channel-attached memory must begin at
installed on the RT PC, allows the PC AT challenge of incorporating the coprocessor address 0 and be continuous if it is to be
coprocessor to run concurrently with the was the allocation of memory, sharing of recognized and used by the coprocessor. The
native ROMP processor. The coprocessor devices, supporting displays that are not amount of system memory that is available to
card is attached to the I/O channel. Figure 1 supported by the PC AT, and monitoring I/O the coprocessor depends upon how much is
shows the PC AT coprocessor system accesses in the creation of a PC AT left after VRM and the operating system have
environment and Figure 2 shows the environment. met their requirements.
coprocessor software support. VRM software
running on ROMP, with the aid of trap logic An AIX command, PCSTART, is provided to Devices connected to the I/O channel are
on the coprocessor card, protects the RT PC the user to tailor the configuration of the supported in different ways, depending on the
base operating system from applications PC AT environment. PCSTART allows the specific attributes of the device. The followin"g

142
 Coprocessor
Device ROMP Only Shared Dedicated Only
AIX
MMU X
10CC X
System Mouse X
Virtual Machine Interface (VMI) DMA X
Disk X
Keyboard X
Virtual SVC Virtual
INT INT Real Time Clock X
Configuration CMOS RAM X
Display X X
CP Virtual CP Minidisk Communications Ports X
Terminal Manager Manager
(CPVT) (CPM) Planar Serial Ports X
V
R Printer X
Virtual
M Diskette X
Display Driver
Speaker X
New Devices X
System Memory X
I/O Channel Memory X
CP Device Driver 80286 Int. Ctlr X
(CPDD)
80287 Math Coprocessor X
Interval Timer X
Light Pen X
H
A
R Figure 3 Device Support Modes
D
IN
A Coprocessor Card (80286) Disk support is provided using RT PC
R
E minidisks. File system integrity is maintained
by trapping all coprocessor accesses to the
disk. Coprocessor support code performs the
Figure 2 Co-Processor Software Structure
data transfers using the minidisk manager
and then sends acknowledgments back to the
definitions describe the range of device coprocessor session. If the device is
coprocessor.
support: PC AT-compatible (e.g., planar serial ports),
coprocessor accesses to it go directly to Terminal Support: Displays
• ROMP only - the device is available only that device with no ROMP intervention. If The RT PC display support plan includes
to the ROMP. the device is not PC AT-compatible, PC AT supported display adapters and new
coprocessor accesses to it are trapped and RT PC adapters that are unknown to the PC
• Shared - a device is shared when it can emulated by the ROMP. family product line. Given that the
either be accessed by both processors coprocessor option could reside on any
concurrently (e.g., disk, DMA) or can be • Coprocessor only - available only to the RT PC display configuration, code and
dynamically switched between them (e.g., coprocessor. Either the ROMP is unable to hardware were required to supply the
the display). Device sharing is accomplished get to it or the device is never allocated to coprocessor user with various display support
by allowing only the ROMP to issue the 110 the ROMP. possibilities in order to run PC applications on
commands to the device. a non-PC supported display adapter. Thus,
Figure 3 shows the ways in which the various the coprocessor user has two display
• Dedicated - the device is allocated to the supported devices are treated. configuration options available: dedicated
coprocessor for the duration of the

143
mode, which allows the coprocessor to inadvertently with the ALT-ACTION hot-key Coprocessor support of the APA8 was the
access the display adapter directly; and sequence. major driving force behind providing a display
monitored mode, which prevents the access mode that would allow sharing display
coprocessor from accessing the adapter • If ROM P did not have an open virtual devices between ROMP and the coprocessor.
directly, while allowing the coprocessor virtual terminal on the requested system display, The coprocessor virtual terminal mode
terminal to be in the ring of virtual terminals then the display is "allocated" to the processor utilizes the same VRM virtual
supported by the Virtual Terminal Manager[2]. coprocessor for the duration of its session. display driver (VDD) interface that other virtual
In this mode, the user can traverse the terminals do, to emulate the PC Monochrome
Allowing the coprocessor to run a PC- virtual terminal ring without ending the Adapter and the PC Color Graphics Adapter.
supported system display adapter in coprocessor session. Emulation of the graphics modes involved a
dedicated mode (with channel-attached great amount of transformations on the video
memory) gives the user up to 80% of the The user is unaware that the display is pel buffer. Emulation details are outlined
performance of the PC AT since there is no configured as dedicated/direct or dedicated/ below:
intermediate device driver trapping/emulating allocated, and the performance is the same.
the I/O address range or relocating the video Note: If the system display can be allocated • Color text emulation is supported on the
memory. The only Release 1 displays that this to the coprocessor (as opposed to direct), it APA8. However, the color select register is
mode can be used with are the IBM Personal will be, so as to enable the user to hot key to ignored since this adapter is monochrome.
Computer Monochrome Display Adapter and other virtual terminals. Text characters are built up into text lines,
the Enhanced Color Graphics Display while the color attributes are ignored. This
Adapter. The APA8 can only be run dedicated If a PC AT-supported system display cannot allows an application that switches between
if a future PC application is written that be allocated to the coprocessor, or if the user text and graphics to operate on this one
supports it. In any case, the APA8 in wishes to emulate the PC Monochrome adapter, without requiring the user to
dedicated mode is not supported as the adapter or PC Color Graphics display adapter configure in two displays to support the two
primary coprocessor display. on the APA8, the system display can be different modes.
configured to be shared with ROMP in a
Depending on the display utilization by ROMP display access mode referred to as • The pel resolution and the pel aspect ratio
virtual terminals, dedicated mode is formally "monitored." All I/O commands from the of the PC Color Graphics Display Adapter
defined as "direct" or "allocated:" coprocessor are trapped and saved; to allow differs from the APA8. Converting a
the display adapter state to be restored when graphics image built for a 640 x 200
• If ROMP had a virtual terminal opened on control is returned to the coprocessor. When resolution display with a pel ratio of 2:1, to
the requested system display at the time the display adapter is the PC Monochrome or a 720 x 512 high-res display with a pel ratio
the coprocessor was started, then the the Enhanced Color Graphics Adapter, the of 1:1 was accomplished with a simple and
display is configured in "direct" access video buffer is accessed directly by the fast algorithm that duplicated scan rows to
mode. In this mode, the virtual terminal coprocessor. When the display adapter is the create a 640 x 400 image. Basically, the
does not provide a device-driver interface APA8, video buffer accesses are relocated to algorithm squared off the rectangular pel
that monitors the state of the adapter at all system memory and the APA8 virtual display ratio of the PC color graphics image, in
times (I/O and video buffer). The only way driver is used to update the screen. This order to proportion the image onto the
for the user to access the next ROMP mode also frees the display adapter so that square pel ratio of the APA8. The resulting
virtual terminal in the ring is to terminate ROMP can open new virtual terminals on it. image was then centered onto the APA8
the coprocessor virtual terminal session by Control of the requested system display screen with a border around it.
use of a special key sequence (CNTL-ALT- adapter is switched to the coprocessor when
ACTION). This prevents the user from its virtual terminal becomes active via the • To support an application operating in 320
terminating the coprocessor session ALT-ACTION hot-key sequence. x 200 medium resolution color graphics
mode, four different shades of gray are

144
 provided, by a "half-toning" method, to keyboard buffer is a 16-byte FI FO queue with session. The only interface to the fixed disk
simulate the four selected colors. On a a 17th byte for overrun. from the coprocessor is through BIOS. Any
Color Graphics Display Adapter (CGA), two attempts to issue I/O instructions to the
bits describe a logical pel unit, which The keyboard layout of the RT PC keys is a physical disk addresses are trapped by the
consists of two physical screen pels. With superset of a PC AT keyboard. It contains all coprocessor card and are interpreted as
the scan rows duplicated as in high- of the engravings resident on a PC AT unallocated device accesses.
resolution (640 x 200) mode, this creates a keyboard, while some of them have been
640 x 400 image with a square logical pel moved or duplicated to other key positions. Async Redirection
unit of four physical pels. The four pels For example, the new set of cursor motion There exists a coprocessor async device
comprising the logical pel unit are turned on keys and edit keys (INS, DEL, PAGE UP, driver that will emulate serial port functions of
or off to produce one of four shades (Le., PAGE DOWN, HOME, and END), will be the PC AT serial/parallel card on the native
black, dark gray, light gray, white). As an translated as engraved, without numbers. The RT PC planar serial ports (RT PC model 6150
example, with all pels turned on, the color coprocessor virtual terminal will maintain state only) which are Zilog Z8530 based. I/O
produced is white. With two diagonal pels flags for the NUMLOCK and the SHIFT keys, between the coprocessor and the PC AT
turned on, the color produced is a light as well as for the CAPSLOCK, SCROLL Serial/Parallel card (National 8250) is
gray. LOCK, CTRL, and ALT. Depending on the redirected to one of the two planar async
combined state of the NUMLOCK and the ports. Control information being sent will be
The coprocessor may have use of more than SHIFT, SHIFT make/breaks may be sent translated from the PC AT Serial/Parallel card
one display, but it can use only one ROMP around the scan codes for the new native format to the planar serial port format and
system display on which a virtual terminal cursor motion and edit keys, in order to force redirected to the async ports on the planar.
exists. Other displays can be ROMP displays the engraved key translation. Data bytes containing control information
that can be allocated to the coprocessor or being received from the async ports on the
coprocessor-only display devices such as the From a system perspective, the coprocessor planar wi!! be translated from the planar serial
PC Color Graphics Adapter. The PCSTART mode processor works with the VRM port format to the PC AT serial port format
command monitors the system usage of the keyboard device driver in raw mode, receiving and redirected to the coprocessor.
available system displays and only allows a all makes and breaks of keys. During virtual
valid coprocessor environment to be set up. terminal transitions, the break of keys may be All PC AT serial port commands are emulated
sent to the next active terminal. Since the on the planar ports except stuck parity and
Terminal Support: Keyboard mode processor keeps track of the control/ diagnostic loop mode.
The keyboard on RT PC is a shared device shift keys, it can send break scan codes
between the ROMP processor and the appropriately. The mode processor also traps Summary
coprocessor. Residing in the VRM the situation where the user wishes to The RT PC AT Coprocessor Services LPP
coprocessor terminal support code are a terminate the coprocessor session with the provides PC compatibility to the user,
device driver and a mode processor that CNTL-ALT-ACTION key sequence. This complete with device-monitoring features to
provide a PC AT 8042 keyboard controller simulates the user entering the PCEND emulate an IBM PC AT environment.
interface to the coprocessor. The mode command in the AIX operating system.
processor takes in RT PC key positions from There are known incompatibilities that exist
the VRM keyboard device driver, translates Disk Emulation due to hardware restrictions, or to limited
them to PC or PC AT scan codes, places The fixed disk devices on the RT PC are software emulation capabilities:
them in a simulated keyboard buffer, and then divided into logical minidisks that are
generates an interrupt to the coprocessor. managed by the minidisk manager. PC AT 1. (Mini)disk access supported through BIOS
The scan code sets for PC and for PC AT are fixed disks are emulated through the use of interface only. All BIOS calls are
stored in a structure indexed by the type of minidisks. Up to two minidisks can be supported except formatting a disk,
the emulated keyboard. The simulated allocated to the coprocessor during a given

145
 initializing drive pair characteristics, read Henry, Larry Loucks and Frank King were
long, and write long. invaluable in helping us through many difficult
times.
2. Code dependent on instruction execution
timing may cause unpredictable results. References
1. John W. Irwin, "Use of a Coprocessor for Emulating
the PC AT," IBM RT Personal Computer Technology,
3. Some 6845 display controller commands
p.137.
and some PC color graphics modes are
2. D.C. Baker, G.A. Flurry, and K.D. Nguyen,
not supported on the APA8. "Implementation of a Virtual Terminal Subsystem,"
IBM RT Personal Computer Technology, p. 134.
4. Enhanced Color Graphics Adapter high-
resolution modes are supported only on
the Enhanced Color Display in dedicated
mode.

5. Partial DMA support.

Even with the known restrictions, the AT

Coprocessor LPP provides the RT PC user
with the ability to run PC applications
concurrently with ROMP virtual terminals. The
simulated PC AT environment is made
virtually transparent to the user after
configuration time and allows system devices
to be shared by both processors.

Acknowiedgments
The Coprocessor Licensed Program Product
is the result of the outstanding contributions
of many people. The dedication of the
development team which included Harish
Agarawal, Wayne Blackard, Dean Boschult,
David Chiang and Chuck Nunn and the
management leadership of Johnny Barnes,
Joe Corso, Stan Douglas, Pat Motola and
Gary Snyder during the various stages of the
project were critical to the success of the
product. The cooperation and efforts of the
Systems Test, System Assurance and VRM
departments were key in ensuring a high
quality product. The encouragement and
support provided by Clay Cipione, Glenn

146
PC DOS Emulation in the AIX Environment

Leonard F. Brissette, Roy A. Clauson, Jack E. Olson

Introduction command without having to exit the DOS DOS Library

This article describes the major features of Shell and then restart it. I .profile DOS User
File Application
the PC DOS emulation functions that are a DOS Access Space
part of the IBM RT PC AIX operating system. Figure 1 shows one instance of a DOS Shell Shell I-- Method
The widespread acceptance of the IBM PC and its relationship to the rest of the system.
and the DOS operating system mandated that At "login", a user's AIX .profile file can AIX Kernel API

a user interface with a similar set of DOS specify "dos" and the DOS Shell will
functions be part of the RT PC AIX. These automatically be invoked for the user. Using TTY Device Driver
Fixed Floppy Printer
functions allow the existing PC DOS user to this procedure makes the system look entirely Disk Disk DD
easily move up to the higher performance and "DOS" to the user, except for the login. DD DD

capacity of the RT PC with minimal re- Environment variables are used to define the
(hd) (fd)
r.;Tl
~
IASVNC
DD
I (Ip)

training. The nature of the AIX operating relationship between DOS Shell "logical
system allows a single RT PC to concurrently devices" like A:, LPT1:, etc., and the system's VMI

support multiple PC DOS emulation users, resources. These environment variables may
hence an apparent "multi-tasking" DOS. The be individually overridden by placing the
PC DOS emulation functions are provided by override information in the user's .profile file.
two major pieces; the RT PC AIX DOS Shell Thus, each DOS user on the system can
and the RT PC AIX DOS File Access Method. customize his or her own DOS environment.

The RT PC AIX DOS Shell Interface A user may also place an "autoexec.bat" file Figure 1 PC DOS Emulation Component Relationships
The RT PC AIX DOS Shell (hereafter referred in the A: drive, and at "login" time this batch
to as the "DOS Shell") provides a more file will be executed just as in DOS. Application programs written for the RT PC
friendly alternative user interface to the system may be executed from the DOS Shell.
traditional UNIX Shells. It allows a user to The DOS Shell uses the DOS File Access These programs may be stored in either AIX
manipulate "UNIX" files on AIX file systems Method set of routines in the DOS library to or DOS file systems. The system searches for
and "DOS" files on diskettes or RT PC access user files. These routines allow these programs starting in directory /usr/dos,
minidisks. It is an emulation of most of the PC transparent access to either an AIX file then in the user's current directory, and then
DOS 3.0 functions, using identical command system or a DOS file system and will be in each directory specified by the PATH list.
syntax. Those functions not emulated are PC discussed in the next section. The DOS file
DOS or hardware specific. system may have been created for use by the The DOS Shell was implemented as a
PC AT coprocessor feature. Thus, data separate shell, rather than using the "link"
The DOS Shell allows for PC DOS batch file objects created or processed on the command, because of the difference in
execution and also emulates the line editing coprocessor may also be processed by native semantics between the DOS Shell special
functions provided by PC DOS. An escape running RT PC applications, though not characters (? and *) and the AIX shell
mechanism is provided (via a prefix of '! ') to concurrently. metacharacters. The DOS Shell parses the
allow a user to execute an AIX Shell command line input following PC DOS rules

147
and passes the parsed/expanded parameters method in order to implement DFAM. This development cycle to be included in Release
to RT PC AIX programs in the conventional was done to assure portability of existing 1. File sharing allows concurrent access to
AIX format of argc, argv values. applications that use the current UNIX file the same file by multiple processes. At file
systems. "open time", an application specifies whether
The RT PC DOS File Access Method or not other processes may have write, read,
Many existing PC DOS applications create As was mentioned previously, a number of or read/write access concurrently.
data files in the form of data bases, environment variables have been established
spreadsheet models, and various forms of in the AIX environment for use by DOS Coprocessor applications run independent of
text documents. In an attempt to build upon emulation functions. DFAM uses these applications executing on the native RT PC
the existing customer base, the need was environment variables to determine the processor. No provision has been made for
recognized for easy migration of that data to binding of DOS device names to AIX access concurrency by coprocessor
the RT PC, as well as easy use of PC directories or system devices, as well as to applications and RT PC applications.
application data in a mixed PC and RT PC aid in the interpretation of file and path names
environment. Although file conversion utilities received by the various library routines. Summary
are provided for some files, it was felt that A high degree of PC DOS compatibility has
many applications may want to use the same Automatic conversion of ASCII files is been achieved at the user interface level. This
format of data on both PC's and on the provided through the use of a DOS should allow PC DOS users to easily migrate
RTPC. environment variable DOSFORMAT. If a file is to the RT PC. The system behaves like a
opened explicitly as an ASCII file, each read multi-tasking DOS system from an end user's
The DOS File Access Method (DFAM) or write to that file results in the conversion perspective. PC data files move easily into
consists of a set of library routines that allow of the data to either DOS ASCII or AIX ASCII, and out of the RT PC, allowing users
applications to access both DOS and AIX file depending upon the value of the flexibility in their data processing
systems transparently. The application DOSFORMAT variable. This conversion deals environment.
program interface contains those functions primarily with line ending characters
available in the UNIX file access method. (NL, CR, LF).
However, these functions have been
generalized to allow access to either DOS or DOS file attributes are closely emulated by
AIX files. The syntax of these routines is the DFAM library routines. The "hidden" and
identical to corresponding AIX system calls. "read-only" file attributes are emulated if the
Hence, existing applications can be easily file resides in the AIX file system. This was
converted to use DOS file systems. done using analagous attributes in the AIX file
system. The "system", "volume" and
DFAM uses the concepts of path names and "archive" attributes do not directly map to
a current directory to determine the location AIX attributes, and are therefore, not directly
of a specified file. If a specified file resides in supported.
the AIX file system, calls are converted to AIX
file system calls. If the files reside in the DOS Some Limitations
file system (either on a DOS diskette, or on a Some of the DOS functions have not been
DOS minidisk created by the coprocessor), implemented. The current design allows for
DFAM interprets the DOS directory structure the possibility of adding those functions, if
and retrieves data from the DOS file system. necessary.

DFAM resides above the kernel. No changes DOS file sharing became available in DOS
were made to the AIX file system access Release 3.1. This was too late in the RT PC

148
Authors

Hira G. Advani Ronald J. Barnett RT PC. He joined IBM in 1981 after receiving
a BSEE from the University of Texas at
Engineering Systems Products, Austin, Texas Engineering Systems Products, Austin, Texas
Austin. He received an Outstanding Technical
Achievement Award in 1983 for the design of
After receiving an MS in Computer Science After joining IBM in 1965, Mr. Barnett served
printer test equipment.
from Georgia Institute of Technology, Mr. in a variety of staff and management
Advani joined the IBM Office Products positions in the areas of quality and industrial
John M. Bissell
Division at Austin, TX in 1978. He worked on engineering. He worked in quality and
several software projects related to OS/6 and reliability positions on NASA Space and Navy Engineering Systems Products, Austin, Texas
Displaywriter. He is currently a Development Sonar programs before moving to Austin in
Programmer and is Operating System 1978. In Austin, he has managed quality and Mr. Bissell was the team leader for Data
Extensions manager for the IBM RT PC. industrial engineering areas for IBM's 5520 Management Services, and vendor technical
Administrative System, Displaywriter, and interface for the SQL/RT LPP. Mr. Bissell
David C. Baker RT PC products. Mr. Barnett holds degrees in joined IBM in 1972 after receiving a BSEE
Industrial Management and Industrial degree from MIT. Prior to coming to Austin,
Engineering Systems Products, Austin, Texas
Engineering from Auburn University. he worked on software for the Space Shuttle
Launch Processing System at Cape
Mr. Baker is an advisory programmer. He
J. R. (Bob) Barr Canaveral, Flo He currently manages the Data
received the Bachelor of Science in Electrical
Management Services department.
Engineering from New Mexico State Engineering Systems Products, Austin, Texas
University in 1972 and the Master of Science
Leonard F. Brissette
in Engineering from the University of Texas at Mr. Barr joined the Federal Systems Division
Austin in 1979. He joined IBM in 1976 and of IBM in Owego, NY in 1960, where he had Engineering Systems Products, Austin, Texas
was involved in microprocessor and systems design and test responsibilities on several
architecture and design. Mr. Baker worked on major government contracts. He received a Leonard Brissette is an advisory engineer
the system design of the Displaywriter. After BS degree in Electrical Engineering from the with the Engineering Systems Architecture
a temporary assignment to the IBM T. J. University of Missouri in 1960 and an MS department. He came to IBM from Eastman
Watson Research Center at Yorktown degree in Electrical Engineering from the Kodak Company in 1978 as a senior
Heights, Mr. Baker returned to Austin where University of Arizona in 1964. He is currently associate engineer in the Office Products
he worked on the advanced technology effort an advisory engineer in the Microprocessor Division at Austin, TX. Before joining the
leading to the startup of the RT PC Design group. RT PC development group, Mr. Brissette
development project. Mr. Baker currently worked on various Austin word processing
serves as chief programmer for local terminal Charles W. Bartlett products in the areas of diskette and data
support. stream design and applications. His work with
Engineering Systems Products, Austin, Texas
the Advanced Applications Development
group involved data base and LAN
Charles Bartlett is a project engineer and
manager of Manufacturing Test for the IBM

149
applications. Mr. Brissette holds a BSEE from Nancy A. Burns Roy A. Clauson
the University of Texas at EI Paso.
Engineering Systems Products, Austin, Texas Engineering Systems Products, Austin, Texas
Bertram E. Buller
Mrs. Burns is a senior associate programmer Mr. Clauson is currently the manager of the
Engineering Systems Products, Austin, Texas for IBM. She is currently a technical member Engineering Systems Architecture department
of the team developing an expert system to for the IBM RT PC. During the development
Mr. Buller is an advisory programmer in the perform diagnostics on a machine with limited of the RT PC he managed one of the
Hardware Architecture group for the RT PC. memory. Mrs. Burns is a PhD candidate at operating system departments responsible for
He joined IBM in 1956 in Kingston, NY as a Southern Methodist University. She received porting UNIX to the RT PC. Mr. Clauson
diagnostic programmer for the SAGE system. a BS in Statistics and Quantitative Methods at joined IBM in the Boston, MA, branch office
He has participated in the development of the Louisiana State University and an MA in in 1970. He worked on testing 3270 Display
1410 operating system, OS/360, System/23, Mathematical Sciences at the University of products, various communications networks,
and Displaywriter. He has held management North Florida. She is a member of the and the System/370-135 while in Kingston,
assignments in the FAA Air Traffic Control, Association for Computing Machinery and its NY. In 1975 he joined the 5256 printer
3705 Emulator, and 6670 SNA Special Interest Group on Artificial development group in Rochester, MN and
communications projects. From 1972 to 1976, Intelligence, the American Association for subsequently worked on the 5280 Distributed
Mr. Buller provided technical guidance on Artificial Intelligence, and the Association for Data System I/O Subsystem. In 1980 Mr.
SNA for a number of major application Computational Linguistics. Clauson transferred to Austin, TX, where he
projects, including Credit Lyonnaise, Mid- has held management assignments for 5280
Atlantic Mastercard, and the State of Albert Chang follow-ons, Office Systems Interconnect
California. He received a BA degree from Architecture, and IBM RT PC software
IBM Research Division, Yorktown Heights,
Gettysburg College in 1950 and has done development. Mr. Clauson received a BSEE
New York
graduate work at Syracuse University. from Northwestern University in 1970 and an
MSEE from Syracuse University in 1979.
Dr. Chang is manager of systems
A. V. (Tony) Burghart
development in the Advanced Minicomputer
Raymond A. DuPont
Entry Systems Division, Austin, Texas Pioject of the IBM Research Division which
he joined in 1965 after receiving a PhD in Engineering Systems Products, Austin, Texas
Mr. Burghart is an advisory engineer Electrical Engineering from the University of
responsible for the design and implementation California at Berkeley. His current interests Mr. DuPont joined IBM in April 1964 at East
of a new manufacturing process. He joined are in systems programming and computer Fishkill, NY after receiving a diploma from the
IBM in 1965 in Endicott, NY. He transferred to architecture. Penn Technical Institute. He held various
Austin in 1973. His career experience at IBM aSSignments in test equipment maintenance,
has been in the development and support of Ahmed Chibib bipolar circuit design and manufacturing
manufacturing processes, both component engineering. He received a BS degree in
Engineering Systems Products, Austin, Texas
manufacturing and product manufacturing. He PhYSics from Marist College in June, 1974.
has held positions in both engineering and He transferred to Austin in 1976 and has
Mr. Chibib joined the IBM Research Division
management. He received an IBM worked in the circuit technology area. He
in Yorktown in 1965. There he worked on
Outstanding Contribution Award for his work received a MSEE degree from the University
computer assisted instruction and symbolic
in developing a chemical recovery process. of Vermont in 1982. He is currently a senior
execution of programs. In 1977, he joined the
He holds a patent for a circuit line repair tool. engineer and manager of the AESD Advanced
OPD Architecture group in Austin and
Mr. Burghart received his BS in Electrical Circuit Technology department.
participated in the early PL.8 compiler work
Engineering from Wichita State University in
for ROMP. He is currently a member of the
1965.
PL.8 Tools group for IS&CG.

150
Charles K. Erdelyi nodal model and the Memory Control portion joined IBM in 1982. Ms. Greene has worked
of the MMU memory management chip. Mr. on several software projects for the
General Technology Division, Essex Junction,
Freeman has had principal responsibility for Displaywriter and the IBM RT PC, doing
Vermont
M M U since 1983. He received a BS degree in design, modelling, and evaluation of user
Electrical Engineering from Tennessee interfaces.
Mr. Erdelyi was born in Hungary in 1938 and
Technological University in 1975 and an MS
came to the U.S. in 1957. He joined IBM as a
degree from the University of Texas at Austin Randall D. Groves
Customer Engineer in 1958 and, with the
in 1981.
exception of military and educational leaves, Engineering Systems Products, Austin, Texas
has been with the company since. He holds a
Willie T. Glover, Jr.
BSEE and MSEE from MIT and an MSEE Mr. Groves is a staff engineer in the
from the University of Vermont. He has spent Engineering Systems Products, Austin, Texas Advanced Microprocessor Development
most of his engineering career in circuit group in Austin. He jOined IBM in 1979 in
design activities. He is currently a senior Mr. Glover is a senior associate engineer in Manassas, VA and transferred to the MMU
engineer responsible for CMOS macro Advanced Microprocessor Design. He joined chip design team in Austin in 1982. Mr.
development. I BM in 1980 after receiving a BS in Electrical Groves received BS degrees in Electrical
Engineering from the University of Tennessee, Engineering and in Business Administration
Gregory C. Flurry Knoxville. Mr. Glover is a member of Tau from Kansas State University in 1978 and
Beta Pi, Eta Kappa Nu, and the Institute of 1979. He is a member of Tau Beta Pi, Eta
Engineering Systems Products, Austin, Texas
Electrical and Electronics Engineers. Kappa Nu, Blue Key, and Phi Kappa Phi.
Mr. Flurry joined the Office Products Division
Mark S. Greenberg G. Glenn Henry
of IBM in Lexington, KY in 1973. He worked
in Advanced Ink Jet Technology and on an Engineering Systems Products, Austin, Texas Engineering Systems Products, Austin, Texas
electronic typewriter using that technology.
He spent two years at the IBM Research Mr. Greenberg is a senior programmer who Mr. Henry is an IBM Fellow and is the
Laboratory in Yorktown Heights, NY working has been working on the design and manager of Hardware and Software System
on various projects related to office implementation of the VRM since 1982. He Development for the IBM RT PC. He joined
workstations. He transferred to Austin in 1980 joined IBM FSD at the Cape Canaveral IBM in 1967 in San Jose, CA, and has been
to work on the RT PC virtual terminal Facility in 1965 after receiving a BS in involved in the design and management of the
subsystem. Mr. Flurry received a BS in mathematics from MIT. IBM 1800, IBM System/3, the IBM System/32,
electrical engineering from Vanderbilt and the IBM System/38. He has received
University and an MS in electrical engineering Carolyn Greene several formal awards, including an IBM
from the University of Kentucky. He is corporate award in 1982 for his work on the
Engineering Systems Products, Austin, Texas
currently an advisory programmer in RT PC System/38. Mr. Henry received a BS and an
system architecture. MS in mathematics in 1966 and 1967 from the
Ms. Greene is a staff programmer and is
California State University at Hayward, and is
currently technical assistant to the manager
C. P. (Chuck) Freeman a member of the ACM and IEEE.
of the AESD Systems Extensions group. She
Engineering Systems Products, Austin, Texas was the architect responsible for the
Phillip D. Hester
externals of the Usability Services package.
Mr. Freeman is a staff engineer assigned to Ms. Greene received a BS in Information and Engineering Systems Products, Austin, Texas
AESD Memory Management Design. He Computer Science from Georgia Institute of
joined IBM in 1976 and the ROMP project in Technology in 1980. After two years of Phil Hester is a senior engineer and manager
1980. He designed a portion of the ROMP graduate study on user interface design, she of Hardware Architecture for the IBM RT PC.

151
His area's responsibilities include hardware from the University of Missouri at Rolla in Jerry Kilpatrick
architecture, performance, compatibility, and 1964, and an MSEE from the University of
follow-on requirements. He joined IBM in Kentucky in 1966. Engineering Systems Products, Austin, Texas
1976 after receiving a bachelor's degree in
Electrical Engineering from the University of M. E. Hopkins Jerry Kilpatrick joined IBM in 1968 after
Texas at Austin. His previous experience receiving a BS in Mathematics from
IBM Research Division, Yorktown Heights, Centenary College. He initially worked as a
includes design of various portions of ROMP,
New York Systems Engineer in the Shreveport, LA
lead engineer for MMU, and management of
the Microprocessor and Memory Management Branch Office. In 1969 he took an educational
Martin Hopkins is manager of compilers in the leave of absence to do graduate work in
department. While at IBM, he received an MS
Advanced Minicomputer Department of the Computer Science at the University of North
degree in Engineering from the University of
IBM Research Division. He spent ten years Carolina at Chapel Hill. After receiving his
Texas in 1981.
with Computer Usage Co., a software house, PhD in 1976, Dr. Kilpatrick returned to IBM at
mainly working on compiler development. In Austin. He was the User Interface Design
Harrell Hoffman
1969 he joined the Research Division. Since manager for the RT PC.
Engineering Systems Products, Austin, Texas then he has worked on computer architecture
as well as compiler development and Rajan Krishnamurty
Mr. Hoffman joined IBM in 1976 at Houston language design. In 1985 he received a
where he was involved with programming the Corporate Award for his work on the PL.8 Engineering Systems Products, Austin, Texas
space shuttle on board computers. He worked language and compiler. Mr. Hopkins has a BA
as a programmer on the 5520 Administrative in Philosophy from Amherst College. Rajan Krishnamurty, a staff programmer in
System in Austin before moving to his current Austin, TX received a BSEE degree from the
position of staff engineer with the advanced University of Houston, 1976, and a MSEE
John W. Irwin
microprocessor group. Mr. Hoffman has a MS degree from the University of Texas, 1983.
in Computer Science and BS degrees in Engineering Systems Products, Austin, Texas After joining IBM in 1976 at Austin, TX he
Electrical Engineering and in Mathematics. worked on the media attachment hardware on
John W. Irwin is a senior engineer in the Displaywriter from 1979 to 1982. After
John T. Honaway Advanced Eng!neering Systems Development working on a number media proposals for
He joined iB~ as a Customer Engineer in follow-on pioducts, he joined the RT PC
Engineering Systems Products, Austin, Texas 1956 after serving as a USAF jet fighter pilot, program in 1983 where he was responsible
then transferred to the Poughkeepsie for development of the PC AT coprocessor
Mr. Hollaway is the manager of the AESP Laboratory in 1958. He participated in the services licensed program product. Mr.
Workstation Development group. He has design of Hypertape I and II, the 2415 Tape Krishnamurty holds two U.S. patents and has
development and product engineering Unit, and the 2803 Mod I and II Tape had nine articles published in the IBM
responsibility for RT PC. Mr. Hollaway joined Controllers. He received an IBM Corporate Technical Disclosure Bulletin.
IBM in 1964 as a junior engineer at Award in 1974 for development of the GCR
Lexington, KY. He worked on such projects recording method and an IBM Eighth Level Thomas G. Lang
as the Tape Transmission Unit, Invention Award in 1985 in recognition of 24
communication controls for the MCIST, the Engineering Systems Products, Austin, Texas
patent applications and 28 patent
Small Business Terminal, and Communicating publications.
Mag Card I. Mr. Hollaway entered Mr. Lang is a staff programmer for the
management in 1972. His management Advanced Engineering Systems Development
assignments include Dictation Systems, OS/6, group, where he works on design and
communicating Mag Card, and Displaywriter implementation of the VRM. He joined IBM in
1/0 and RAS. Mr. Hollaway received a BSEE 1978 in Rochester, MN, after receiving a BS

152
in Computer Science and Electrical Alan MacKay Peter E. McCormick
Engineering from Michigan State University.
Engineering Systems Products, Austin, Texas General Technology Division, Essex Junction,
In Rochester, he worked on SNA
Vermont
communications programming for the S/32
After receiving a BS degree in Computer
and S/34. He transferred to Austin in 1980,
Science from Brigham Young University, Mr. Mr. McCormick received a BSEE degree from
where he was involved with operating
MacKay joined the IBM Office Products Worcester Polytechnic Institute in 1965 and a
systems development on the 5280 Data Entry
Division at Lexington, KY in 1974. There he MSEE degree from Michigan State University
System before joining AESD.
worked on Software Development Tools. He in 1967. He joined IBM in 1967 at East
received his MS in Computer Science from Fishkill, NY, transferred to Manassas, VA in
S. A. Lerom
the University of Kentucky in 1977. In 1977, 1970, and to Essex Junction, VT in 1978. His
Engineering Systems Products, Austin, Texas he joined the OPD Architecture group in work experience has been in bipolar and FET
Austin and participated in the early PL.8 circuit and chip design spanning SSI, LSI, and
During the development of the RT PC system, compiler work for ROMP. He is currently a VLSI digital integrated circuits. Development
Ms. Lerom managed the AIX Configuration member of the PL.8 tools group for IS&CG. projects have included masterslice, master
department. She currently is Technical image, and custom chip designs. He is
Assistant to G. G. Henry. Ms. Lerom received F. T. May currently an advisory engineer in the
a BA in Mathematics from the University of Microcomponent Design area of the IBM
Engineering Systems Products, Austin, Texas
Minnesota. She joined IBM in 1976 in General Technology Division.
Rochester, MN, and has worked in
Mr. May joined IBM as an associate engineer
communications software development on T. L. Mothersole
in Lexington, KY in 1961, with BS and MS
S/3 CCP, S/34, and 5280. She transferred to
degrees in Electrical Engineering from the Engineering Systems Products, Austin, Texas
Austin in 1980 and entered management in
University of Kentucky and the University of
1981 as manager of a SNA Communications
Tennessee. In 1968, he moved to Austin to Ms. Mothersole received her BA in Computer
department.
head a new development laboratory in Science from the University of Texas at
conjunction with the release to production Austin in 1978. She spent 3 years at Motorola
Larry Loucks
of the Mag Card I. In 1973, he was promoted Semiconductors in the Computer Aided
Engineering Systems Products, Austin, Texas to director of the Office Product Division Design group, working on engineering tools
engineering organization in Lexington, KY. He for circuit analysis and logic simulations. She
Larry Loucks is a member of the IBM Senior was vice president of OPD development from joined IBM in 1982 in the Displaywriter
Technical Staff and is the lead architect of 1973 to 1976 and then returned to Austin as Display Support group. After working on
the RT PC system. He received a BA in vice president of office systems with several screen management research
Mathematics from Minot State University in responsibility for Austin manufacturing and projects, she joined the design and
Minot, ND. Larry joined IBM in 1967 in the development. He was director of the Austin implementation team building coprocessor
Fargo, ND branch office. In 1970 he laboratory from 1977 to 1978. Mr. May was terminal support in the VRM.
transferred to Raleigh, NC, where he worked the IBM RT PC Workstation Development
on QTAM, TCAM, and SNA. In 1977 he Manager and is currently responsible for Tom Murphy
transferred to Austin, where he has worked future workstation development.
Engineering Systems Products, Austin, Texas
on the 5520 and the RT PC.
Mr. Murphy is a senior programmer. He
received a bachelor's degree in Education
and a master's degree in Computer Science

153
from the University of Wisconsin. Mr. Murphy John C. O'Quin and has defined the design system and
joined IBM in 1967 and has been involved methodology and directed their
Engineering Systems Products, Austin, Texas
with language implementation on System 3, implementation. He is a senior engineer
5100 Series, and 5280. Currently he serves in the Advanced Microprocessor Development
Jack O'Quin joined IBM in 1977, after
as lead programmer for the usability package. Function.
receiving a BA in Computer Science from the
University of Texas at Austin. He began doing
Khoa D. Nguyen P. T. Patel
operating system work while employed by the
Engineering Systems Products, Austin, Texas University Computation Center. Prior to Engineering Systems Products, Austin, Texas
joining the RT PC project, he worked on the
Mr. Nguyen is an advisory engineer in the IBM 5520 operating system. After assisting in Mr. Patel joined IBM in Manassas, VA in June
system design department of the AESD the initial bringup of the RT PC prototype 1973 upon receiving a MSEE degree from the
group, where he worked on the design of the hardware, he worked at improving the code University of Connecticut. He worked in
virtual terminal subsystem. He joined the IBM produced by the C compiler. This led to various bipolar circuit design activities in
Office Products Division at Austin, TX in 1975 redefining the subroutine linkage interface. He Manassas. He transferred to Burlington in
and worked on hardware and software also was active in developing the virtual 1978 where he worked in the 1(2)L circuit
projects related to OS/6, ROMP, and memory paging supervisor in the VRM. technology. He transferred to Austin in 1980
Displaywriter. He received a BS degree in and has worked in the area of VLSI design.
Electrical Engineering and Computer Sciences John T. O'Quin He has been the lead designer on the
from the University of California at Berkeley in memory management chip and made
Engineering Systems Products, Austin, Texas
1974 and a MS degree in Electrical numerous contributions to the design
Engineering from the University of Texas at methodology. He is currently an advisory
Mr. O'Quin is an advisory programmer who
Austin in 1980. engineer in the Advanced Microprocessor
has been working on the design and
Development Function.
implementation of the VRM since 1982. He
Jack E. Olson
joined IBM in 1977 in Austin, TX after
Sheldon L. Phelps
Engineering Systems Products, Austin, Texas receiving a MSEE degree from Georgia Tech.
Engineering Systems Products, Austin, Texas
Jack Olson is a senior programmer with the Mukesh P. Patei
Advanced Strategic Products Development Mr. Phelps is a staff engineer in Advanced
Engineering Systems Products, Austin, Texas
Group in ESD. He joined IBM as an associate Engineering Systems Development with
programmer in 1969 at the Application RT PC System Architecture. His primary work
Mr. Patel received his MSEE degree from
Development Center in Des Plaines, IL. on RT PC is on the I/O Channel Architecture.
Utah State University in June 1966 and joined
Before coming to Austin he was in the DB/DC He joined IBM in 1969 at San Jose working
the General Electric Company in Lynchburg,
Development Group in the Santa Teresa on the System/3 file system. In 1972 he
VA, in the Communication Division. In June
Laboratory where he worked on the CICS and moved to Rochester, MN Development
1968 he joined IBM in East Fishkill, NY where
IMS projects. In Austin he was a member of Laboratory to work on processor
he worked on bipolar device characterization
the 5520 Administrative System development development for the 3657 Ticket Unit. Mr.
and modeling. He transferred to Manassas,
team before joining the RT PC development Phelps received his BSME from Los Angeles
VA in 1971, where he worked on a variety of
group. He holds a BS in Mathematics from State College in 1961 and his MSEE from the
bipolar and FET circuit designs and chip
the Illinois Institute of Technology and an University of California at Santa Barbara in
design systems. He continued to work in this
MBA in Operations Research from 1969. Prior to working for IBM, he worked for
area until his transfer to Austin, TX in 1978.
Northwestern University. the Naval Civil Engineering Laboratory at Port
He has been a key member of the design
Hueneme, CA.
team on the ROMP and MMU chip designs

154
Mark D. Rogers Research Center and in 1982 transferred to Ed Seewann
the IBM Communications Products Division
Engineering Systems Products, Austin, Texas Engineering Systems Products, Austin, Texas
laboratory in Austin, TX. Currently he is
Manager of System Architecture for the IBM
Mark Rogers joined IBM in 1982 after Mr. Seewann joined IBM in Austin in 1969
RT PC. Dr. Sauer has published three
receiving a BA in Computer Science from the after receiving an MEE degree from Rice
textbooks, Computer System Performance
University of Texas at Austin. He is a senior University. He has had numerous circuit
Modeling, co-authored by K. M. Chandy,
associate programmer in the Advanced design responsibilities and his development
Simulation of Computer Communication
Engineering Systems Development group. On work includes circuit designs for the Mag
Systems, co-authored by E.A. MacNair, and
the IBM RT PC he has been involved in the Card I, Mag Card II, and System/6. He is
Elements of Practical Performance Modeling,
design and implementation of the VRM Virtual currently an advisory engineer in the
co-authored by E.A. MacNair. He has
Memory Manager. Advanced Microprocessor Development
received an IBM Outstanding Innovation
Function.
Award for creation and basic design of the
Ron Rowland
Research Queueing Package (RESQ). Dr.
Richard O. Simpson
Engineering Systems Products, Austin, Texas Sauer is a member of the Association for
Computing Machinery. Engineering Systems Products, Austin, Texas
Mr. Rowland, a staff engineer, received a
BSEE degree from the University of Cincinnati Martin S. Schmookler Richard Simpson is a senior programmer in
(1978) and attended graduate classes at the the Advanced Microprocessor Development
Engineering Systems Products, Austin, Texas
Electrical Engineering department of the department of IBM's Engineering Systems
University of Texas at Austin. Prior to his Products group, working on ROMP
Dr. Schmookler, who is a member of the
present position in memory systems architecture. He joined IBM in 1969 and has
Microprocessor Development group in Austin,
development for the RT PC, he had worked worked in several IBM divisions on various
joined IBM in 1956 at the Poughkeepsie, NY
on communication controllers for the IBM projects, including J ES2 and the 5520
laboratory. There he worked on the designs
5520 Administrative System, memory systems Administrative System. He has been involved
of many large systems, including Stretch,
for the IBM System/36, and memory systems with ROMP architecture since 1981. He holds
7074, 7094, System/360 Models 91 and 195,
for the IBM Displaywriter. He has authored BA and MEE degrees from Rice University
3033, and the 3081. He received a BSEE from
papers on design for testability, gate array and is pursuing studies for a PhD in
Pennsylvania State University in 1956, an
design methodologies, and on various Computer Science at the University of Texas
MSEE from Syracuse University in 1964, and
aspects of memory systems design. at Austin.
a PhD from Princeton University in 1969
through the IBM Resident Study Fellowship
Charles H. Sauer Scott M. Smith
program. In 1976, he was a Visiting Associate
Engineering Systems Products, Austin, Texas Professor in the Computer Sciences Engineering Systems Products, Austin, Texas
department at the University of Texas at
Dr. Sauer received his BA in mathematics and Austin, where he is currently an adjunct Mr. Smith joined IBM in Austin in 1978
PhD in computer sciences from the University associate professor. Dr. Schmookler has working in test tool development for the
of Texas at Austin in 1970 and 1975, received two IBM Invention Achievement Systems Assurance function and became
respectively. He joined IBM at the Thomas J. awards, and is a member of Tau Beta Pi, Pi manager of test tool development in 1980. In
Watson Research Center in 1975. From 1977 Mu Epsilon, Eta Kappa Nu, and the Institute 1983 he transferred to Advanced Engineering
to 1979 he was an Assistant Professor of of Electrical and Electronics Engineers. Systems Products Development, where he
Computer Sciences at the University of Texas has been involved with floating point
at Austin. In 1979 he returned to the Watson accelerators. He received a BSEE from the

155
University of Texas at Austin in 1969 and an BS degree in Electrical Engineering from the Dick Verburg
MSEE from the University of Maryland- University of Texas at Austin. He was
Engineering Systems Products, Austin, Texas
College Park in 1972. Prior work experience technical lead programmer in the AIX
includes Texas Instruments Incorporated and Configuration group for the RT PC.
Mr. Verburg is a staff programmer. He
the University of Texas Applied Research
received bachelor's degrees in Marketing and
Laboratories. Mr. Smith is a member of Tau Abraham Torres Computer Science from Michigan
Beta Pi, Eta Kappa Nu, and the IEEE
Engineering Systems Products, Austin, Texas Technological University. Mr. Verburg joined
Computer Society.
IBM in 1978 and has been involved with
Mr. Torres is an advisory engineer working in language implementation on the 5280.
T.A. Smith
the Advanced Microprocessor Design group. Currently he serves as lead programmer for
Engineering Systems Products, Austin, Texas He joined IBM in 1973 after receiving a BS the dialog manager.
degree in Electrical Engineering from the
Todd Smith is a staff programmer. He joined University of Texas at EI Paso and has done Donald E. Waldecker
IBM at Austin in 1984. He received a BS in graduate work at the University of Texas at Engineering Systems Products, Austin, Texas
Mathematics and a BS in Electrical Austin. He worked in MOSFET circuit design
Engineering from MIT and an MS in Computer and in the Design Automation group Mr. Waldecker is a senior engineer and
Science from SMU. He is a member of the supporting Austin's development lab. In 1978, manager of Microprocessor Development. He
RT PC Architecture department and worked he joined the ROMP group and worked on the joined IBM in 1961 in the Federal Systems
on the design of the Virtual Memory Manager logic design of ROM P. He also had Division, Owego, NY and transferred to Austin
and other VRM components. responsibility for the ROMP design in 1978. Since then he has been involved in
methodology and testing. the management of ROMP/MMU chip
Joe C. St. Clair
development and system related application
Engineering Systems Products, Austin, Texas John D. Upton of these chips. While in Owego, he worked on
Engineering Systems Products, Austin, Texas development and management of numerous
Mr. St. Clair is an advisory engineer in militarized computers, data links, and
Display Subsystem Development. He has Mr. Upton is an advisory engineer in the Full computer system integration activities. Mr.
been working in the area of display adapter Function CPU development area of the VValdecker has a BSEE from the University of
design since 1980. He joined IBM in 1976 Advanced Engineering Systems Development Missouri - Rolla, and a MSEE from
after receiving a MS degree from the group. He received his BS in Physics in 1971 Syracuse University. He is a member of Tau
University of Illinois at Urbana-Champaign. In and a BS in Electrical Engineering in 1977 Beta Pi, Eta Kappa Nu, and Phi Kappa Phi.
1971 he received a BSEE degree from the from Lamar University. He joined IBM in 1977
University of Texas at Austin. He is a member at Boulder, CO and moved to Austin in 1980. Frank C.H. Waters
of IEEE, ACM, Eta Kappa Nu, and Tau Beta He has been involved in the areas of logic Engineering Systems Products, Austin, Texas
Pi. design, simulation, and testing on several
microprocessor-based IBM products. He Mr. Waters joined IBM in 1962 after
Lee Terrell joined the RT PC development group as graduating from Oklahoma State University
Engineering Systems Products, Austin, Texas design team leader for the 6151 system with a BS in Physics. He has worked as a
board. He later assumed design responsibility technical writer, programmer, and
Lee Terrell is an advisory engineer in the for the 6150 system board as well. programming manager on projects such as
Advanced Engineering Systems Development the 7040/7044, OS/360 Release 1,
group. He joined IBM in 1974 after receiving a TERMTEXT, OSjVS1 and VS2, VSAM, 3850

156
Mass Storage System, 8100 Data Base and C. Edward Williams Electrical Engineering from Texas A & M
Transaction Management System, and AIX University in 1975. For the past several years
Engineering Systems Products, Austin, Texas
user interface design. Mr. Waters is currently he has worked in the microprocessor design
an advisory programmer on educational leave area, mostly in the design of the bus interface
Mr. Williams is a staff engineer for IBM. He is
of absence from IBM to pursue graduate portions of various LSI designs.
currently a technical member of the team
studies in the cognitive and social
developing expert system diagnostics for a
psychological aspects of the human use of George M. Yanker
personal workstation. Mr. Williams attended
computers.
Atlantic Christian College in Wilson, North Engineering Systems Products, Austin, Texas
Carolina. He was on the 5258 Ink Jet Printer
T. G. (Tom) Whiteside
Development team and the Displaywriter Mr. Yanker worked as an advisory engineer
Engineering Systems Products, Austin, Texas Diagnostics Development team. He has won on the RT PC, first in the Development
three Informal awards and one IBM Means Engineering group and then as manufacturing
Mr. Whiteside is currently manager of AESD Service award. engineering's design-for-robotics coordinator
Memory Management Design, with between development and manufacturing
responsibility for both the ROMP and MMU Peter Y. Woon engineering. He joined IBM in 1964 with a BS
chips. He joined IBM in 1982 and worked on degree in Mechanical Engineering from the
Engineering Systems Products, Austin, Texas
the ROMP project for about a year. He then University of Arkansas and received an MS
participated in the RT PC product definition degree in Engineering Mechanics from the
Dr. Woon received his BS in Physics from the
as a member of AESD Hardware Architecture University of Kentucky in 1968. His past
University of Toronto, MS in Mathematics
until his return to the ROMP area in 1984. Mr. assignments were in the development and
from the University of Waterloo, and PhD in
Whiteside received a BS degree in Electrical design of Austin's Mag Card I, Mag Card II,
Computer Science from New York University.
Engineering from the University of Texas at Office System 6, and Displaywriter. He
He joined IBM in 1962 as a programmer in
Austin in 1975. Prior to joining IBM, Mr. received an Outstanding Contribution Award
the New York Programming Center, and has
Whiteside worked at the Motorola in 1973 for design work on the Mag Card II
since worked in research and development
Government Electronics Division from 1975 to and he received an IBM Invention
divisions in areas such as languages,
1981 and the Motorola MOS Division Achievement Award in 1985.
compilers, operating systems, computer
Microprocessor Design Group from 1981 to
architecture, and advanced software
1982.
technology. He was manager of OPD Austin
Architecture, and then manager of Advanced
Kenneth G. Wilcox
Microprocessor Software Architecture and
Engineering Systems Products, Austin, Texas Tools. At present, he is manager of Software
Technology at the IBM Japan Science
Mr. Wilcox joined IBM in 1957 in Owego, NY Institute in Tokyo. Dr. Woon is a member of
where he worked on test and design of Tau Beta Pi and Eta Kappa Nu.
Federal Systems Division computers and
computer systems for projects such as C. G. (Chuck) Wright
TITAN, SATURN missiles, and F15 and A7
Engineering Systems Products, Austin, Texas
aircraft. For the past two years he has been
the development engineer for the RT PC
Mr. Wright, an advisory engineer in the
processor card. He graduated from DeVry
Advanced Microprocessor Development
Technical Institute in 1954 and has taken
group in Austin, received a BS degree from
undergraduate courses at the University of
Trinity University in 1974, and an MS in
New York and the University of Texas.

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International Business Machines Corporation

Engineering Systems Products

Independent Business Unit
472 Wheelers Farms Road
Milford, CT 06460

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SA23-1057-00

SA23-1057
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