AN966

Interfacing SPI Serial EEPROMs to Microchip PICmicro Microcontrollers

Author: Martin Kvasnicka Microchip Technology Inc. Microchip Technology has addressed these needs by offering a full line of serial EEPROMs covering industry standard serial communication protocol for two-wire (I2C), three-wire (Microwire), and SPI communication. Serial EEPROM devices are available in a variety of densities, operational voltage ranges and packaging options. This application note provides assistance and source code to ease the design process of interfacing a Microchip mid-range PIC16F877 microcontroller to a Microchip SPI serial EEPROM. The hardware SPI port on the microcontroller Master Syncronous Serial Port (MSSP) provides a simple three-wire connection to the EEPROM with no external glue logic. Figure 1 describes the hardware schematic for interfacing between Microchips SPI memories and the Microchip PIC16F877 microcontroller. The software was written assuming these connections.

INTRODUCTION
There are many different microcontrollers on the market today that are being used in embedded control applications. Many of these embedded control systems need nonvolatile memory. Because of their small footprint, byte level flexibility, low I/O pin requirement, low power consumption, and low cost, serial EEPROMs are a popular choice for nonvolatile storage.

FIGURE 1:

CIRCUIT FOR PIC16F877 AND 25XXX SERIES DEVICES

MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS RE0/RD/AN5 RE1/WR/AN5 RE2/CS/AN7 VDD VSS OSC1/CLKIN OSC2/CLKOUT RC0/T10S0T1CKI RC1/T10SI/CCP2 RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 RB7/PGD RB6/PGC RB5 RB4 RB3/PGM RB2 RB1 RB0/INT VDD VSS RD7/PSP7 RD6/PSP6 RD5/PSP5 RD4/PSP4 RC7/RX/DT RC6TX/CK RC5/SDO RC4/SDI/SDA RD3/PSP3 RD2PSP2

PDIP (600 MIL)

PIC16F877

Vcc

CS SO WP Vss

1 2 3 4 25XXXXX

8 7 6 5

Vcc HOLD SCK SI

Note:

CS, WP and HOLD pins should all have pull-up resistors (~10k ohms).

2004 Microchip Technology Inc.

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FIRMWARE DESCRIPTION
The program shows individual features of the SPI protocol and gives code samples of opcodes so that basic building blocks of a system can be put together for rapid deployment of electronics using SPI EEPROMs. The opcodes used in the program are Write Enable (WREN), Write, Read, Read Status Register (RDSR) (used in the program for WIP (Writein-Process) polling), and Write Disable (WRDI). The oscilloscope pictures have markers that are shown from CS enable to CS disable for ease in reading. The data sheet version of the waveform is below the actual oscilloscope picture. The MSSP module is set up for Mode 1,1 operation at approximately 625 kHz. The code is written in modules and commented so changing modes, speeds, and modifying commands, such as sequential reads and page writes, are simple. The values represented in this application note are all hex values.

WRITE ENABLE
Figure 2 shows an example of the Write Enable command. Chip Select is brought low (active) and the opcode is sent out through the MSSP port. The Write Enable command must be given before a write is attempted to either the array or the Status Register. The WEL bit can be cleared by issuing a Write Disable command (WRDI), or it is automatically reset if the device is powered down or a write cycle is completed. Instances of this command can be found in the firmware by searching for WREN.

FIGURE 2:

WRITE ENABLE (WREN)

CS 0 SCK 1 2 3 4 5 6 7

SI

SO

high-impedance

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AN966
READ STATUS REGISTER TO CHECK FOR WEL BIT
Figure 3 shows an example of the Read Status Register command to check for the Write Enable Latch (WEL) bit. The WEL bit must be set before a write is attempted to either the Status Register or the array. It is good programming practice to check for the bit to be set before attempting the write. Once again the device is selected using CS and the opcode 0x05 is received. Although it appears that the opcode is received twice, the second 8 bits are dont cares on the Data In pin and act as a dummy byte just to provide clock signals so that the Status Register can be shifted out on the Data Out pin. A value of 0x02 shows that the WEL bit in the Status Register has been set. The device is now ready to do a write on either the Status Register or the array.

FIGURE 3:

READ STATUS REGISTER TO CHECK FOR WEL BIT (RDSR)

CS 0 SCK instruction SI 0 0 0 0 0 1 0 1 data from Status Register 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

high-impedance SO

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WRITE COMMAND (OPCODE, ADDRESS AND DATA)
Figure 4 shows an example of the Write command. For this waveform the device is selected and the opcode 0x02 is received. The High Address byte receives 0x00 followed by the Low Address byte 0x55. Finally, the data is clocked in which is 0xAA. Once the Chip Select is toggled at the end of this command, the internal write cycle is initiated. After the internal write cycle has begun, the WIP bit in the Status Register can now be polled to check when the write finishes, or a delay needs to be added to the microcontroller firmware (~5ms) if the WIP bit is not being polled. This code uses WIP polling.

FIGURE 4:

WRITE COMMAND, ADDRESS AND DATA

CS 0 SCK instruction SI 0 0 0 0 0 0 1 16-bit address 0 15 14 13 12 2 1 0 7 6 data byte 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31

Twc

high-impedance SO

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AN966
DATA POLLING (RDSR CHECK FOR WIP SET)
After a valid Write command is given, the Status Register can be read to check if the internal write cycle has been initiated. It can also be monitored continuously to look for the end of the write cycle. In this case, the device is selected and the opcode 0x05 is received. The Status Register contents are then shifted out on the Data Out pin, resulting in a value of 0x03. Figure 5 shows that both the WEL bit (bit 1) and the WIP bit (bit 0) are set (0x03), meaning the write cycle is in progress.

FIGURE 5:

DATA POLLING (READ STATUS REGISTER TO CHECK WIP BIT)

CS 0 SCK instruction SI 0 0 0 0 0 1 0 1 data from Status Register 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

high-impedance SO

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DATA POLLING FINISHED (RDSR WIP BIT CLEARED)
The code was written to stay in a continuous loop and evaluate the status Register until the WIP bit is cleared. Figure 6 shows the Status Register Read command followed by a value of 0x00 being shifted out on the Data Out pin. This indicates that the write cycle has finished and the EEPROM is now ready for additional commands. The WEL bit is also cleared at the end of a write cycle. This serves as additional protection against unwanted writes.

FIGURE 6:

DATA POLLING FINISHED (RDSR WIP & WEL BITS CLEARED)

CS 0 SCK instruction SI 0 0 0 0 0 1 0 1 data from Status Register 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

high-impedance SO

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AN966
WRITE DISABLE COMMAND
Previously, we showed a Status Register Read to illustrate the WEL bit being set. Figure 7 shows the WEL being set followed by the WRDI command. The Status Register is then read and indicates that the WEL bit has been cleared and the device will no longer accept Write commands to either the array or the Status Register.

FIGURE 7:

RDSR FOR WEL SET AND THEN CLEARED AFTER WRDI COMMAND

CS 0 SCK 1 2 3 4 5 6 7

SI

0 1

high-impedance SO

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CONCLUSION
This is an application note of the basic features of SPI communications using the MSSP module on one of Microchips mid-range devices. The code is highly portable and can be used on many devices that have the MSSP module, possibly with very minor modifications. Using the code provided, designers can begin to build their own SPI libraries to be as simple or complex as needed. The code was tested on Microchips PICDEM 2 Plus Demonstration Board with the connections shown in Figure 1.

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Note the following details of the code protection feature on Microchip devices: Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchips Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as unbreakable.

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchips code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchips products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Companys quality system processes and procedures are for its PICmicro 8-bit MCUs, KEELOQ code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchips quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

2004 Microchip Technology Inc.

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10/20/04

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2004 Microchip Technology Inc.