Interrupt Handling

Interrupt handling
Hebah Kohari
Rathnakar Reddy Bodhireddy
Sheril Dhabriya
Interrupt : A change in execution caused by an external event.

Have device tell OS/CPU it is ready. Requires hardware to support.
OS/CPU can then interrupt what it is doing to:

Determine what device wants service Perform or start the service.
Go back to what OS/CPU was doing.

Determine what service it wants.
Examples of interrupts
Mouse moved. Disk drive at sector/track position(old days).
Keyboard key pressed.

Printer out of paper. Video card wants memory access. Modem sending or receiving. USB scanner has data.
Types of interrupts
Synchronous/Asynchronous: Synchronous if it occurs at the same place, every time the program is executed with the same data and memory allocation. Asynchronous interrupts are those that occur unexpectedly. Internal/External : Internal interrupts arise from illegal or erroneous use of an instruction or data , also called as traps. External interrupts arise from I/O devices, timing device, circuit generated by power supply. Software/Hardware : Software interrupts is initiated by executing an instruction .
General flow
Returns Process in execution
Main Program
Process requires I/O service
I/O Interrupt
Interrupt Service Routine
When a program throws an interrupt a device searching routine is performed. The program is reentered after the interrupt is handled.
Interrupt
RegPC+1
Save the return address of the PCinterrupt addr main program

Determine device; determine whether input or output; I/OA or AI/O PCreg Execute the instructions in the service routine Restore the program control
Interrupt Service Routine Interrupt return
Different types of interrupt systems

Single interrupt systems. Multiple interrupt systems.
Single interrupt system

Finish current instruction. Save program counter in IRL. Load program counter with content of IHL.
2
Single-interrupt system:
inter rupt signal pro gram counte r
inter rupt re turn location IRL
3 1 CPU inter rupt handler location IHL
Multiple interrupt system

Multiple- interrupt system:
2 1 inter rupt signal 1 n pro gram counte r IRL1 IRL2 IRL3 IRL4 3 CPU IHL1 IHL2 IHL3 IHL4
IHLn IRLn
Single and multiple

interrupt controller
inter rupt signal IRL1 IRL2 CPU IRL3 IRL4
IRLn
status control
interrupt lines
IHL1
Device CPU
IHL2 IHL3 IHL4

IHLn
Interrupt handlers
Interrupt handlers are the routines that are called when an interrupt is detected.
Interrupt handlers are usually short sections of code that are designed to handle the immediate needs of the device and return control to the operating system or user program.
Steps in handling interrupts

Disable further interrupts. Store current state of program. Execute appropriate interrupt handling routine. Restore state of program. Enable interrupts. Resume program execution.
Flowchart of basic interrupt mechanism

Fetch Instruction Increment PC Decode and Execute instr.
No
Int request line active
Restore PC
Yes Interrupt
Store PC
service Routine
Masking interrupts
It is sometimes advantageous to disable interrupts while the processor is performing some critical operation (like handling another interrupt). On some systems there may be one or more high priority interrupts that cannot be masked.
Interrupt handling
Interrupt handling in a PC: On a PC there are 24 separate interrupt lines that can be asserted. The appropriate interrupt handler is invoked based on the interrupt number. Interrupt handling in MIMS: On a MIPS machine the Cause register is filled in with an appropriate code which allows the interrupt handler to figure out the cause of the interrupt
Interrupt handling OS ISSUES

When an interrupt is serviced the processor must be able to execute without being interrupted. It must have the capability of temporarily disabling the interrupt atomically. If an interrupt occurs while an interrupt service is ongoing, it is simply deferred and considered a pending interrupt. It is serviced after the current request terminates. The MIPS RISC architecture does not allow user programs to access beyond 0x8000 0000 (the upper half of the memory). The exception handler is in this part of memory and only executed in kernel mode.
Changing the mode back to the mode before the exception occurs is accomplished via the instruction rfe (return from exception). The mode information is stored in the Status Register and can only be written in the kernel mode. It can be read in user mode. The Status Register contains a simple hardware stack that can hold up to three levels of information: old, previous, current. On exception: old previous current
On rfe: old previous current
A reentrant exception handler is written such that it is itself interruptible. Interrupts and traps are assigned priorities. A check is made for pending interrupt requests after every instruction. If there is a pending interrupt request, the priority is checked. If it has a higher priority than the currently running code, it serviced first, otherwise it is ignored
Enabling and disabling of interrupts can be done either by using an interrupt mask (IPM) applied to bits 8-15, or the IE (applied to bit 0) of the Status Register. The execution of rfe enables interrupts. rfe and jr must be executed atomically.
In the MIPS RISC architecture, jr is actually executed first and does not take effect until after rfe is executed.
Interrupt priority
When multiple I/O devices are present in an interrupt system, two difficulties must be resolved:
How to handle interrupt requets from more than one device at a time. Identification of the selected device.
Assigning priority levels to each device means that highest level priorities will be serviced before lower levels.
Types of priority implementations

Software Priority : When the polled data is collected by the servicing routine the program will then assign an order of servicing. Hardware Priority : This implementation selects the ordering and generates the vectored information that identifies the selected device. Daisy Chain Priority Control : It distributes the priority selection so that each device has part of the ordering logic located with the device controller.
Interrupt Service
Interrupt service is a procedure in which its address specifies the desired service and is typically called ISR (interrupt service routine).
Centralized dispatch: exception handler decodes the cause. (MIPS style)

Vectored dispatch: the hardware based on a vector number invokes the appropriate service. (Power PC)
The MIPS has a special coprocessor CPO, that is dedicated to exception handling.
Status register Entry hi Entry low Index register Context register Random register TLB BdAddr register
Cause register
EPC register
PRid REGISTER
MIPS CPO
EPC: A 32 bit register used to hold the address of the affected instruction. Register 14 of coprocessor 0. Cause: A register used to record the cause of the exception. In the MIPS architecture this register is 32 bits, though some bits are currently unused. BadVAddr: Register contains memory address at which memory reference occurred. Register 8 of coprocessor 0. Status: interrupt mask and enable bits.
Status register
15 8 MASK 5 4 K 3 2 E 1 0 E K E K
Mask = 1 bit for each of 5 hardware and 3 software interrupt levels. 1 enables interrupts, 0 disables interrupts
K = kernel/user; 0 = was in the kernel when interrupt occurred 1 = was running user mode;
E = interrupt enable; 0 means disabled, 1 means enabled

Interrupt handler runs in kernel mode with interrupts disabled When interrupt occurs 6 LSB shifts left 2 bits, sets 2 LSB to 0.
Cause register
15 10 5 2
Pending
Code
Pending interrupt 5 hardware levels: bit set if interrupt occurs but not yet serviced. Handles cases when more than one interrupt occurs at same time, or records interrupt requests when interrupts disabled. Exception Code encodes reasons for interrupt.
Cause register details

0 (INT) => external interrupt. 4 (ADDRL) => address error exception (load or fetch) 5 (ADDRS) => address error exception (store). 6 (IBUS) => bus error on instruction fetch. 7 (DBUS) => bus error on data fetch 8 (Syscall) => Syscall exception 9 (BKPT) => Breakpoint exception 10 (RI) => Reserved Instruction exception 12 (OVF) => Arithmetic overflow exception
Summary
An interrupt is one class of exception. An interrupt can occur at any time. Hardware and software are needed to support interrupt handling. The hardware must choose the appropriate time in which to interrupt the executing program and transfers control to an exception handler. The current state of the interrupted program must be saved.
Summary
The exception handler also determines which event has caused the exception and decides what should be done based on it. It must also save register values being used by the interrupted program and restore them before returning control to the interrupted program.
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Interrupt Handling

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Interrupt handling

Interrupt : A change in execution caused by an external event.

OS/CPU can then interrupt what it is doing to:

Go back to what OS/CPU was doing.

Keyboard key pressed.

Process requires I/O service

Interrupt Service Routine

Save the return address of the PCinterrupt addr main program

Interrupt Service Routine Interrupt return

Different types of interrupt systems

Single interrupt system

inter rupt re turn location IRL

3 1 CPU inter rupt handler location IHL

Multiple interrupt system

Single and multiple

IHL2 IHL3 IHL4

Steps in handling interrupts

Flowchart of basic interrupt mechanism

Int request line active

Interrupt handling OS ISSUES

Types of priority implementations

Centralized dispatch: exception handler decodes the cause. (MIPS style)

E = interrupt enable; 0 means disabled, 1 means enabled

Cause register details

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