Lecture Instructions Addressing Mode Timing Diagram
Lecture Instructions Addressing Mode Timing Diagram
Lecture Instructions Addressing Mode Timing Diagram
RAL
RAR
LDAX B
STAX B
PCHL
DAA
IN 02H
OUT 03H
ADD M
Addressingmode of 8085
Microprocessor
2
ADDRESSING MODES
Various ways of specifying the operands or
various formats for specifying the operands is
called addressing mode
8-bit or 16-bit data may be directly given in
the instruction itself
The address of the memory location, I/O port
or I/O device, where data resides, may be
given in the instruction itself
In some instructions only one register is
specified. The content of the specified register
is one of the operands. It is understood that
the other operand is in the accumulator.
ADDRESSING MODES
Some instructions specify one or two registers.
The contents of the registers are the required
data.
In some instructions data is implied. The most
instructions of this type operate on the content of
the accumulator.
ADDRESSING MODES
Implicit addressing: Source of the operand is
directly specified in the instruction itself.
CMA
Immediate addressing : Operand is directly given
in the instruction.
MVI A, 05H
ADI 06H
Direct addressing – The address of the operand is
directly specified in the instruction - STA 2400H,
IN 02H
Indirect addressing- the address of the operands
are not directly specified in the instruction.
ADD M
ADDRESSING MODES
Register addressing
In register addressing mode the operands are in the
general purpose registers
MOV A, B
ADD B
Register indirect addressing
Memory location is specified by the contents of the
registers
LDAX B, STAX D
TIMING DIAGRAM
Opcode Fetch
T1 T2 T3 T4
CLX
A15
20H High-Order Memory Address Unspecified
A8
Low-Order
AD7
05H 4FH Opcode
AD0
Memory Address
ALE
RD
TIMING FOR EXECUTION OF THE
INSTRUCTION MVI A,32H
M1 Opcode Fetch M2 Memory Read
T1 T2 T3 T4 T1 T2 T3
CLX
A15
20H High-Order Memory Address Unspecifie 20H High- Order Memory Addresss
A8 d
Low-Order
AD7
00H 3EH Opcode 01H 32H Data
AD0
Memory Address Memory Address
ALE
IO/M
Status IO/M = 0, S0 = 1, S1 = 1 Opcode Fetch IO/M = 0, S1 = 1, S0 = 0 Status
S1, S0
RD
DEMULTIPLEXING THE BUS AD7-AD0
A15 A15
A14
A13
A12
A11
8085
Microprocessor
A10
A9
A8
A8
ALE
A7
Enable
D FF A6
AD7 A5
A4
A3
A2
74LS373 A1
AD0 A0
D7
D6
D5
D4
D3
D2
D1
D0
Delay Subroutine
10
DELAY PROGRAM 1
No. of T states Total T states
MVI B,FFH 7 7
LOOP:DCR B 4 255X4
JNZ LOOP 10/7 254X10 +7