MPI

Sapna Arora
Assistant Professor
PIET(ECE)
1
Intel 8086 was launched
in 1978.
It was the first 16-bit
microprocessor.
This microprocessor had
major improvement over
the execution speed of
8085.
It is available as 40-pin
Dual-Inline-Package
(DIP).

3
It is available in three versions:

8086 (5 MHz)

8086-2 (8 MHz)

8086-1 (10 MHz)

It consists of
29,000 transistors.

4
It has a 16 line data
bus.
And 20 line address
bus.
It could address up to 1
MB of memory.

It has more than

20,000
instructions.
It supports
multiplication and 5

division.
6
These lines are multiplexed bi-
directional address/data bus.
During T1, they carry lower
order 16-bit address.

In the remaining clock cycles,

they carry 16-bit data.
AD0-AD7 carry lower order byte of
data.
AD8-AD15 carry higher order
byte of data.

7
 Time Multiplexing

When the same pin has different functions

during different time cycles,
that pin is said to be time multiplexed.

Aren’t all humans time multiplexed?

These lines are multiplexed
unidirectional address and
status bus.

During T1, they carry higher order

4-bit address.

In the remaining clock cycles,

they carry status signals.

9
 GND 1 40 Vcc
AD1 AD15
2 39
AD13 3 38 A16 / S3
AD1 4 37 A17 / S4
AD11 5 36 A18 / S5
AD1 6 35 A19 / S6
AD9 7 34 S3 S4 Segment
AD8 8 33
9 32 0 0 Extra
AD7
AD6 10 8086 31 0 1 Stack
11 30
AD5 1 0 Code
12 29
AD4 13 28 1 1 Data
AD3 14 27
AD2 S5 indicates interrupt
15 26
AD1 flag is set
16 25
AD 17 24 S6 is 0 when 8086 is
0
18 23 BM
CLK 19 22 READY
GND 20 21 RESET
7/17/2017
Active High/Active Low?

• Describes how a pin is activated.

• Active high pins are enabled when set to 1
• Active low pins are enabled when set to 0
• By default all pins are directly connected
to the Vcc.
• Active low pins are connected via NOT
gate
• If we do not want certain pins to be active
by default, we will reverse their role.
It is a read signal used for read
operation.

It is an output signal.

It is an active low signal.

12
This is an acknowledgement signal
from slower I/O devices or
memory.
It is an active high signal.
When high, it indicates that the
device is ready to transfer data.

When low,then microprocessor

is in wait state.

13
It is a system reset.
It is an active high signal.
When high, microprocessor enters
into reset state and terminates
the current activity.

It must be active for at least four

clock cycles to reset the
microprocessor.

14
 GND 1 40
Vcc
AD14 2 39
3 38 AD15
AD13 4 A0 A
A16 / S3
BHE
12 37 17 / S4
AD 5 Access 36
AD110 6 0 16-bit word (D15 – D0) A18 / S5
35
AD 0
10
71 34 𝐵A𝐻𝐸
9 Upper byte (D15 – D8) 19 / /
S6S
AD 1 8 0 Lower byte (D7 –33
7
AD8
AD7 1 9 D0)
1 32 BHE = 0
10Invalid 31 Enable data on D8 –
AD6
AD5 11 8086 30 D15

AD4 12 29
13 28 BHE
Enable
=data
1 on D –
AD3 0
14 27 D 7
AD2
AD1 15 26
16 25 S7 reserved for
AD0 future
17 24
NMI
18 23
INTR
CLK 19 22 READY
20 21
GND
7/17/2017
RESET
It is an interrupt request signal.

It is active high.

It is level triggered.

16
It is a non-maskable interrupt
signal.

It is an active high.

It is an edge triggered interrupt.

17
It is used to test the
status of math co-
processor 8087.

The BUSY pin of 8087 is

connected to this pin of
8086.

If low, execution continues else

microprocessor is in wait state.

18
This clock input provides the
basic timing for processor
operation.

The range of frequency of different

versions is 5 MHz, 8 MHz and 10
MHz.

19
VCC is power supply signal.

+5V DC is supplied
through this pin.

VSSis ground signal.

20
Modes of Operation

Processor needs control over the address, data and control

buses to access memory and I/O devices.

• Minimum mode – single processor mode

• Processor issues control signals

• Maximum mode – multi processor mode

• The bus controller issues control signals

These modes of operations are available only in 8086/88.

8086 works in two modes:
Minimum Mode

Maximum Mode

If MN/MX is high, it works

in minimum mode.
If MN/MX is low, it works
in maximum mode.

22
Pins 24 to 31 issue two
different sets of signals.

One set of signals is issued when

CPU operates in minimum mode.

Other set of signals is issued

when CPU operates in
maximum mode.

23
24
This is an interrupt
acknowledge signal.

When microprocessor
receives INTR signal, it
acknowledges the interrupt
by generating this signal.

It is an active low signal.

25
This is an Address Latch
Enable signal.
It indicates that valid address is
available on bus AD0 – AD15.

It is an active high signal and

remains high during T1 state.

It is connected to enable pin of

latch 8282.

26
This is a Data Enable
signal.
This signal is used to enable
the transceiver 8286.
Transceiver is used to separate the
data from the address/data bus.

It is an active low signal.

27
This is a Data Transmit/Receive
signal.

It decides the direction of data

flow through the transceiver.

When it is high, data is

transmitted out.

When it is low, data is

received in.

28
 1 STB (3)
ALE 8086
8086
8282 A0 – A19
AD0 – AD15
AD0 – AD15, Latch
A16/S3 – A19/S6 8-bit
A16/S3 – A19/S6, 𝑩𝑯𝑬/S7 𝑂𝐸
𝐵𝐻𝐸 / S7

AD0 – AD15
GND

(2)

8086
8286
Transrecieve
D0 – D15
T r Pure Data
8 𝑂𝐸 8-bit

086

DT/𝑅
𝐷𝐸𝑁
This signal is issued by the
microprocessor to distinguish
memory access from I/O access.

When it is high, memory is accessed.

When it is low, I/O devices are

accessed.

30
It is a Write signal.

It is used to write data in memory

or output device depending on
the status of M/IO signal.
It is an active low signal.

31
It is a Hold Acknowledge signal.

It is issued after receiving the

HOLD signal.

It is an active high signal.

32
When DMA controller needs to use
address/data bus, it sends a
request to the CPU through this
pin.

It is an active high signal.

When microprocessor receives

HOLD signal, it issues HLDA
signal to the DMA controller.

33
34
These pins provide the
status of instruction queue.

35
These status signals indicate
the operation being done
by the microprocessor.

This information is
required by the Bus
Controller 8288.

Bus controller 8288 generates all

memory and I/O control signals.

37
S2 S1 S0 Status
0 0 0 Interrupt Acknowledge
0 0 1 I/O Read
0 1 0 I/O Write
0 1 1 Halt
1 0 0 Opcode Fetch
1 0 1 Memory Read
1 1 0 Memory Write
1 1 1 Passive

38
This signal indicates that other
processors should not ask CPU
to relinquish the system bus.
When it goes low, all interrupts are
masked and HOLD request is not
granted.
This pin is activated by using
LOCK prefix on any instruction.

39
These are Request/Grant
pins.

Other processors request the CPU

through these lines to release
the system bus.

After receiving the request,

CPU sends acknowledge
signal on the same lines.

RQ/GT0 has higher priority

than RQ/GT1.

40
The READY input causes wait states for slower memory
& I/O components.

A wait state(Tw) is an extra clocking period, inserted

between T2 & T3, that lengthens the bus cycle.

If one wait state in inserted, then the memory access

time, normally 460 ns with a 5 MHz clock, is
lengthened by one clocking period (200ns) to 660 ns.