EC-3003 :: MICROPROCESSORS AND MICROCONTROLLERS

(Credit - 4)

Solved Question Paper

2014 Midsem

Jabir Hussain
([email protected])
School of Electronics Engineering
KIIT University

August 14, 2018

Part One

1 (a). POP B
Opcode Fetch M/C with 4 T-states, Memory Read M/C and Memory Read M/C.

1 (b). Content of the accumulator is 32H

After the execution of CMP A instruction the contents of the accumulator will be 32H and
status of Z-flag will be 1.
After the execution of XRA A instruction the contents of the accumulator will be 00H and
status of Z-flag will be 1.

1 (c). 8085 requires 10 T-states to execute the MVI M,25H instruction. According to
the question, crystal frequency, fX is 4MHz.

fX = 4MHz
fX
fµP =
2
∴ Clock frequncy, fµp = 2 MHz
1
Now, 1T-state = = 0.5 µs
fµp
Time taken to execute the instruction is 10 × 0.5 µs = 5 µs

1 (d). i) STA 3050H is used in Memory-mapped I/O mapping scheme.

ii) RST 2 : 2 × 8 = 16D = 10H . Therefore, vector address is 0010H.

1 (e).

SID I7.5 I6.5 I5.5 IE M7.5 M6.5 M5.5

0 0 0 1 1 0 0 1

• RST 5.5 is pending.

• Interrupt Enable flip-flop is set.
• RST 5.5 is masked.
• RST 7.5 and RST 6.5 are not pending and are enabled.

1
Part Two

2 (a). See notes (Unit 2, Sections 2.2 and 2.4)

2 (b).

S Z x AC x P x C

1 0 0 1 0 1 0 0

S = 1 : Sum is a negative number.

Z = 0 : Sum is not equal to zero.
AC = 1 : There was a carry from D3 bit to D4 bit.
P = 1 : Sum has even number of 1s.
C = 0 : Sum did not produced any carry.

2 (c). See notes (Unit 2)

2 (d). Stack operation: The stack can be described as a set of memory locations which
are used to temporarily store information during the execution of a program. In 8085,
the instructions PUSH and POP are used to perform stack related operations. The stack
pointer register tracks the storage and retrieval of the information. Because two data
bytes are being stored at a time, the 16-bit memory address in the stack pointer register
is decremented by two; when data bytes are retrieved, the address is incremented by two.

See notes (Unit 4, Section 2.3)

2
Part Three

3 (a). i) SHLD 4000H : Store H and L Registers Direct – Direct Addressing Mode.
Contents of L reg. is stored in 4000H and contents of H reg. is stored in 4001H
ii) RAL : Rotate Accumulator left through Carry – Implicit Addressing Mode.

Cy

A7 A6 A5 A4 A3 A2 A1 A0

An+1 ← An
Cy ← A7
A 0 ← Cy

3 (b). See notes (Unit 1, Section 2)

3 (c). EI SOD SDE x R7.5 MSE M7.5 M6.5 M5.5

MVI A,1CH 0 0 0 1 1 1 0 0

SIM

3
 Timing Diagram of LDAX D instruction

M1 : Opcode Fetch M/C M2 : Memory Read M/C

T1 T2 T3 T4 T1 T2 T3

CLK

Higher Order Memory Address Higher Order Memory Address

A15 –A8 Contents of D reg.
F0H Unspecified F1H

Lower Order Opcode Lower Order Data from Memory

Data in memory
AD7 –AD0 Contents of E reg.
address F150H
00H 1AH 50H 56H
Memory Address Memory Address

4
ALE
register pair is F150H and contents of accumulator is 56H

IO/M, S1 , S0
IO/M = 0, S1 = 1, S0 = 1 IO/M = 0, S1 = 1, S0 = 0

RD bc bc

bc bc

WR
3 (d). Timing diagram of LDAX D is shown below. It is assumed that the content of DE
Part Four

4 (a). Comparison of Memory-mapped I/O and I/O-mapped I/O.

Characteristics Memory-mapped I/O I/O-mapped I/O

1. Device Address 16-bit 8-bit

2. Control signals for MEMR/MEMW IOR/IOW

Input/Output

3. Instructions available Memory-related instructions IN and OUT

such as STA, LDA, etc.

4. Data transfer Between any register and I/O Only between I/O and the
accumulator

5. Maximum number of The memory map (64K) is The I/O map is

I/Os possible shared between I/Os and system independent of the memory
memory map; 256 input devices and
256 output devices can be
connected

6. Execution speed 13 T-states (STA, LDA) 10 T-states.

7 T-states (MOV M,R)

7. Hardware More hardware is needed to Less hardware is needed to

requirements decode 16-bit address decode 8-bit address

8. Other features Arithmetic or logical operations Not available

can be directly performed with
I/O data

4 (b). See notes (Unit 3, Section 5.1 and 5.2)

4 (c). ORG 0F200H

MVI C,10H; Initializing count with 10H ≡ 16D
LXI H,0F500H; According to the question data is stored from address XX00H
MOV A,M
DCR C

5
 LOOP: INX H
CMP M
JNC AHEAD
MOV A,M
AHEAD: DCR C
JNZ LOOP
STA 0F520H; According to the question, result is stored at XX20H
RST 1
ORG 0F500H; Define 16 bytes of Data
DB 62H,55H,98H,47H,98H,27H,32H,26H
DB 23H,42H,68H,82H,32H,12H,52H,61H
END

4 (d). RST 3 : DF → 1 1 0 1 1 1 1 1
+5V
In response to
the Interrupt
Tri-state Buffer Request (INTR),
1
b
DI7 8085 sends the

1
INTA (Interrupt
b
DI6
b
Acknowledge)
0
DI5 low signal. This
b

1
is used to enable
b
DI4
b
the buffer and
DFH To Data Bus
1
b
DI3 the corresponding
b

RST instruction
1
b
DI2
b
is placed on the
1
b
DI1 data bus.
b

1
DI0
b

bc
ENABLE

← INTA from microprocessor