[LINEAR INTEGRATED

CIRCUITS]
[TIMMER ICS AND PLL]

MARCH 26, 2019

MODULE 3
ELECTRONICS S4
 Module III

TIMER IC 555

FEATURES OF IC 555
 Highly temperature insensitive
 Output is compatible with TTL,CMOS and DTL logics
 Can source or sink current up to 200mA
 Monostable and Astable modes are possible with timing span of a few microseconds to
hours
 Wide range of supply voltage.
 Built in compensation for component tolerances and temperature drifts

APPLICATIONS OF IC555
*Frequency divider

*Pulse Generator

*Square wave generator

*Temperature controller

*Pulse detector

*Photo timers

*Pulsewidth modulation

1
FUNCTIONAL BLOCK DIAGRAM OF 555

The functional block diagram of IC 555 is shown in figure.It consists of Two

comparators,one SR flipflop,a discharge transisitor ,a reset transistor ,an inverter buffer
and three 5kohm resistors.Here the three equal value resistors of 5K serves as internal
voltage divider for the VCC.It produces a reference voltage of 2/3VCC and 1/3VCC for
upper comparator and lower comparator respectively.The output of the comparators are
connected to the input terminals of the RS flipflop.The flip flop changes its output
according to the input states.If the voltage at the positive terminal of the upper
comparator goes above the threshold voltage(2/3VCC) ,output of the upper comparator
becomes high and hence rest the flip flop.(Q=0).On the otherhand,if the trigger voltage
(voltage at the inverting input of the lower comparator)goes below 1/3VCC,the output of
the lower comparator becomes high ,and the output of the flipflop is set to one(Q=1).

The output Ō of the flip flop is used to drive the discharge transistor and output
stage. When Ō is high (Ō=1)the discharge transistor becomes ON and become conductive
it offers a short circuit to ground.The output stage produces an inverted output at the
output pin of IC 555.When Ō is low(Ō=0) the reverse action takesplace and a high output
is produced at output pin of IC 555.The reset transistor is used to reset the output of the
IC.when a low signal is applied to the base of the reset transistor the output of the IC will
be reset.and the output of the flipflop has no effect on the ouput.normally the reset pin
is connected to the VCC.

2
 PIN DIAGRM OF IC 555

ASTABLE MULTIVIBRATOR USING 555

Operation

The following schematic depicts the internal circuit of the IC 555 operating in astable mode. The
RC timing circuit incorporates R1, R2 and C.

3
Initially, on power-up, the flip-flop is RESET (and hence the output of the timer is low). As a
result, the discharge transistor is driven to saturation (as it is connected to Q’). The capacitor C
of the timing circuit is connected at Pin 7 of the IC 555 and will discharge through the transistor.
The output of the timer at this point is low. The voltage across the capacitor is nothing but the
trigger voltage. So while discharging, if the capacitor voltage becomes less than 1/3 VCC, which
is the reference voltage to trigger comparator (comparator 2), the output of the comparator 2 will
become high. This will SET the flip-flop and hence the output of the timer at pin 3 goes to
HIGH.

This high output will turn OFF the transistor. As a result, the capacitor C starts charging through
the resistors R1 and R2. Now, the capacitor voltage is same as the threshold voltage (as pin 6 is
connected to the capacitor resistor junction). While charging, the capacitor voltage increases
exponentially towards VCC and the moment it crosses 2/3 VCC, which is the reference voltage
to threshold comparator (comparator 1), its output becomes high.

As a result, the flip-flop is RESET. The output of the timer falls to LOW. This low output will
once again turn on the transistor which provides a discharge path to the capacitor. Hence the
capacitor C will discharge through the resistor R2. And hence the cycle continues.

Thus, when the capacitor is charging, the voltage across the capacitor rises exponentially and the
output voltage at pin 3 is high. Similarly, when the capacitor is discharging, the voltage across
the capacitor falls exponentially and the output voltage at pin 3 is low. The shape of the output
waveform is a train of rectangular pulses. The waveforms of capacitor voltage and the output in
the astable mode are shown below.

4
While charging, the capacitor charges through the resistors R1 and R2. Therefore the charging
time constant is (R1 + R2) C as the total resistance in the charging path is R1 + R2. While
discharging, the capacitor discharges through the resistor R2 only. Hence the discharge time
constant is R2C.

Ton=0.693(R1+R2)C

Toff=0.693(R2)C

Total time period T=0.693(R1+2R2)C

Frequency = 1/T = 1.44(R1+2R2)C

5
 MONOSTABLE MULTIVIBRATOR USING IC 555

vcc

Initially, when the output at pin 3 is low i.e. the circuit is in a stable state, the transistor is on and
capacitor- C is shorted to ground. When a negative pulse is applied to pin 2, the trigger input
falls below +1/3 VCC, the output of comparator goes high which resets the flip-flop and
consequently the transistor turns off and the output at pin 3 goes high. This is the transition of the
output from stable to quasi-stable state, as shown in figure. As the discharge transistor is cutoff,
the capacitor C begins charging toward +VCC through resistance RA with a time constant equal to
RAC. When the increasing capacitor voltage becomes slightly greater than +2/3 VCC, the output
of comparator 1 goes high, which sets the flip-flop. The transistor goes to saturation, thereby
discharging the capacitor C and the output of the timer goes low, as illustrated in figure.Thus the
output returns back to stable state from quasi-stable state.The output of the Monostable
Multivibrator remains low until a trigger pulse is again applied. Then the cycle repeats. Trigger
input, output voltage and capacitor voltage waveforms are shown in figure.

Time period Tp==1.1RC

6
It is the time period for which the monostable multivibrator stay at quasistable state

LM 380 Audio Power Amplifier

LM 380 is a low power audio amplifier designed to deliver a minimum of 2.5W to 8 ohm
load.The features of th IC are

1.It requires minimum external components

2.Internally fixed gain of 50(34 dB)
3.Ouput automatically centered to one half of the supply voltage
4.Output short circuit protection
5.Internal thermal limiting
6.Wide supplyvoltage range(5 to 22V)
7.High peak current capacity
8.High impedance

7
 The figure shows the simplest and most basic application of LM 380 as an audio
amplifier. As shown in the figure ,the amplifier requires very few external components because
of the internal biasing,compensation,and the fixed gain.When the power amplifier is used in the
non inverting mode ,the inverting terminal may be either connected to ground ,conected to
ground through a resister or capacitor,or left open as shown.similarly when the amplifier is used
in inverting mode the non inverting terminal is either connected to ground or kept open.A
decoupling capacitor is connected at the supply voltage pin.An RC series combinationshoud be
used at the output terminal to eliminate unnecessary oscillations.Here the amplifier is opertaed
with fixed internal gain of 50.it can be changed with the use of external components .

PHASE LOCKED LOOP (PLL)

The PLL is an important building block of linear systems.It is main technique used for
electronic frequency control in modern communication systems.

Block Digram of PLL

PLL is a feedback system as shown below.It consists of

1.Phase detector/comparator
2.A low pass filter
3.An error amplifier
4.A voltage controlled oscillator(VCO)

8
 The VCO is a free running oscillator and operates at a set frequency fo
called free running frequency.This frequency is determined by an external timing resistor and
capacitor.It can be increased or decreased by a DC control voltage at the input of the VCO.The
frequency change at the output is directly propotional to the DC control voltage and hence it is
called voltage controlled oscillator.(VCO)
If an iput volatage Vs of frequency fs is applied to the PLL,the phase detector compares
the phase and frequency of the incomming signal with the VCO output.If the two signals differ in
frequency and/or phase ,an error voltage is generated.The phase detector is basically a mixer and
produces the sum(fs+fo) and difference (fs-fo) components at its output.The high frequency
component is removed by low pass filter and the difference frequency component is amplified
and then applied as control voltage Vc to VCO.The signal Vc chsnges the VCO frequency in
adirection to reduce the frequency difference between fs and fo. Once this action starts ,we can
say the PLL is in capture range.The VCO continues to change the frequency till its output
frequency is exactly equal to the input signal frequency.The circuit is then said to be locked.Once
locked the output frequency of VCO is identical to fs.or fo follows th fs.Once locked ,PLL tracks
the frequency changes of the input signal.Thus PLL goes through three stages.(i).Free running
(ii). Capture (iii). Locked or tracking

capture range

The range of input frequencies over which PLL will capture the input signal is referred asPLL
capture range. As shown in the fig-2, it is much narrower compare to the PLL lock range

Lock range
The range of frequencies over which PLL will track the input frequency signal and remains
locked is referred as PLL Lock range. The lock range is usually band of frequencies above and below
the PLL free running frequency

9
 Pull-in time:

The total time taken by the PLL to establish lock is called pull-in time.It is the time taken by the
PLL to change its state from freerunning mode to lock mode.

Block Diagram of NE 566 Voltage Controlled oscillator

10
 The above figure shows the internal block diagram of VCO IC 566.It consist of a constant
current source/sink,a buffer amplifier,a schmitt trigger and an inverter power amplifier.An external
timing capacitor and resistor is required for the opertaion VCO as shown in the figure.

Here a the timing capacitor is linearly charged and discharged by a constant current source.The
amount of current can be controlled by changing the voltage Vc applied at the modulating input.The
voltage at pin number 6 is held at the same voltage as pin 5.Thus ,if the modulating voltage at pin 5 is
increased ,the voltage at pin 6 is also increased,resulting in less voltage acrossRt and thereby decreasing
the charging current.

WORKING

The voltage across the capacitor is applied to the inverting input of a schmitt trigger via buffer
amplifier.The output voltage of the Schmitt trigger is designed to change from 0.5VCC to VCC.Since
the resistors Ra=Rb in the positive feedback loop of schmitt trigger the non inverting input voltage of
schmitt trigger changes between 0.5VCC and 0.25 VCC.
When the voltage across the capacitor Ct exceeds 0.5VCC during charging the output of the
schmitt trigger goes low(0.5VCC). Then the output of the VCO will be high(VCC) because of the ouput
power amplifier is an inverter type. Now the capacitor discharges and when it goes below the 0.25VCC
the output of the schmitt trigger goes high(VCC).and the ouput becomes Low(0.5 VCC).Since the source
and sink currents are equal,capacitor charges and discharges the same amount of time.This gives a
triangular waveforms across Ct and at the pin 4.
When we apply a control voltage at pin 5 ,the charging current and discharging current will
changed thereby changing the time period of the output siganl.Thus the frequency of the output signal
can be varied by externally applied control voltage.so the circuit is called Voltage Controlled Oscillator
or VCO

WAVEFORM

11
The important electrical characteristics of the 565 PLL
* Operating frequency range: 0.001Hz to 500 Khz.
* Operating voltage range: ±6 to ±12v
·* Input level required for tracking: 10mv rms min to 3 Vpp max
* Input impedance: 10 K ohms typically.
* Output sink current: 1Ma
* Output source current: 10 mA
* Triangle wave amplitude :Typically 2.4V pp at+-6V
* Square wave amplitude Typically 5.4 Vpp at +-6V
* Drift in VCO centre frequency with temperature: 300 ppm/ °C typically.
* Drift in VCO centre frequency with supply voltage: 1.5 %/V maximum.
* Input level required for tracking: 10 mVrms minimum to 3 V peak-to-peak maximum.
* Bandwidth adjustment range: < ± 1 to > ± 60 %.

FUNCTIONAL BLOCK DIAGRAM OF PLL IC NE565

12
The block diagram consist of a phase detector which acts as a phase comparator, an amplifier,
and a low pass filter with the combination of the resistor (3.6 kilo ohm) and capacitor C2. The
output of the amplifier is fed back to the VCO. The different pins representing that of the IC are
also shown in the block diagram. Pins 1 and 10 are the positive and negative supply pins. The
pins 2 and 3 are the input to the phase detector. The input signals are fed through these pins in
differential mode. Pin 4 is the VCO output and pin 5 is the phase comparator VCO input. If both
these pins are shorted the output of the VCO is supplied back to the phase comparator. The
output of the phase comparator is given to the amplifier. The amplifier has two outputs that goes
to the external pins as the demodulator output (pin 7) and the reference output (pin 6). An LPF
circuit is formed by connecting the capacitor C2 between pin 7 and 10 with a resistor of value
3.6 kilo ohms. The value of C2 must be large enough to eliminate the variations in demodulated
output and stabilize the VCO frequency.

Pins 8 and 9 are used to connect the external resistor (R1) and external capacitor (C1). The
values of R1 and C1 help to adjust the free running frequency (fr) of the PLL. Though the value
of C1 can be anything, the value of resistor R1 must have a value between 2 to 20 kilo ohms. All
these factors can be used to determine the center frequency of the PLL.

The free running frequency of the PLL is given as fr = (1.2)/(4R1C1) Hertz

PLL as frequency multiplier

In this application, the loop is broken and a frequency divider network is inserted between VCO
and phase detector as shown in figure above.Since the output of frequency divider is locked to
input frequency fin, the VCO is actually running at a multiple of the input frequency. The desired
amount of multiplication can be obtained by selecting a proper ÷N network.

Input to the phase detector

fin=fo/N

fo=Nfin

That is the output of the VCO is the N multiple of input frequency. Eg: If N=10 ; the fo will be
10 times the input frequency.

13
FM demodulator

When the PLL is in lock range the output of the VCO follows the input
frequency.So if apply an FM signal to the PLL the VCO frequency will try to
capture the FM signal.And if select the free running frequency of VCO as the
centre frequency of FM ,The frequency of the error voltage obtained at the output
of the Low pass filter will be the modulating signal.So if we apply the FM signal to
a locked PLL. the output from the amplifier stage will be the original modulating
signal.

14