CMOS 8-Bit Single Chip Microcomputer
CMOS 8-Bit Single Chip Microcomputer
CMOS 8-Bit Single Chip Microcomputer
Description
The CXP86541/86549/86561 are the CMOS 8-bit 52 pin SDIP (Plastic)
microcomputer integrating on a single chip an A/D
converter, serial interface, timer/counter, time-base
timer, on-screen display function, I2C bus interface,
PWM output, remote control reception circuit,
HSYNC counter, watchdog timer, 32kHz timer/counter
besides the basic configurations of 8-bit CPU, ROM,
RAM, I/O ports.
The CXP86541/86549/86561 also provide a sleep
function that enables to lower the power consumption.
Features Structure
• A wide instruction set (213 instructions) which Silicon gate CMOS IC
covers various types of data
– 16-bit operation/multiplication and division/
Boolean bit operation instructions
• Minimum instruction cycle 250ns at 16MHz operation (4.5 to 5.5V)
122µs at 32kHz operation (2.7 to 5.5V)
• Incorporated ROM 40K bytes (CXP86541)
48K bytes (CXP86549)
60K bytes (CXP86561)
• Incorporated RAM 1536 bytes
(Excludes VRAM for on-screen display and sprite RAM)
• Peripheral functions
– A/D converter 8-bit 6-channel successive approximation method
(Conversion time of 3.25µs at 16 MHz)
– Serial interface 8-bit clock sync type, 1 channel
– Timer 8-bit timer
8-bit timer/counter
19-bit time-base timer
32kHz timer/counter
– On-screen display (OSD) function 12 × 16 dots,
512 character types,
15 character colors, 2 lines × 24 characters,
frame background 8 colors/ half blanking,
background on full screen 15 colors/ half blanking
edging/ shadowing/ rounding for every line,
background with shadow for every character,
double scanning,
sprite OSD,
12 × 16 dots, 1 screen, 8 colors for every dot
– I2C bus interface
– PWM output 8 bits, 6 channels
14 bits, 1 channel
– Remote control reception circuit 8-bit pulse measurement counter, 6-stage FIFO
– HSYNC counter 2 channels
– Watchdog timer
• Interruption 13 factors, 13 vectors, multi-interruption possible
• Standby mode Sleep
• Package 52-pin plastic SDIP
• Piggyback/evaluator CXP86490 64-pin ceramic PSDIP (Supports custom font)
Perchase of Sony's I2C components conveys a licence under the Philips I2C Patent Rights to use these components
in an I2C system, provided that the system conforms to the I2C Standard Specifications as defined by Philips.
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E96Z15B1X-PS
Block Diagram
INT2
MP
EXTAL
INT1
VSS
RST
TX
INT0
VDD
XTAL
TEX
CLOCK GENERATOR
A/D CONVERTER SPC700 CPU CORE
AN0 to AN5 6 /SYSTEM CONTROL 8 PA0 to PA7
6CH
PORT A
RMC REMOCON FIFO ROM
RAM
12K/16K/24K/32K/
352/704/1536 BYTES 8 PB0 to PB7
40K/48K/60K BYTES
PORT B
SI
SERIAL INTERFACE
SO
INTERRUPT CONTROLLER
UNIT
SCK
TO 8BIT TIMER 1
–2–
PORT E
3 PE4 to PE6
G
B ON SCREEN
I DISPLAY WATCHDOG TIMER
YS 8 PF0 to PF7
PORT F
YM
32kHz
HSYNC
TIMER/COUNTER
VSYNC
1 PG7
HS0 HSYNC COUNTER 0
PORT G
2
I2C BUS
8BIT PWM 14BIT PWM
HS1 HSYNC COUNTER 1 INTERFACE UNIT
6
ADJ
PWM
SCL0
SCL1
SDA0
SDA1
PWM0 to PWM5
CXP86541/86549/86561
CXP86541/86549/86561
EC/PD7 1 52 PF0/PWM0
RMC/PD6 2 51 PF1/PWM1
HS1/PD5 3 50 PF2/PWM2
HS0/PD4 4 49 PF3/PWM3
SI/PD3 5 48 PF4/SCL0
SO/PD2 6 47 PF5/SCL1/PWM4
SCK/PD1 7 46 PF6/SDA0
INT2/PD0 8 45 PF7/SDA1/PWM5
HSYNC/PA7 9 44 PE0/TO/ADJ
VSYNC/PA6 10 43 PE1/PWM
RST 11 42 PE2/TEX/INT0
VSS 12 41 PE3/TX
XTAL 13 40 VSS
EXTAL 14 39 VDD
PA5/AN5 15 38 NC
PA4/AN4 16 37 EXLC
PA3/AN3 17 36 XLC
PA2/AN2 18 35 PE4/YM
PA1/AN1 19 34 PE5/YS
PA0/AN0 20 33 PE6/I
PB7 21 32 B
PB6 22 31 G
PB5 23 30 R
PB4 24 29 PB0
PB3 25 28 PB1
INT1/PG7 26 27 PB2
Note)
1. NC (Pin 38) is left open.
2. Vss (Pins 12 and 40) are both connected to GND.
–3–
CXP86541/86549/86561
Pin Description
PE5/YS Output/Output
PE6/I Output/Output OSD display 6-bit output.
B Output (6 pins)
G Output
R Output
–4–
CXP86541/86549/86561
NC No connected.
VDD Positive power supply.
Vss GND. Connect two Vss pins to GND.
–5–
CXP86541/86549/86561
Port A data
Port A direction
6 pins
Port A
Port A data
Port A direction
PA6/VSYNC “0” when reset
PA7/HSYNC
Data bus Schmitt input Hi-Z
IP
RD (Port A)
Port B
Ports B, G data
Port G
Ports B, G direction
PB0 to PB7 “0” when reset
PG7/INT1
Schmitt input Hi-Z
Data bus for PB0, PB1, PB2, IP
PG7
RD (Ports B, G)
9 pins INT1
Port F
PWM0 to PWM3
PF0/PWM0
to
Port F function selection
PF3/PWM3 Hi-Z
“0” when reset ∗
Port F data
“1” when reset ∗ 12V drive voltage
Large current 12mA
4 pins
–6–
CXP86541/86549/86561
Port D
SCK, SO
SIO output enable
Port D data
PD1/SCK
PD2/SO ∗
Port D direction Hi-Z
“0” when reset
IP
Schmitt input
Data bus only for PD1
RD (Port D)
Port E
Internal reset signal
Port E data 00
“1” when reset
TO 01 MPX
ADJ16K∗1 10 ∗2
ADJ2K∗1 11 High level
PE0/TO/ADJ (with
Port E function selection (Upper) approximately
Port E function selection (Lower) 150kΩ
∗1 ADJ signals are frequency resistor when
“00” when reset
dividing outputs for 32kHz reset)
Port E direction oscillation frequency IP
“1” when reset adjustment. ADJ2K provides
usage as buzzer output.
Data bus ∗2 Pull-up resistors approx. 150kΩ
1 pin RD (Port E)
–7–
CXP86541/86549/86561
RD (Port E)
1 pin
Port E
32kHz oscillation circuit control
“1” when reset
Schmitt input
INT0
Data bus
RD (Port E)
PE2/TEX/INT0
Data bus Oscillation
PE3/TX
halted
RD (Port E)
PE2/ Schmitt input Port input
TEX/ IP IP
INT0 Clock input
PE3/
2 pins TX
Port E
YM, YS, I
Output polarity
PE4/YM “0” when reset
PE5/YS
PE6/I Port E function selection Hi-Z
“0” when reset
Port E data
–8–
CXP86541/86549/86561
SCL, SDA IP
(I2C bus circuit)
BUS SW
4 pins ∗ Large current 12mA To internal I2C pins
(SCL1 for SCL0)
R, G, B
R Output polarity
G “0” when reset
B Hi-Z
Oscillation control
2 pins XLC
EXTAL EXTAL IP
XTAL • Diagram shows the
circuit composition Oscillation
during oscillation.
• Feedback resistor is
XTAL removed during stop mode.
2 pins (This device does not
enter stop mode.)
Pull-up resistor
RST
AA
OP Mask option Low level
Schmitt input
1 pin
AA
–9–
CXP86541/86549/86561
Electrical Characteristics
– 11 –
CXP86541/86549/86561
∗1 For RST pin, specifies the input current when pull-up resistance is selected, and specifies the leakage
current when non-resistor is selected.
∗2 When all output pins are left open. Specifies only when the OSD oscillation is halted.
∗3 This device does not enter the stop mode.
– 12 –
CXP86541/86549/86561
AC Characteristics
(1) Clock timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
Item Symbol Pins Conditions Min. Typ. Max Unit
XTAL
System clock frequency fC Fig. 1, Fig.2 8 16 MHz
EXTAL
tXL, Fig. 1, Fig.2
System clock input pulse width EXTAL 28 ns
tXH External clock drive
System clock input rise and fall tCR, Fig. 1, Fig.2
EXTAL 200 ns
times tCF External clock drive
Event count input clock pulse tEH, EC Fig. 3 4tsys∗1 ns
width tEL
Event count input clock rise tER, EC Fig. 3 20 ms
and fall times tEF
VDD = 2.7 to 5.5 V
TEX
System clock frequency fC Fig. 2 (32kHz clock 32.768 kHz
TX
applied conditions)
Event count input clock tTL, TEX Fig. 3 10 µs
pulse width tTH
Event count input clock rise tTR, TEX Fig. 3 ms
20
and fall times tTF
∗1 Indicates three values according to the contents of the clock control register (CLC: 00FEh) upper 2 bits
(CPU clock selection).
tsys (ns) = 2000/fc (Upper 2 bits = “00”), 4000/fc (Upper 2 bits = “01”), 16000/fc (Upper 2 bits = “11”)
VDD – 0.4V
EXTAL
0.4V
AAAAAAAAA AAAA
Crystal oscillation 32kHz clock applied condition
Ceramic oscillation External clock Crystal oscillation
AAAAAAAAA AAAA
C1
EXTAL XTAL
C2
EXTAL
74HC04
XTAL
C1
TEX TX
C2
TEX 0.8VDD
EC
0.2VDD
– 13 –
CXP86541/86549/86561
(2) Serial transfer (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
SCK High and Low level tKH SCK input mode 400 ns
SCK
widths tKL SCK output mode 4000/fc – 50 ns
Note) The load of SCK output mode and SO output delay time is 50pF + 1TTL.
tKCY
tKL tKH
0.8VDD
SCK
0.2VDD
tSIK tKSI
0.8VDD
SI Input data
0.2VDD
tKSO
0.8VDD
SO Output data
0.2VDD
– 14 –
CXP86541/86549/86561
(3) A/D converter (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
FFh
FEh
Digital conversion value
01h
00h
fADC = fc (CKS = “0”), fc/2 (CKS = “1”)
VZT VFT
Analog input
– 15 –
CXP86541/86549/86561
(4) Interruption, reset input (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
tIH tIL
INT0
INT1 0.8VDD
INT2
(falling edge) 0.2VDD
RST
0.2VDD
– 16 –
CXP86541/86549/86561
(5) I2C bus timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
SDA
tBUF
tR tF tHD; STA
SCL
tHD; STA
tSU; STA tSU; STO
P S tLOW tHD; DAT tHIGH tSU; DAT St P
RS RS RS R S RP RP
SDA0
(or SDA1)
SCL0
(or SCL1)
• A pull-up resistor (Rp) must be connected to SDA0 (or SDA1) and SCL0 (or SCL1).
• The SDA0 (or SDA1) and SCL0 (or SCL1) series resistance can be used to reduce the spike noise caused
by CRT flashover.
– 17 –
CXP86541/86549/86561
(6) OSD timing (Ta = –20 to +75°C, VDD = 4.5 to 5.5V, Vss = 0V reference)
EXLC
OSD clock frequency fOSC Fig. 11 4 28∗1 MHz
XLC
tHCG
tHWD
HSYNC 0.8VDD
For OSD I/O polarity register
(OPOL: 01FEh)
bit 7 at “0” 0.2VDD
tVCG
tVWD
VSYNC 0.8VDD
For OSD I/O polarity register
(OPOL: 01FEh)
bit 6 at “0” 0.2VDD
EXLC XLC
R∗1
L
C1 C2
∗1 The series resistor for XLC is used to reduce the frequency of occurrence of the undesired radiation.
– 18 –
CXP86541/86549/86561
Appendix
AAAA
AAAA
(i) Main clock
AAAA AAAAA
(ii) Main clock
AAAA AAAAA
(iii) Sub clock
AAAA
EXTAL XTAL
AAAA AAAAA
EXTAL XTAL TEX TX
AA
Rd Rd Rd
A
C1 C2 C1 C2
A
C1 C 2
Item Content
Reset pin pull-up resistor Non-existent Existent
– 19 –
CXP86541/86549/86561
Sleep mode
1
10
0.1
32kHz operation mode 5
0.01
Sleep mode
0
1 2 3 4 5 6 7 0 5 10 15
VDD – Supply voltage [mA] Frequency [MHz]
10
L – Inductance [µH]
16MHz
20MHz
1
24MHz
28MHz
30MHz
fOSC = 1 C = C1//C2
2π√ LC
0.1
0.01
0 10 20 30 40 50 60 70 80 90 100
C1, C2 – Capacitance [pF]
– 20 –
CXP86541/86549/86561
05
+ 0.1
0.25 – 0.
+ 0.4
47.0 – 0.1
52 27
13.5 – 0.1
+ 0.3
0˚ to 15˚
15.24
1 26
1.778
5.0 MIN
0.51 MIN
0.5 ± 0.1
2.8 MIN
+ 0.1
0.9 – 0.05
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN
SONY CODE SDIP-52P-01 LEAD TREATMENT SOLDER PLATING
+ 0.4
47.0 – 0.1
52 27
13.5 – 0.1
+ 0.3
0˚ to 15˚
15.24
1 26
1.778
5.0 MIN
0.51 MIN
0.5 ± 0.1
2.8 MIN
+ 0.1
0.9 – 0.05
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN
SONY CODE SDIP-52P-01 LEAD TREATMENT SOLDER PLATING
ITEM SPEC.
LEAD MATERIAL COPPER ALLOY
SOLDER COMPOSITION Sn-Bi Bi:1-4wt%
PLATING THICKNESS 5-18µm
– 21 – Sony Corporation