Atmega644Pa: 8-Bit Avr Microcontrollers

8-bit AVR Microcontrollers
ATmega644PA
DATASHEET SUMMARY
Introduction
®
The Atmel ATmega644PA is a low-power CMOS 8-bit microcontroller based
on the AVR® enhanced RISC architecture. By executing powerful
instructions in a single clock cycle, the ATmega644PA achieves throughputs
close to 1MIPS per MHz. This empowers system designer to optimize the
device for power consumption versus processing speed.
Feature
High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Family

• Advanced RISC Architecture
– 131 Powerful Instructions
– Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Throughput at 20MHz
– On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory Segments
– 64KBytes of In-System Self-Programmable Flash Program
Memory
– 2KBytes EEPROM
– 4KBytes Internal SRAM
– Write/Erase Cycles: 10,000 Flash/100,000 EEPROM
– Data Retention: 20 Years at 85°C/100 Years at 25°C(1)
– Optional Boot Code Section with Independent Lock Bits
• In-System Programming by On-chip Boot Program
• True Read-While-Write Operation
– Programming Lock for Software Security
• Atmel QTouch® Library Support
– Capacitive Touch Buttons, Sliders and Wheels
– QTouch and QMatrix acquisition
– Up to 64 Sense Channels
Atmel-42717A-ATmega644PA_Datasheet_Summary-05/2016
• JTAG (IEEE std. 1149.1 Compliant) Interface
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode
– Real Time Counter with Separate Oscillator
– Six PWM Channels
– 8-channel 10-bit ADC
• Differential Mode with Selectable Gain at 1×, 10× or 200×
– One Byte-oriented 2-wire Serial Interface (Philips I2C compatible)
– Two Programmable Serial USART
– One Master/Slave SPI Serial Interface
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated RC Oscillator
– External and Internal Interrupt Sources
– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby, and
Extended Standby
• I/O and Packages
– 32 Programmable I/O Lines
– 40-pin PDIP
– 44-lead TQFP
– 44-pad VQFN/QFN
• Operating Voltage:
– 1.8 - 5.5V
• Speed Grades
– 0 - 4MHz @ 1.8V - 5.5V
– 0 - 10MHz @ 2.7V - 5.5V
– 0 - 20MHz @ 4.5 - 5.5V
• Power Consumption at 1MHz, 1.8V, 25°C
– Active Mode: 0.4mA
– Power-down Mode: 0.1μA
– Power-save Mode: 0.6μA (Including 32kHz RTC)
Note:
1. Refer to Data Retention
Related Links
Data Retention on page 12
Atmel ATmega644PA [DATASHEET] 2

1. Description
The Atmel® ATmega644PA is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC
architecture. By executing powerful instructions in a single clock cycle, the ATmega644PA achieves
throughputs close to 1MIPS per MHz. This empowers system designer to optimize the device for power
consumption versus processing speed.
The Atmel AVR® core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers
to be accessed in a single instruction executed in one clock cycle. The resulting architecture is more code
efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.
The ATmega644PA provides the following features: 64Kbytes of In-System Programmable Flash with
Read-While-Write capabilities, 2Kbytes EEPROM, 4Kbytes SRAM, 32 general purpose I/O lines, 32
general purpose working registers, Real Time Counter (RTC), three flexible Timer/Counters with compare
modes and PWM, two serial programmable USARTs , one byte-oriented 2-wire Serial Interface (I2C), a 8-
channel 10-bit ADC with optional differential input stage with programmable gain, a programmable
Watchdog Timer with internal Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test
interface, also used for accessing the On-chip Debug system and programming and six software
selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters,
SPI port, and interrupt system to continue functioning. The Power-down mode saves the register contents
but freezes the Oscillator, disabling all other chip functions until the next interrupt or hardware reset. In
Power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base
while the rest of the device is sleeping. The ADC Noise Reduction mode stops the CPU and all I/O
modules except asynchronous timer and ADC to minimize switching noise during ADC conversions. In
Standby mode, the crystal/resonator oscillator is running while the rest of the device is sleeping. This
allows very fast start-up combined with low power consumption. In Extended Standby mode, both the
main oscillator and the asynchronous timer continue to run.
Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality
into AVR microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and
includes fully debounced reporting of touch keys and includes Adjacent Key Suppression® (AKS™)
technology for unambiguous detection of key events. The easy-to-use QTouch Suite toolchain allows you
to explore, develop and debug your own touch applications.
The device is manufactured using Atmel’s high density non-volatile memory technology. The On-chip ISP
Flash allows the program memory to be reprogrammed In-System through an SPI serial interface, by a
conventional nonvolatile memory programmer, or by an On-chip Boot program running on the AVR core.
The Boot program can use any interface to download the application program in the Application Flash
memory. Software in the Boot Flash section will continue to run while the Application Flash section is
updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System
Self-Programmable Flash on a monolithic chip, the Atmel ATmega644PA is a powerful microcontroller
that provides a highly flexible and cost effective solution to many embedded control applications.
The ATmega644PA is supported with a full suite of program and system development tools including: C
Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emulators, and Evaluation kits.

2. Configuration Summary
The table below compares the device series of feature and pin compatible devices, providing a seamless
migration path.
Table 2-1. Configuration Summary and Device Comparison
Features ATmega164PA ATmega324PA ATmega644PA ATmega1284P

Pin Count 40/44/49 40/44/49 40/44 40/44
Flash (Bytes) 16K 32K 64K 128K
SRAM (Bytes) 1K 2K 4K 16K
EEPROM (Bytes) 512 1K 2K 4K
General Purpose 32 32 32 32
I/O Lines
SPI 1 1 1 1
TWI (I2C) 1 1 1 1
USART 2 2 2 2
ADC 10-bit 15ksps 10-bit 15ksps 10-bit 15ksps 10-bit 15ksps
ADC Channels 8 8 8 8
Analog Comparator 1 1 1 1
8-bit Timer/ 2 2 2 2
Counters
16-bit Timer/ 1 1 1 2
Counters
PWM channels 6 6 6 8
Packages PDIP PDIP PDIP PDIP
TQFP TQFP TQFP TQFP
VQFN/QFN VQFN/QFN VQFN/QFN VQFNQFN
DRQFN DRQFN
VFBGA VFBGA

3. Ordering Information
Speed [MHz](3) Power Supply [V] Ordering Code(2) Package(1) Operational Range
20 1.8 - 5.5 Industrial
ATmega644PA-AU 44A
(-40°C to 85°C)
ATmega644PA-AUR(4) 44A
ATmega644PA-PU 40P6
ATmega644PA-MU 44M1
ATmega644PA-MUR(4) 44M1
20 1.8 - 5.5 Industrial

ATmega644PA-AN 44A
(-40°C to 105°C)
ATmega644PA-ANR(4) 44A
ATmega644PA-PN 40P6
ATmega644PA-MN 44M1
ATmega644PA-MNR(4) 44M1
Note:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for
detailed ordering information and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances
(RoHS directive). Also Halide free and fully Green.
3. Refer to Speed Grades for Speed vs. VCC
4. Tape & Reel.
Package Type
40P6 40-pin, 0.600” Wide, Plastic Dual Inline Package (PDIP)
44A 44-lead, Thin (1.0mm) Plastic Quad Flat Package (TQFP)
44M1 44-pad, 7 × 7 × 1.0mm body, lead pitch 0.50mm, Thermally Enhanced Plastic Very Thin Quad Flat No-
Lead (VQFN)

4. Block Diagram
Figure 4-1. Block Diagram
SRAM
TCK
TMS
TDI JTAG CPU
TDO OCD
Clock generation
PA[7:0]
TOSC1 I I/O PB[7:0]
32.768kHz
8MHz NVM N PORTS PC[7:0]
Calib RC PD[7:0]
XOSC programming FLASH /
TOSC2 128kHz int O
XTAL1 osc U
16MHz LP Power
T GPIOR[2:0]
XOSC External management
clock
XTAL2 and clock D EEPROM D T0
control A A TC 0 OC0A
T (8-bit)
T OC0B
A A
B B MISO
VCC EEPROMIF MOSI
Power U U SPI SCK
Supervision Watchdog S S SS
RESET Timer
POR/BOD & AIN0
RESET AIN1
AC ACO
GND Internal ADCMUX
ADC[7:0] Reference
AREF ADC
RxD0
PCINT[31:0]
INT[2:0] EXTINT USART 0 TxD0
XCK0
OC1A/B RxD1
TC 1
T1
(16-bit) USART 1 TxD1
ICP1 XCK1
OC2A TC 2 TWI SDA

OC2B (8-bit async) SCL

5. Pin Configurations
5.1. Pinout
5.1.1. PDIP
(PCINT8/XCK0/T0) (ADC0/PCINT0)
(PCINT9/CLKO/T1) (ADC1/PCINT1)
(PCINT10/INT2/AIN0) (ADC2/PCINT2)
(PCINT11/OC0A/AIN1) (ADC3/PCINT3)
(PCINT12/OC0B/ (ADC4/PCINT4)
(PCINT13/MOSI) (ADC5/PCINT5)
(PCINT14/MISO) (ADC6/PCINT6)
(PCINT15//SCK) (ADC7/PCINT7)
(TOSC2/PCINT23)
(TOSC1/PCINT22)
(PCINT24/RXD0) (TDI/PCINT21)
(PCINT25/TXD0) (TDO/PCINT20)
(PCINT26/RXD1/INT0) (TMS/PCINT19) Power
(PCINT27/TXD1/INT1) (TCK/PCINT18) Ground
Programming/debug
(PCINT28/XCK1/OC1B) (SDA/PCINT17) Digital
(PCINT29/OC1A) (SCL/PCINT16) Analog
Crystal/Osc
(PCINT30/OC2B/ICP) (OC2A/PCINT31)

5.1.2. TQFN and QFN
PB3 (AIN1/OC0A/PCINT11)
PB2 (AIN0/INT2/PCINT10)
PB4 (SS/OC0B/PCINT12)
PB1 (T1/CLKO/PCINT9)
PB0 (XCK0/T0/PCINT8)
Power
PA0 (ADC0/PCINT0)
PA1 (ADC1/PCINT1)
PA2 (ADC2/PCINT2)
PA3 (ADC3/PCINT3)
Ground
Programming/debug
Digital
Analog
GND
VCC
Crystal/Osc
44
43
42
41
40
39
38
37
36
35
34
(PCINT13/MOSI) PB5 1 33 PA4 (ADC4/PCINT4)
(PCINT14/MISO) PB6 2 32 PA5 (ADC5/PCINT5)
(PCINT15/SCK) PB7 3 31 PA6 (ADC6/PCINT6)
RESET 4 30 PA7 (ADC7/PCINT7)
VCC 5 29 AREF
GND 6 28 GND
XTAL2 7 27 AVCC
XTAL1 8 26 PC7 (TOSC2/PCINT23)
(PCINT24/RXD0) PD0 9 25 PC6 (TOSC1/PCINT22)
(PCINT25/TXD0) PD1 10 24 PC5 (TDI/PCINT21)
(PCINT26/RXD1/INT0) PD2 11 23 PC4 (TDO/PCINT20)
12
13
14
15
16
17
18
19
20
21
22(PCINT19/TMS) PC3
(PCINT27/TXD1/INT1) PD3
(PCINT28/XCK1/OC1B) PD4
(PCINT17/SDA) PC1
(PCINT18/TCK) PC2
(PCINT30/OC2B/ICP1) PD6
(PCINT29/OC1A) PD5
(PCINT31/OC2A) PD7
(PCINT16/SCL) PC0
GND
VCC
5.2. Pin Descriptions
5.2.1. VCC
Digital supply voltage.
5.2.2. GND
Ground.
5.2.3. Port A (PA[7:0])

This port serves as analog inputs to the Analog-to-digital Converter.

This is an 8-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for each bit.
The output buffers have symmetrical drive characteristics, with both high sink and source capability. As
inputs, the port pins that are externally pulled low will source current if pull-up resistors are activated. Port
pins are tri-stated when a reset condition becomes active, even if the clock is not running.
5.2.4. Port B (PB[7:0])

This port also serves the functions of various special features.
5.2.5. Port C (PC[7:0])

This port also serves the functions of the JTAG interface, along with special features.
5.2.6. Port D (PD[7:0])

This port also serves the functions of various special features.
5.2.7. RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a reset, even if
the clock is not running. Shorter pulses are not guaranteed to generate a reset.
5.2.8. XTAL1
Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.
5.2.9. XTAL2
Output from the inverting Oscillator amplifier.
5.2.10. AVCC
AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be externally
connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected to VCC through
a low-pass filter.
5.2.11. AREF
This is the analog reference pin for the Analog-to-digital Converter.

6. I/O Multiplexing
Each pin is by default controlled by the PORT as a general purpose I/O and alternatively it can be
assigned to one of the peripheral functions.
The following table describes the peripheral signals multiplexed to the PORT I/O pins.
Table 6-1. PORT Function Multiplexing
32-pin 40-pin DRQFN VFBGA PAD EXTINT PCINT ADC/AC OSC T/C # 0 T/C # 1 USART I2C SPI JTAG
TQFP/ PIPD Pin# Pin#
QFN/ Pin #
MLF Pin
#
1 6 A1 B2 PB[5] PCINT1 MOSI

3
2 7 B1 B1 PB[6] PCINT1 MISO

4
3 8 A2 C3 PB[7] PCINT1 SCK

5
4 9 B2 C2 RESET
5 10 A3 A5 VCC
6 11 B3 A1 GND
7 12 A4 D2 XTAL2
8 13 B4 E1 XTAL1
9 14 A5 D3 PD[0] PCINT2 RxD0

4
10 15 B5 E2 PD[1] PCINT2 TxD0

5
11 16 A6 F1 PD[2] INT0 PCINT2 RxD1

6
12 17 A7 F2 PD[3] INT1 PCINT2 TXD1

7
13 18 B6 G2 PD[4] PCINT2 OC1B XCK1

8
14 19 A8 E3 PD[5] PCINT2 OC1A

9
15 20 B7 F3 PD[6] PCINT3 OC2B ICP1

0
16 21 A9 E4 PD[7] PCINT3 OC2A

1
17 - B8 C1 VCC RxD2 MISO1
18 - A10 A4 GND TxD2 MOSI1
19 22 B9 F4 PC[0] PCINT1 SCL

6
20 23 A11 G5 PC[1] PCINT1 SDA

7
21 24 B10 F5 PC[2] PCINT1 TCK

8
22 25 A12 G6 PC[3] PCINT1 TMS

9
23 26 A13 F6 PC[4] PCINT2 TDO

0

32-pin 40-pin DRQFN VFBGA PAD EXTINT PCINT ADC/AC OSC T/C # 0 T/C # 1 USART I2C SPI JTAG
TQFP/ PIPD Pin# Pin#
QFN/ Pin #
MLF Pin
#
24 27 B11 E5 PC[5] PCINT2 TDI

1
25 28 A14 F7 PC[6] PCINT2 TOSC1

2
26 29 B12 E6 PC[7] PCINT2 TOSC2

3
27 30 A15 E7 AVCC
28 31 B13 D1 GND
29 32 A16 C7 AREF AREF
30 33 B14 D6 PA[7] PCINT7 ADC7
31 34 A17 C6 PA[6] PCINT6 ADC6
32 35 B15 B7 PA[5] PCINT5 ADC5
33 36 A18 D5 PA[4] PCINT4 ADC4
34 37 A19 B6 PA[3] PCINT3 ADC3
35 38 B16 A6 PA[2] PCINT2 ADC2
36 39 A20 C5 PA[1] PCINT1 ADC1
37 40 B17 B5 PA[0] PCINT0 ADC0
38 - A21 G3 VCC SDA1
39 - B18 A7 GND SCL1
40 1 A22 B4 PB[0] PCINT8 T0 XCK0
41 2 B19 C4 PB[1] PCINT9 CLKO T1
42 3 A23 A3 PB[2] INT2 PCINT1 AIN0

0
43 4 B20 B3 PB[3] PCINT1 AIN1 OC0A

1
44 5 A24 A2 PB[4] PCINT1 OC0B SS

2
- - - D4 GND
- - - D7 GND
- - - G1 GND
- - - G4 GND
- - - G7 GND

7. General Information
7.1. Resources
A comprehensive set of development tools, application notes, and datasheets are available for download
on http://www.atmel.com/avr.
7.2. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM
over 20 years at 85°C or 100 years at 25°C.
7.3. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of the
device. These code examples assume that the part specific header file is included before compilation. Be
aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in C
is compiler dependent. Confirm with the C compiler documentation for more details.
For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions
must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS”
combined with “SBRS”, “SBRC”, “SBR”, and “CBR”.
7.4. Capacitive Touch Sensing
7.4.1. QTouch Library

® ®
The Atmel QTouch Library provides a simple to use solution to realize touch sensitive interfaces on
®
most Atmel AVR microcontrollers. The QTouch Library includes support for the Atmel QTouch and Atmel
®
QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library for the
AVR Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors,
and then calling the touch sensing API’s to retrieve the channel information and determine the touch
sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location: http://
www.atmel.com/technologies/touch/. For implementation details and other information, refer to the Atmel
QTouch Library User Guide - also available for download from the Atmel website.

8. Packaging Information
8.1. 40-pin PDIP
D
PIN
1
E1
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
0º ~ 15º REF (Unit of Measure = mm)
C
SYMBOL MIN NOM MAX NOTE
eB A – – 4.826
A1 0.381 – –
D 52.070 – 52.578 Note 2
E 15.240 – 15.875
E1 13.462 – 13.970 Note 2
B 0.356 – 0.559
B1 1.041 – 1.651
Notes: L 3.048 – 3.556
1. This package conforms to JEDEC reference MS-011, Variation AC. C 0.203 – 0.381
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25mm (0.010"). eB 15.494 – 17.526
e 2.540 TYP
13/02/2014
40P6, 40-lead (0.600"/15.24mm Wide) Plastic Dual

Inline Package (PDIP) 40P6 C

8.2. 44-pin TQFP
P IN 1 IDENTIFIER
P IN 1
e B
E1 E
D1
D
C 0°~7°
A1 A2 A
L
COMMON DIMENS IONS
(Unit of Me a s ure = mm)
S YMBOL MIN NOM MAX NOTE

A – – 1.20
A1 0.05 – 0.15
A2 0.95 1.00 1.05
D 11.75 12.00 12.25
D1 9.90 10.00 10.10 Note 2
Note s : E 11.75 12.00 12.25

1. This pa cka ge conforms to J EDEC re fe re nce MS -026, Va ria tion ACB. E1 9.90 10.00 10.10 Note 2
2. Dime ns ions D1 a nd E1 do not include mold protrus ion. Allowa ble
B 0.30 0.37 0.45
protrus ion is 0.25mm pe r s ide . Dime ns ions D1 a nd E1 a re ma ximum
pla s tic body s ize dime ns ions including mold mis ma tch. C 0.09 (0.17) 0.20
3. Le a d copla na rity is 0.10mm ma ximum. L 0.45 0.60 0.75
e 0.80 TYP
06/02/2014
44A, 44-le a d, 10 x 10mm body s ize , 1.0mm body thickne s s ,

44A C
0.8 mm le a d pitch, thin profile pla s tic qua d fla t pa cka ge (TQFP )

8.3. 44-pin VQFN
Marked Pin# 1 I D
SE ATING PLANE
A1
TOP VIEW
A3
A
K
L
Pin #1 Co rne r SIDE VIEW
D2
1 Option A Pin #1 COMMON DIMENSIONS

Triangl e
2 (Unit of Measure = mm)
3
SYMBOL MIN NOM MAX NOTE
A 0.80 0.90 1.00
E2
Option B
Pin #1 A1 – 0.02 0.05
Cham fe r
(C 0.30) A3 0.20 REF
b 0.18 0.23 0.30
D 6.90 7.00 7.10
K Option C Pin #1
D2 5.00 5.20 5.40
e Notch
b (0.20 R) E 6.90 7.00 7.10
BOTTOM VIEW E2 5.00 5.20 5.40

e 0.50 BSC
L 0.59 0.64 0.69
Note : JEDEC Standard MO-220, Fig . 1 (S AW Singulation) VKKD-3 .
K 0.20 0.26 0.41
9/26/08
TITLE GPC DRAWING NO. REV.
Package Drawing Contact: 44M1, 44-pad, 7 x 7 x 1.0mm body, lead
[email protected] pitch 0.50mm, 5.20mm exposed pad, thermally ZWS 44M1 H
enhanced plastic very thin quad flat no
lead package (VQFN)

Atmel Corporation 1600 Technology Drive, San Jose, CA 95110 USA T: (+1)(408) 441.0311 F: (+1)(408) 436.4200 | www.atmel.com
© 2016 Atmel Corporation. / Rev.: Atmel-42717A-ATmega644PA_Datasheet_Summary-05/2016
® ® ®
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intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND
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8-bit AVR Microcontrollers

High Performance, Low Power Atmel®AVR® 8-Bit Microcontroller Family

Atmel ATmega644PA [DATASHEET] 2

Atmel ATmega644PA [DATASHEET] 3

Features ATmega164PA ATmega324PA ATmega644PA ATmega1284P

Atmel ATmega644PA [DATASHEET] 4

20 1.8 - 5.5 Industrial

Atmel ATmega644PA [DATASHEET] 5

OC2A TC 2 TWI SDA

Atmel ATmega644PA [DATASHEET] 6

(PCINT27/TXD1/INT1) (TCK/PCINT18) Ground

(PCINT29/OC1A) (SCL/PCINT16) Analog

Atmel ATmega644PA [DATASHEET] 7

5.2. Pin Descriptions

5.2.3. Port A (PA[7:0])

Atmel ATmega644PA [DATASHEET] 8

5.2.4. Port B (PB[7:0])

5.2.5. Port C (PC[7:0])

5.2.6. Port D (PD[7:0])

Atmel ATmega644PA [DATASHEET] 9

1 6 A1 B2 PB[5] PCINT1 MOSI

2 7 B1 B1 PB[6] PCINT1 MISO

3 8 A2 C3 PB[7] PCINT1 SCK

9 14 A5 D3 PD[0] PCINT2 RxD0

10 15 B5 E2 PD[1] PCINT2 TxD0

11 16 A6 F1 PD[2] INT0 PCINT2 RxD1

12 17 A7 F2 PD[3] INT1 PCINT2 TXD1

13 18 B6 G2 PD[4] PCINT2 OC1B XCK1

14 19 A8 E3 PD[5] PCINT2 OC1A

15 20 B7 F3 PD[6] PCINT3 OC2B ICP1

16 21 A9 E4 PD[7] PCINT3 OC2A

17 - B8 C1 VCC RxD2 MISO1

18 - A10 A4 GND TxD2 MOSI1

19 22 B9 F4 PC[0] PCINT1 SCL

20 23 A11 G5 PC[1] PCINT1 SDA

21 24 B10 F5 PC[2] PCINT1 TCK

22 25 A12 G6 PC[3] PCINT1 TMS

23 26 A13 F6 PC[4] PCINT2 TDO

Atmel ATmega644PA [DATASHEET] 10

24 27 B11 E5 PC[5] PCINT2 TDI

25 28 A14 F7 PC[6] PCINT2 TOSC1

26 29 B12 E6 PC[7] PCINT2 TOSC2

29 32 A16 C7 AREF AREF

30 33 B14 D6 PA[7] PCINT7 ADC7

31 34 A17 C6 PA[6] PCINT6 ADC6

32 35 B15 B7 PA[5] PCINT5 ADC5

33 36 A18 D5 PA[4] PCINT4 ADC4

34 37 A19 B6 PA[3] PCINT3 ADC3

35 38 B16 A6 PA[2] PCINT2 ADC2

36 39 A20 C5 PA[1] PCINT1 ADC1

37 40 B17 B5 PA[0] PCINT0 ADC0

38 - A21 G3 VCC SDA1

39 - B18 A7 GND SCL1

40 1 A22 B4 PB[0] PCINT8 T0 XCK0

41 2 B19 C4 PB[1] PCINT9 CLKO T1

42 3 A23 A3 PB[2] INT2 PCINT1 AIN0

43 4 B20 B3 PB[3] PCINT1 AIN1 OC0A

44 5 A24 A2 PB[4] PCINT1 OC0B SS

Atmel ATmega644PA [DATASHEET] 11