LNCT GROUP OF COLLEGES

NAME : PRASHANT CHATURVEDI

DESIGNATIUON : ASSISTANT PROFESSOR

DEPARTMENT : ELECTRONICS & COMMUNICATION

ENGINEERING

SUBJECT : VLSI DESIGN

SUBJECT CODE : EC-701

UNIT : 1

TOPICS : Introduction, Size and complexity of Integrated

Circuits, The Microelectronics Field, IC
Production Process, Processing Steps, Packaging
and Testing, MOS Processes, NMOS Process,
CMOS Process, Bipolar Technology, Hybrid
Technology, Design Rules and Process
Parameters.
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INTRODUCTION

Very-large-scale integration (VLSI) is the process of creating an integrated

circuit (IC) by combining thousands of transistors into a single chip. VLSI began in
the 1970s when complex semiconductor and communication technologies were
being developed. The microprocessor is a VLSI device.

Before the introduction of VLSI technology, most ICs had a limited set of functions
they could perform. An electronic circuit might consist of a CPU, ROM, RAM and
other glue logic. VLSI lets IC designers add all of these into one chip.

The electronics industry has achieved a phenomenal growth over the last few
decades, mainly due to the rapid advances in large scale integration technologies
and system design applications. With the advent of very large scale integration
(VLSI) designs, the number of applications of integrated circuits (ICs) in high-
performance computing, controls, telecommunications, image and video processing,
and consumer electronics has been rising at a very fast pace.

The current cutting-edge technologies such as high resolution and low bit-rate video
and cellular communications provide the end-users a marvelous amount of
applications, processing power and portability. This trend is expected to grow
rapidly, with very important implications on VLSI design and systems design.

VLSI Design Flow

The VLSI IC circuits design flow is shown in the figure below. The various levels
of design are numbered and the blocks show processes in the design flow.
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Specifications comes first, they describe abstractly, the functionality, interface, and
the architecture of the digital IC circuit to be designed.
Behavioral description is then created to analyze the design in terms of
functionality, performance, compliance to given standards, and other specifications.
RTL description is done using HDLs. This RTL description is simulated to test
functionality. From here onwards we need the help of EDA tools.

RTL description is then converted to a gate-level netlist using logic synthesis tools.
A gate level netlist is a description of the circuit in terms of gates and connections
between them, which are made in such a way that they meet the timing, power and
area specifications. Finally, a physical layout is made, which will be verified and
then sent to fabrication.
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Y Chart

The Gajski-Kuhn Y-chart is a model, which captures the considerations in

designing semiconductor devices.

The three domains of the Gajski-Kuhn Y-chart are on radial axes. Each of the
domains can be divided into levels of abstraction, using concentric rings.

At the top level (outer ring), we consider the architecture of the chip; at the lower
levels (inner rings), we successively refine the design into finer detailed
implementation −

Creating a structural description from a behavioral one is achieved through the

processes of high-level synthesis or logical synthesis.

Creating a physical description from a structural one is achieved through layout

synthesis.
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Design Hierarchy-Structural

The design hierarchy involves the principle of "Divide and Conquer." It is nothing
but dividing the task into smaller tasks until it reaches to its simplest level. This
process is most suitable because the last evolution of design has become so simple
that its manufacturing becomes easier.
We can design the given task into the design flow process's domain (Behavioral,
Structural, and Geometrical). To understand this, let’s take an example of designing
a 16-bit adder, as shown in the figure below.

Here, the whole chip of 16 bit adder is divided into four modules of 4-bit adders.
Further, dividing the 4-bit adder into 1-bit adder or half adder. 1 bit addition is the
simplest designing process and its internal circuit is also easy to fabricate on the
chip. Now, connecting all the last four adders, we can design a 4-bit adder and
moving on, we can design a 16-bit adder.
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FPGA – Introduction

The full form of FPGA is “Field Programmable Gate Array”. It contains ten
thousand to more than a million logic gates with programmable interconnection.
Programmable interconnections are available for users or designers to perform
given functions easily. A typical model FPGA chip is shown in the given figure.
There are I/O blocks, which are designed and numbered according to function. For
each module of logic level composition, there are CLB’s (Configurable Logic
Blocks).
CLB performs the logic operation given to the module. The inter connection
between CLB and I/O blocks are made with the help of horizontal routing channels,
vertical routing channels and PSM (Programmable Multiplexers).
The number of CLB it contains only decides the complexity of FPGA. The
functionality of CLB’s and PSM are designed by VHDL or any other hardware
descriptive language. After programming, CLB and PSM are placed on chip and
connected with each other with routing channels.
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Advantages

 It requires very small time; starting from design process to functional chip.
 No physical manufacturing steps are involved in it.
 The only disadvantage is, it is costly than other styles.

Gate Array Design

The gate array (GA) ranks second after the FPGA, in terms of fast prototyping
capability. While user programming is important to the design implementation of
the FPGA chip, metal mask design and processing is used for GA. Gate array
implementation requires a two-step manufacturing process.
The first phase results in an array of uncommitted transistors on each GA chip.
These uncommitted chips can be stored for later customization, which is completed
by defining the metal interconnects between the transistors of the array. The
patterning of metallic interconnects is done at the end of the chip fabrication
process, so that the turn-around time can still be short, a few days to a few weeks.

The figure given below shows the basic processing steps for gate array implementation
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Typical gate array platforms use dedicated areas called channels, for inter-cell
routing between rows or columns of MOS transistors. They simplify the
interconnections. Interconnection patterns that perform basic logic gates are stored
in a library, which can then be used to customize rows of uncommitted transistors
according to the netlist.
In most of the modern GAs, multiple metal layers are used for channel routing.
With the use of multiple interconnected layers, the routing can be achieved over the
active cell areas; so that the routing channels can be removed as in Sea-of-Gates
(SOG) chips. Here, the entire chip surface is covered with uncommitted nMOS and
pMOS transistors. The neighboring transistors can be customized using a metal
mask to form basic logic gates.
For inter cell routing, some of the uncommitted transistors must be sacrificed. This
design style results in more flexibility for interconnections and usually in a higher
density. GA chip utilization factor is measured by the used chip area divided by the
total chip area. It is higher than that of the FPGA and so is the chip speed.

Standard Cell Based Design

A standard cell based design requires development of a full custom mask set. The
standard cell is also known as the polycell. In this approach, all of the commonly
used logic cells are developed, characterized and stored in a standard cell library.
A library may contain a few hundred cells including inverters, NAND gates, NOR
gates, complex AOI, OAI gates, D-latches and Flip-flops. Each gate type can be
implemented in several versions to provide adequate driving capability for different
fan-outs. The inverter gate can have standard size, double size, and quadruple size
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so that the chip designer can select the proper size to obtain high circuit speed and
layout density.
Each cell is characterized according to several different characterization categories,
such as,
 Delay time versus load capacitance
 Circuit simulation model
 Timing simulation model
 Fault simulation model
 Cell data for place-and-route
 Mask data
For automated placement of the cells and routing, each cell layout is designed with
a fixed height, so that a number of cells can be bounded side-by-side to form rows.
The power and ground rails run parallel to the upper and lower boundaries of the
cell. So that, neighboring cells share a common power bus and a common ground
bus. The figure shown below is a floorplan for standard-cell based design.
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Full Custom Design

In a full-custom design, the entire mask design is made new, without the use of any
library. The development cost of this design style is rising. Thus, the concept of
design reuse is becoming famous to reduce design cycle time and development cost.
The hardest full custom design can be the design of a memory cell, be it static or
dynamic. For logic chip design, a good negotiation can be obtained using a
combination of different design styles on the same chip, i.e. standard cells, data-
path cells, and programmable logic arrays (PLAs).
Practically, the designer does the full custom layout, i.e. the geometry, orientation,
and placement of every transistor. The design productivity is usually very low;
typically a few tens of transistors per day, per designer. In digital CMOS VLSI,
full-custom design is hardly used due to the high labor cost. These design styles
include the design of high-volume products such as memory chips, high-
performance microprocessors and FPGA.
An incorporated circuit or monolithic integrated circuit (also known as an ic,
a chip, or a microchip) is a hard and fast of digital circuits on one small plate of
semiconductor cloth, typically silicon. This could be made plenty smaller than a
discrete circuit made from independent additives. Ics may be made very compact,
having up to several billion transistors and other electronic additives in an area the
size of a fingernail. The width of every accomplishing line in a circuit may be made
smaller and smaller because the generation advances; in 2008 it dropped below one
hundred nanometers and in 2017 approximately 7 nanometer.
Ics had been made possible via experimental discoveries showing that
semiconductor gadgets ought to perform the features of vacuum tubes and via mid-
20th-century technology advancements in semiconductor tool fabrication.
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The integration of huge numbers of tiny transistors into a small chip become an
giant development over the guide assembly of circuits the usage of discrete
electronic components. The incorporated circuits mass production functionality,
reliability, and building-block method to circuit design ensured the rapid adoption
of standardized included circuits in region of designs the usage of discrete
transistors.
There are two major advantages of ics over discrete circuits: value and overall
performance. Price is low because the chips, with all their components, are
published as a unit by using photolithography instead of being built one transistor at
a time. Moreover, lots much less cloth is used to assemble a packaged ic die than to
assemble a discrete circuit. Overall performance is excessive because the additives
transfer quick and eat little electricity (in comparison to their discrete counterparts)
as a result of the small size and near proximity of the components. Incorporated
circuits are used in genuinely all digital equipment nowadays and have
revolutionized the arena of electronics. Computer systems, cellular phones, and
different virtual domestic appliances are actually inextricable parts of the shape of
modern societies, made viable with the aid of the low value of manufacturing
integrated circuits.
Terminologies related to included circuit design are:

 Integrated circuit (IC): IC is an aggregate of interconnected circuit

factors related on or inside a substrate.
 Substrate: Supporting material upon or within an IC is fabricated.
 Hybrid IC: IC consists of a combination of two or more IC or an IC with
some discrete elements.
 Monolithic IC: An IC whose elements are fashioned in place upon or
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inside a semiconductor substrate with at least one of the factors fashioned
within the substrate.
 Wafer or Slice: It is a physical unit used in processing. Typically wafer is
circular; production wafers have a diameter of 4,5 or 6 in.
 Chip or die or bar: It is one of the repeated ics on a wafer. Manufacturing
wafer may additionally includes 20 or 30 ics, or numerous loads or hundreds
depending upon the complexity and size of circuit fabricated.
 Test Plug: It's miles a special chip repeated only for few times on every
wafer. Used to reveal the manner parameters of the generation. After processing,
the verification of system is tested by means of measuring, at the wafer probe
degree, the characteristics of devices or circuits at the take a look at plug. If the
important thing parameters at the test plug stage aren't matched , the wafer is
discarded. Test plug is likewise called manner manage bar (pcb) or manner
manipulate display (pcm).
 Test cell: Special chip repeated only few times on each wafer. The circuit
designers include test cell to monitor the performance of subcircuits or
subcomponents.

Size and complexity of Integrated Circuits

IC are classified in terms of device count used in the design of the circuit and in
terms of the minimum feature size (such as minimum gate length or minimum
polysilicon width or minimum metal width) or in terms of the pitch (minimum of
the sum of the minimum width of a feature and minimum spacing between similar
features). The pitch is often nearly twice the minimum feature size.

Classification of IC by device count:

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Nomenclature Active device count

SSI Small scale integration. 1-100
MSI Medium scale integration. 100-1000.
LSI Large scale integration. 1000-100000
VLSI Very large scale integration. 10 5 – 10 6

Classification based on feature size:

Year Minimum Feature Size in microns

(µ)
1970 7 to 10
1980 5
Mid-1980 2 to 1.25
1990 0.75 to 0.25

Limitations associated with shrinking the feature size:

 Wear and tear in matching characteristics.
 Increased cost of equipments required for processing the wafers.
 Advanced software design aids required.
 Increased impact of interconnection delays.
 Increased power dissipation and processing complications associated with
heat cycling limitations during fabrication.
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Wafer Size: The number of devices that could potentially be placed on a wafer is
strongly dependent upon the wafer size. For example, in a 5µ process, the 1 cm2
chip can accommodate the gates of about 4 million 5µ x 5µ transistors.

Advantages of using smaller size die or chip are:

i) Fabrication of more chips per wafer. b) Reduction in effective cost per chip. C)
Percentage of good chips increases. D) Rectangular chips are fabricated on round
wafers, the amount of wafer wasted around the periphery is reduced.

Major factors which place limits on decreasing device dimensions:

i) Gate oxide thickness: If gate oxides thickness becomes thinner about 50
Armstrong, by decreasing dimensions, quantum mechanical tunneling occurs, thus
placing a practical bound on oxide thickness.
ii) Electric field strength: High electric field strengths are also taken into concern.
Voltages upto 5v are placed across 1000 Armstrong silicon dioxide insulating
layer. Hence, the electric field of magnitude is

This field is large but less than the break down voltage of silicon dioxide ie. (5 -10
MV/cm)

If the same voltage is applied to 100 A° thickness of oxide layer, the electric field
would be very near to the breakdown field for the oxide. So the only option is to
decrease the voltage applied across the oxide layer. But this is not an option
because the voltage decrease noise effect becomes more significant and thus
increasing the chance of errors in the circuit.
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The Microelectronics Field

Microelectronics is a subfield of electronics. As the name suggests,

microelectronics relates to the observe and manufacture (or micro fabrication) of
very small electronic designs and components. Those devices are typically crafted
from semiconductor substances. Many components of ordinary digital layout are
available in a microelectronic equivalent. Those include transistors, capacitors,
inductors, resistors, diodes and insulators and conductors can all be found in
microelectronic gadgets. Precise wiring techniques consisting of twine bonding
also are regularly used in microelectronics because of the strangely small length of
the components, leads and pads. This approach calls for specialized device and is
costly.
In virtual packages, MOS devices offer very low static strength intake. In analog
programs, circuit complexity is decreased in cmos method as opposed to the usage
of nMOS or pMOS procedure. Applications of cmos procedure are recollections,
interfacing, microprocessors, simple logic features and many others.
Bi-mos is a method combining bipolar and mos devices in a single technique. This
is complicated and costly system.

IC Production Process, Processing Steps

Creating the Diffusion and Photolithography

wafer Deposition

Etching and
Metallization
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Wafer preparation
Wafer fabrication is a procedure composed of many repeated sequential processes
to produce complete electrical or photonic circuits on
semiconductor wafers. Examples include production of radio frequency (RF)
amplifiers, LEDs, optical computer components, and CPUs for computers.

Oxidation
In micro fabrication, thermal oxidation is a way to produce a thin layer
of oxide (usually silicon dioxide) on the surface of a wafer. The technique forces an
oxidizing agent to diffuse into the wafer at high temperature and react with it.

Masking:-
IC masks are high-contrast photographic positives or negatives, used to prevent
light from striking a photosensitized wafer during a photolithographic process. The
masks are made of glass covered with a thin film of opaque material. Electron beam
method is used to generate the actual patterns directly onto the final masks. This
method produces the best quality masks and used for small geometries. Another
method used to generate masks is laser beam pattern generator.

Photolithography
Photolithography, also called optical lithography or UV lithography, is a process
used in microfabrication to pattern parts on a thin film or the bulk of a substrate. It
uses light to transfer a geometric pattern from a photomask to a photosensitive
chemical photoresist on the substrate
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Fig: Comparison of positive and negative photoresists

Deposition
The film of numerous materials have to be applied at the wafer at some point of
processing. Film that are deposited include insulators, resistive film, conductive
movies, dielectrics, n and p kind substances available technologies consist of
physical vapor deposition (pvd), chemical vapor deposition (cvd), electrochemical
deposition (ecd) and molecular beam epitaxial (mbe) and extra recently, atomic
layer deposition (ald) among others.

Diffusion
Diffusion refers to the controlled forced migration of impurities into the substrate
.this plays a major role in the performance of the IC and is affected by temperature
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and time during the processing. Methods of diffusion: A solid deposition layer or a
gaseous layer above the surface can be used as a source of impurities. Impurities
can be bombarded to the substrate so that they actually become lodged inside the
substrate very near the surface. This is ion implantation, very accurate control of
impurity concentrations but causes damage to the crystal surface. Impurities
typically diffuse both vertically and laterally from the surface at comparable rates

Packaging and Testing

After processing, the circuits are tested and packaged. The first step in the testing
process generally involves a process verification to make certain that the process
parameters are within the tolerance acceptable for the product. To facilitate this
verification, test plug containing special test structures specially designed for this
purpose are included on the wafer at several locations in place of the regular circuits
themselves.

Packaging for integrated circuits:

Proper packaging technology is critical to the success of the chip development.
Package issues have to be taken into consideration in early stages of chip
development. Ensure sufficient design margins to accommodate the parasitic of the
package.

Important packaging concerns:

 Hermetic seals to prevent the penetration of moisture.
 Thermal conductivity.
 Thermal expansion coefficient.
 Pin density.
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 Parasitic inductance and capacitance.
 α particle protection.
 Cost.

MOS PROCESSES
MOS Technology comprises of 3 process basically, p-channel MOS, n-
channel MOS and CMOS process. The basic purpose of all these process is to
enhance MOSFET performance one over the other, like lower power consumption,
high power capability, reliability improvements, response speed etc.

There are a large number and variety of basic fabrication steps used in the
production of modern MOS ICs. The same process can be used for the desinged of
NMOS or PMOS or CMOS devices. The gate material could be either metal or
poly-silicon. The most commonly used substrate is bulk silicon or silicon-on-
sapphire (SOS). Inorder to avoid the presence of parasitic transistors, variations are
brought in the techniques that are used to isolate the devices in the wafer.
The fabrication steps are as follows:
Step1:
Processing is carried on single crystal silicon of high purity on which required P
impurities are introduced as crystal is grown. Such wafers are about 75 to 150 mm
in diameter and 0.4 mm thick and they are doped with say boron to impurity
concentration of 10 to power 15/cm3 to 10 to the power 16 /cm3.
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Step 2:
A layer of silicon dioxide (SiO2) typically 1 micrometer thick is grown all over the
surface of the wafer to protect the surface, acts as a barrier to the dopant during
processing, and provide a generally insulating substrate on to which other layers
may be deposited and patterned.

Step 3:
The surface is now covered with the photo resist which is deposited onto the wafer
and spun to an even distribution of the required thickness.

Step 4:
The photo resist layer is then exposed to ultraviolet light through masking which
defines those regions into which diffusion is to take place together with transistor
channels. Assume, for example, that those areas exposed to uv radiations are
polymerized (hardened), but that the areas required for diffusion are shielded by the
mask and remain unaffected.

Step 5:
These areas are subsequently readily etched away together with the underlying
silicon dioxide so that the wafer surface is exposed in the window defined by the
mask.
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Step 6:
The remaining photo resist is removed and a thin layer of SiO2 (0.1 micro m
typical) is grown over the entire chip surface and then poly silicon is deposited on
the top of this to form the gate structure. The polysilicon layer consists of heavily
doped polysilicon deposited by chemical vapour deposition (CVD). In the
fabrication of fine pattern devices, precise control of thickness, impurity
concentration, and resistivity is necessary

Step 7:
Further photo resist coating and masking allows the poly silicon to be patterned and
then the thin oxide is removed to expose areas into which n-type impurities are to
be diffused to form the source and drain. Diffusion is achieved by heating the wafer
to a high temperature and passing a gas containing the desired n-type impurity.
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Note: The poly silicon with underlying thin oxide and the thick oxide acts as mask
during diffusion the process is self aligning.

Step 8:
Thick oxide (SiO2) is grown over all again and is then masked with photo resist
and etched to expose selected areas of the poly silicon gate and the drain and source
areas where connections are to be made. (contacts cut)
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Step 9:
The whole chip then has metal (aluminium) deposited over its surface to a thickness
typically of 1 micro m. This metal layer is then masked and etched to form the
required interconnection pattern.

Working Principle of MOSFET P Channel N Channel MOSFET

MOSFET stands for Metal Oxide Semiconductor Field Effect Transistor. The
mosfet is a capacitor operated transistor device. The capacitor plays an essential
role for operating a MOSFET. We also call the device as Insulated Gate Field
Effect Transistor (IGFET) or Metal Insulator Field Effect Transistor (MIFET). Why
we call so we will understand when we look into the constructional features of this
transistor device. We must take a look into the construction of MOSFET while
going through the working principle of mosfet. Construction wise we can categorise
the device into four types.

 P – Channel Enhancement MOSFET

 N – Channel Enhancement MOSFET
 P – Channel Depletion MOSFET
 N – Channel Depletion MOSFET

P – Channel Enhancement MOSFET

p channel MOSFET as PMOS. Here, a substrate of lightly doped n-type
semiconductor forms the main body of the device. We usually use silicon or
gallium arsenide semiconductor material for this purpose. Two heavily doped p-
type regions are there in the body separated by a certain distance L. We refer this
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distance L as channel length and it is in order of 1 µm.

Now there is a thin layer of silicon dioxide (SiO2) on the top of the substrate. We
may also use Al2O3 for the purpose but SiO2 is most common. This layer on the
substrate behaves as a dielectric. There is an aluminum plate fitted on the top of this
SiO2 dielectric layer.
Now the aluminum plate, dielectric and semiconductor substrate form a capacitor
on the device.

The terminals connected to two p-type regions are the source (S) and drain (D) of
the device respectively. The terminal projected from the aluminum plate of the
capacitor is gate (G) of the device. We also connect the source and body of the
mosfet to earth to facilitate the supply and withdrawal of free electrons as per
requirement during operation of the MOSFET.
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Now let us apply a negative voltage at gate (G). This will create negative static
potential at the aluminum plate of the capacitor. Due to capacitive action, positive
charge gets accumulated just below the dielectric layer.
Basically, the free electrons of that portion of the n-type substrate get shifted away
due to the repulsion of negative gate plate and consequently layers of uncovered
positive ions appear here. Now if we further increase the negative voltage at the
gate terminal, after a certain voltage called threshold voltage, due to the
electrostatic force, covalent bonds of the crystal just below the SiO 2 layer start
breaking. Consequently, electron-hole pairs get generated there. The holes get
attracted and free electrons get repealed due to the negativity of the gate. In this
way, the concentration of holes increases there and create a channel of holes from
source to drain region. Holes also come from both heavily doped p-type source and
drain region. Due to the concentration of holes in that channel the channel becomes
conductive in nature through which electric current can pass.
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Now let us apply a negative voltage at drain terminal. The negative voltage in the
drain region reduces the voltage difference between gate and drain reduces, as a
result, the width of the conductive channel get reduced toward the drain region as
shown below. At the same time, current flows from source to drain shown by
arrowhead

The channel created in the mosfet offers a resistance to the current from source to
drain. The resistance of the channel depends on the cross-section of the channel
and the cross section of the channel again depends on the applied negative gate
voltage. So we can control the current from the source to drain with the help of an
applied gate voltage hence MOSFET is a voltage controlled electronic device. As
the concentration of holes forms the channel, and the current through the channel
gets enhanced due to increase in negative gate voltage, we name the MOSFET as P
– Channel Enhancement MOSFET.

N – Channel Enhancement MOSFET

Working of N – Channel Enhancement MOSFET is similar to that of P – Channel
Enhancement MOSFET but only operationally and constructionally these two are
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different from each other. In N Channel Enhancement MOSFET a lightly doped p-
type substrate forms the body of the device and source and drain regions are heavily
doped with n-type impurities. Here also we connect the body and source commonly
to the ground potential. Now, we apply a positive voltage to the gate terminal. Due
to positivity of the gate and corresponding capacitive effect, free electrons i.e.
minority carriers of the p-type substrate get attracted towards the gate and form a
layer of negative uncovered ions there just below the dielectric layer by
recombining these free electrons with holes. If we continually increase the positive
gate voltage, after the threshold voltage level, the recombinations process gets
saturated and then free electrons start to accumulate at the place to form a
conductive channel of free electrons. The free electrons also come from the heavily
doped source and drain n-type region. Now if we apply a positive voltage at the
drain, current start flowing through the channel. The resistance of the channel
depends on the number of free electrons in the channel and the number of free
electrons in the channel again depends on the gate potential of the device. As the
concentration of free electrons forms the channel, and the current through the
channel gets enhanced due to increase in gate voltage, we name the MOSFET as N
– Channel Enhancement MOSFET

.
N – Channel Depletion MOSFET
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The working principle of depletion MOSFET is a little bit different from that of
enhancement MOSFET. N – Channel Depletion MOSFET the substrate (body) is of
p-type semiconductor. The source and drain regions are of the heavily doped n-type
semiconductor. The space between source and drain regions is diffused by n-type
impurities. Now if we apply a potential difference between source and drain, a
current starts flowing through the entire n region of the substrate.

Now, let us apply a negative voltage at the gate terminal. Due to the capacitive
effect, the free electrons get repealed and shifted downward in the n region just
below the SiO2 dielectric layer. As a result, there will be layers of positive
uncovered ions below the SiO2 dielectric layer. In this way, there will be a
depletion of charge carriers occurred in the channel and hence the overall
conductivity of the channel gets reduced. In this situation, for the same applied
voltage at the drain, the drain current gets reduced. Here we have seen that we can
control the drain current by varying depletion of charge carriers in the channel and
hence we call it as depletion MOSFET. Here, the drain is in a positive potential,
the gate is in a negative potential and the source is at zero potential. So the voltage
difference between drain to gate is more than that of source to gate, hence the
width of the depletion layer is more towards drain than that towards the source.
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P – Channel Depletion MOSFET

Cotruction wise a p channel depletion MOSFET is just reverse of the n channel

depletion MOSFET. Here the pre build channel is made of p – type impurities in
between heavily doped p – type source and drain region. When we apply a positive
voltage at the gate terminal, due to electrostatic action, minority carriers i.e. free
electrons of the p-type region get attracted and form static negative impurity ions
there. Hence a depletion region gets formed in the channel and consequently, the
conductivity of the channel gets reduced. In this way, by applying the positive
voltage at gate we can control the drain current.

Complementary MOS Technology

It is a combination of both n-channel and p-channel devices in one chip. Compared
to both other process, CMOS is complex in fabrication and requires larger chip
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area. Biggest advantage of a CMOS circuit is reduced power consumption (less
than NMOS); it is designed for zero power consumption in steady state condition
for both logic states. As you may already know, CMOS circuits are widely used in
digital equipments like watches, computers etc. CMOS offers comparatively higher
circuit density and high speed performance (used in VLSI); and this is the primary
reason why CMOS is still preferred despite its complex manufacturing process.
Memories and microprocessors made of CMOS usually employ silicon gate
process.
There are variations of MOS technology which offer either better
performance or density advantages over the standard process. Some of those are
named as VMOS (V-groove MOS), DSA (Diffusion Self Aligned), SOS (Silicon
on Sapphire), D-MOS (Double diffused MOS) etc.

Characteristics of CMOS Technology

 Lower static power dissipation Higher noise margins

 Higher packing density – lower manufacturing cost per device High yield
with large integrated complex functions
 High input impedance (low drive current) Scalable threshold voltage
 High delay sensitivity to load (fan-out limitations)
 Low output drive current (issue when driving large capacitive loads)
 Low trans conductance, where trans conductance, gm a Vin
 Bi-directional capability (drain & source are interchangeable) A near ideal
switching device
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Bi-CMOS Technology
BiCMOS technology is a combination of Bipolar and CMOS technology.
CMOS technology offers less power dissipation, smaller noise margins, and higher
packing density. Bipolar technology, on the other hand, ensures high switching and
I/O speed and good noise performance.

Characteristics of Bipolar Technology

 Higher switching speed
 Higher current drive per unit area
 Higher gain
 Better noise performance and better high frequency characteristics
 Better analogue capability
 Improved I/O speed (particularly significant with the growing importance of
package limitations in high speed systems).
 High power dissipation
 Lower input impedance (high drive current) Low voltage swing logic
 Low packing density
 Low delay sensitivity to load
 High unity gain band width (ft) at low currents

Hybrid Technology
hybrid integrated circuit A complete electronic circuit that is fabricated on an
insulating substrate using a variety of device technologies. The substrate acts as a
carrier for the circuit and also has the interconnecting tracks between devices
printed on it by multilayer techniques. Individual devices, which comprise chip
diodes, transistors, integrated circuits, and thick-film resistors and capacitors and
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which form the circuit function, are attached to the substrate and are connected
together using the previously defined interconnecting tracks.
A hybrid integrated circuit, HIC, hybrid microcircuit, or simply hybrid is a
miniaturized electronic circuit constructed of individual devices, such as
semiconductor devices (e.g. transistors and diodes) and passive components (e.g.
resistors, inductors, and capacitors), bonded to a substrate or printed circuit board
he advantage of hybrid circuits is that components which cannot be included in a
monolithic IC can be used, e.g., capacitors of large value, wound components,
crystals, inductors. Thick film technology is often used as the interconnecting
medium for hybrid integrated circuits. Thick film technology is often used as the
interconnecting medium for hybrid integrated circuits. The use of screen printed
thick film interconnect provides advantages of versatility over thin film although
feature sizes may be larger and deposited resistors wider in tolerance. Multi-layer
thick film is a technique for further improvements in integration using a screen
printed insulating dielectric to ensure connections between layers are made only
where required.

Design Rules and Process Parameters

In VLSI design, as processes become more and more complex, need for the
designer to understand the intricacies of the fabrication process and interpret the
relations between the different photo masks is really trouble some. Therefore, a set
of layout rules, also called design rules, has been defined. They act as an interface
or communication link between the circuit designer and the process engineer
during the manufacturing phase. The objective associated with layout rules is to
obtain a circuit with optimum yield
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(functional circuits versus non-functional circuits) in as small as area possible
without compromising reliability of the circuit. In addition, Design rules can be
conservative or aggressive, depending on whether yield or performance is desired.
Generally, they are a compromise between the two. Manufacturing processes have
their inherent limitations in accuracy. So the need of design rules arises due to
manufacturing problems like –
 Photo resist shrinkage, tearing.
 Variations in material deposition, temperature and oxide thickness.
 Impurities.
 Variations across a wafer.

These lead to various problems like

 Transistor problems
 Variations in threshold voltage - This may occur due to variations in
oxide thickness, ion-implantation and poly layer Changes in source/drain
diffusion overlap. Variations in substrate.
 Wiring problems
 Diffusion: There is variation in doping which results in variations in
resistance, capacitance. Poly, metal: Variations in height, width resulting
in variations in resistance, capacitance. Shorts and opens.
 Oxide problems: Variations in height. Lack of planarity.
 Via problems: Via may not be cut all the way through. Undersize via
has too much resistance. Via may be too large and create short.
To reduce these problems, the design rules specify to the designer certain
geometric constraints on the layout artwork so that the patterns on the
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processed wafers will preserve the topology and geometry of the designs.
This consists of minimum-width and minimum-spacing constraints and
requirements between objects on the same or different layers. Apart from
following a definite set of rules, design rules also come by experience.

Types of Design Rules

The design rules primary address two issues
 The geometrical reproduction of features that can be reproduced by the
maskmaking and lithographical process.
 The interaction between different layers.

There are primarily two approaches in describing the design rules.

 Linear scaling is possible only over a limited range of dimensions.
 Scalable design rules are conservative .This results in over dimensioned and
less dense design.
 This rule is not used in real life.

Scalable Design Rules (e.g. SCMOS, λ-based design rules)

In this approach, all rules are defined in terms of a single parameter λ. The
rules are so chosen that a design can be easily ported over a cross section of
industrial process, making the layout portable .Scaling can be easily done by
simply changing the value of.
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Absolute Design Rules (e.g. μ-based design rules )
In this approach, the design rules are expressed in absolute dimensions (e.g.
0.75μm) and therefore can exploit the features of a given process to a
maximum degree. Here, scaling and porting is more demanding, and has to
be performed either manually or using CAD tools .Also, these rules tend to
be more complex especially for deep submicron. The fundamental unity in
the definition of a set of design rules is the minimum line width .It stands for
the minimum mask dimension that can be safely transferred to the
semiconductor material .Even for the same minimum dimension, design rules
tend to differ from company to company, and from process to process. Now,
CAD tools allow designs to migrate between compatible processes.

Layer Representations

With increase of complexity in the CMOS processes, the visualization of all

the mask levels that are used in the actual fabrication process becomes
inhibited. The layer concept translates these masks to a set of conceptual
layout levels that are easier to visualize by the circuit designer. From the
designer's viewpoint, all CMOS designs have the following entities.
 Two different substrates and/or wells: which are p-type for NMOS and
n-type for PMOS.
 Diffusion regions (p+ and n+): which defines the area where transistors
can be formed. These regions are also called active areas. Diffusion of
an inverse type is needed to implement contacts to the well or to
substrate.
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 These are called select regions.
 Transistor gate electrodes : Polysilicon layer
 Metal interconnect layers • Interlayer contacts and via layers.

The layers for typical CMOS processes are represented in various figures in
terms of:
 A color scheme (Mead-Conway colors).
 Other color schemes designed to differentiate CMOS structures.
 Varying stipple patterns
 Varying line styles

Stick Diagrams

Another popular method of symbolic design is "Sticks" layout. In this, the

designer draws a freehand sketch of a layout, using colored lines to represent
the various process layers such as diffusion, metal and polysilicon .Where
polysilicon crosses diffusion, transistors are created and where metal wires
join diffusion or polysilicon, contacts are formed. This notation indicates
only the relative positioning of the various design components. The absolute
coordinates of these elements are determined automatically by the editor
using a compactor. The compactor translates the design rules into a set of
constraints on the component positions, and solve a constrained optimization
problem that attempts to minimize the area or cost function. The advantage of
this symbolic approach is that the designer does not have to worry about
design rules, because the compactor ensures that the final layout is physically
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correct. The disadvantage of the symbolic approach is that the outcome of the
compaction phase is often unpredictable. The resulting layout can be less
dense than what is obtained with the manual approach. In addition, it does not
show exact placement, transistor sizes, wire lengths, wire widths, tub
boundaries.
Design Rules and Process Parameters
1 p-well Layer
1.1 Width 5 4λ
1.2 Spacing to well at different potential 15 10 λ
1.3 Spacing to well at same potential 9 6λ
2 Active (Diffusion ) Layer
2.1 Width 4 2λ
2.2 Spacing to active 4 2λ
2.3 P+ active in n-subs to p-well edge 8 6λ
2.4 n+ active in n-subs to p-well edge 7 5λ
2.5 n+ active in p-well to p-well edge 4 2λ
2.6 p+ active in p-well to p-well edge 1 λ
3 Poly
3.1 Width 3 2λ
3.2 Spacing 3 2λ
3.3 Field poly to active 2 Λ
3.3 Poly overlap of active 3 2λ
3.4 Active overlap of poly 4 2λ
4 P+ Select
4.1 Overlap of active 2 λ
4.2 Space to n+ active 2 λ
4.3 Overlap of channel 3.5 2λ
4.4 Space to channel 3.5 2λ
4.5 Space to P+ select 3 2λ
4.6 width 3 2λ

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