An Introduction to

RTL to GDSII Flow

ASIC Design Flow

Specification

Logic Design (HDL)

Logic Verification

IC Design
Logic/Physical Synthesis

Floor-planning

Power Planning

Placement

Clock tree Synthesis

Routing

GDS Other info

 ASIC Design Flow

Specification

Logic Design (HDL)

Front End
Logic Verification

IC Design
Logic/Physical Synthesis

Floor-planning

Power Planning
Backend
Placement

Clock tree Synthesis

Routing

GDS Other info

 Logical Synthesis
• Definition: Logic Synthesis is a process of converting high level
description (HDL) of a design into a optimized gate level
representation (Netlist) given a standard cell library and certain
design constraints.

Synthesis = Translation + Optimization

Inputs :
1. Verilog RTL code (HDL),
2. Library (Cell Library, contains logic and timing information)
3. Design constraints

Output : Gate level netlist

Synopsys Design Compiler being the most widely used tool for
logical Synthesis

– Gain Based Synthesis: Based on Theory Of Logical Effort

– Traditional Synthesis: Based on Wire load Models
 Synthesis Goals

Goals may include producing designs with

 Maximum Speed.
 Minimum Area.
 Minimum Gate Count.
 Minimum Sequential Elements.
 Minimum Power Consumption.
 Maximum Reliability.
 Design Objects
 Design
Circuit description that perform some logical function.
 Cell
A unique instance of design within another design.
 Reference
The instantiated sub design or lib cell.
 Port
Inputs and outputs of design.
 Pin
Inputs and outputs of cells within a design.
 Net
Wires that connect ports to pins and pins to each other.
 Clock
Clock of design.
design1/port1 u1/pin1
design1/port3

design1/port2 u1/pin2
u1 u2
U2/pin3

design1
 Cells and References
References Link Library
Tech lib

nand2 nand2
u1 nand2
and3_H
nand2
u2 multiplier

Adder
nand2 multiplier
u3 multiplier
u4
Develop HDL files

Specify Libraries Compile/Optimize

Read Design Analyze & Resolve

problems

Define Design
Environment Netlist

Set Design
Constraints
 Technology Library
 Technology libraries contain information about the
characteristics and functions of each cell provided in a
semiconductor vendor’s library.
 Cell characteristics include information such as cell names, pin
names, area, delay arcs, and pin loading.
 DRC: Design Rule Constraints
 Operating conditions
 Wireload models specific to that technology
In Synthesis Technology library is used for-
-Mapping
-Calculating timing and Path delays
-Resolving cell references
-Calculating power consumption

Target Library/ Link Library/Symbol Library

 Design Environment
 Defining the Operating Conditions
 Defining Wire Load Models
 Modeling the System Interface

Operating Conditions
 Operating temperature variation
 To model the effects on performance caused by temperature
fluctuations.
 Supply voltage variation
 The design’s supply voltage can vary from the established ideal
value during day-to-day operation. It is used to model the effect
on performance of design.
 Process variation
 This variation accounts for deviations in the semiconductor
fabrication process. Usually process variation is treated as a
percentage variation in the performance calculation.
****************************************
Report : library
Library: my_lib
Version: 1999.05
Date : Mon Jan 4 10:56:49 1999
****************************************
...
Operating Conditions:
Name Library Process Temp Volt
-----------------------------------------------------------------
WCCOM my_lib 1.50 70.00 4.75
WCIND my_lib 1.50 85.00 4.75
WCMIL my_lib 1.50 125.00 4.50
 Wireload Models
 To estimate the effect of wire length and fanout on the
resistance, capacitance, and area of nets. Design Compiler
uses these physical values to calculate wire delays and circuit
speeds.
 Semiconductor vendors develop wire load models, based on
statistical information specific to the vendors’ process.
 The models include coefficients for
 Area per unit length
 Capacitance per unit length
 Resistance per unit length
 A fanout-to-length table or slope for estimating net lengths (the
number of fanout determines a nominal length).
 Three modes for Hierarchical Designs
 Top
 Enclosed
 Segmented
****************************************
Report : library
Library: my_lib
Version: 1999.05
Date : Mon Jan 4 10:56:49 1999
****************************************
Wire Loading Model:
Name : 05x05
Location : my_lib
Resistance : 0
Capacitance : 1
Area : 0
Slope : 0.186
------------------------------------------------------------------------
1 0.39
 System Interface

Drive Strength

Set operating condition

Input Driving Cell Set wireload model
Fanout
 Defining Design Constraints
 Design rule constraints (DRC)
 Transition time- The transition time of a net is the time
required to change logic values. This transition time is based
on the technology library data.

 Fanout load -The maximum fanout load for a net is the

maximum number of loads the net can drive.

 Capacitance – Synthesis tool calculates the capacitance on

the output net by adding the wire capacitance of the net to
the capacitance of the pins attached to the net. It compares
with the output pin’s max_capacitance value.

 Design optimization constraints

 Timing constraints: Max delay, Min delay, False path,
multicycle path
 Area constraints: Max Area
 Compilation
Following are the steps that lead to a creation of technology
specific gate level netlist

 Mapping
– This process uses gates (combinational and sequential)
from the target technology libraries to generate a gate-level
implementation of the design whose goal is to meet timing
and area goals.

 Delay optimization
– The process goal is to fix delay violations introduced in the
mapping phase.
– Delay optimization does not fix design rule violations or meet
area constraints.
 Compilation

 Design rule fixing

– The process goal is to correct design rule violations by
inserting buffers or resizing existing cells.
– Effort is to fix these violations without affecting timing and
area results, but if necessary, it does violate the optimization
constraints.
 Area optimization
– The process goal is to meet area constraints after the
mapping,delay optimization, and design rule fixing phases
are completed.

After complete flow we write out the netlist and sdc file.
Typical Place & Route Tool Flow

Import Global & Detail

Placement
(Libraries & Design) Routing

Clock Tree Output

Floor Plan Generation
Synthesis

Power Planning Placement

& Routing Optimization
 Import Data

 Verilog RTL design description or Verilog mapped netlist

 Logic and timing library in .lib format
 Technology rules in M-Tcl or LEF format
 Physical library in LEF or GDSII format
 Parasitic extraction rules in Tcl format
 Timing constraints in SDC format

 If going for noise analysis, we also need noise rules.

 Floor-Planning
Floor-planning is the process of
positioning blocks on the die or within
another block, thereby defining routing
areas between them. Floor-planning
includes following steps:

 Bind physical library to design.

 Specify power and ground nets
 Initialize the core and the physical data
model
 Defining I/O Pads and Pins.
 Place Macro Cells
 Create Placement Blockages

Objectives of Floor-planning

• Reduce Die area

• Meet Timing constraints: Predicting interconnect delay by
estimating interconnect length
 Floorplanning Module Constraints
•There are five module constraint types:
– None
A module has the attribute “None” if it is not preplaced in the core design area. A
module can be preplaced by moving it to the core area or by loading in a floorplan file
where the module’s placement is defined.
– Soft Guide (Attribute: SoftGuide)
This module constraint is similar to a guide constraint, except there are no fixed
locations. This provides stronger grouping for the instances under the same soft
guide. Instances within a soft guide are grouped better than without a soft guide.
– Guide (Attribute: Guide)
A module is preplaced in the core design area. The placement program honors the
preplacement.
– Region (Attribute: Region)
A region constraint forces all module instances to be placed within the region, but
allows instances from other modules as well.
– Fence (Attribute: Fence)
A fence constraint forces all instances of the module to be placed within the fence and
does not allow any instances from other modules to be placed inside the fence. A
module becomes a fence when the module is specified as a partition.

22
Important Terms

Pad cell/ Standard cell/ Hard Macro/ Soft Macro

Aspect Ratio = Width/Height

A pad-limited die. The number of pads determines the die

size.
A core-limited die: The core logic determines the die size.

Cell Row: Standard Cell Placement Row

Blockage: Routing/Placement/Standard Cell/ Non-Buffer/

Power

Chip Utilization: Total Area Used / Total Area Available

Effective Utilization: Total Standard Cell Area Used / Total

Area available for Standard Cell Placement

DEF File: Design Exchange Format

 Power Planning

Tasks in Power Planning

•Core and macro rings
•Power and ground mesh
•Rails
•Pin taps and pin ties
•I/O pad rings for chips and
I/O pin rings for macros and
other blocks
 Placement
Floor planning was identifying the specific areas for
different cells. Placement is actually placing the cells in
those areas and achieving legal and optimized results.

 The placer distributes the cells across the available core area,
minimizing wire length and ensuring constant delay.
 All the standard cells are placed in cell rows with no overlapping of
cells.
 Congestion and timing are two main aspects to be taken care of
during placement.
 Congestion comes when cells are placed in such a manner that
there are problems in routing them.
 We also need some area margin for CTS and further optimization
later on in the flow.
 Power Planning
Core Ring

Block rings

Offset with respect to

The block
Block Aboundary

Core boundary
Block B

26
 Clock Tree Synthesis
• The clock topology is built at this stage and all the clock nets are
routed.
• Depending on the tool capability there are various clocking schemes
available
• Optimization is done to achieve balanced clock tree structure and
system timing.
• After builiding the Clock tree another iteration of placement.
• Key terms:
– Insertion Delay
– Skew
– Clock Topologies: H-Tree, Custom, Fish-bone etc
 Clock Tree Synthesis

Balancing the clock is the most challenging part at this stage.

 Routing
• Physical Implementation is completed at this step.
• Although we have already done power and clock routing till now, but
majority of routing is done at this stage.
• Here we route all signal nets and finish any power and clock routing
not completed earlier
• Macro Pin Tappings (If any) are done.
• Normally there are alternate Metal layers for Horizontal & Vertical
routing.(Say M1,M3,M5 Horizontal and M2,M4,M6 Vertical)
• Routing in A Hierarchical Design is broken up into two
– Global routing: Inter-block routing
– Local routing: Intra-block routing, i.e routing within a block

• Routing Is divided in 2 majors (in one module)

– Global Routing: Places the segments on approximately correct location
– Detail Routing: Final Legal routing
 Violations/Fixing

• DRC and LVS violations encountered are fixed at this stage

– Short, Spacing, Island, Notch, Hole, Power open, Off Grid

• Antenna Violations: Is fixed using Antenna Diodes

• Metal Density: Minimum and Maximum
• Noise Violations
• EM Violations
• Signoff quality timing is required, with all the DRCs being met
(capacitance, transition, fanout)

After all the Violations are fixed we can stream out the GDSII, SDF,
SPEF etc.
 RTL to GDSII Flow
Logical Library,
RTL, Design
Constraints

Global & Detail

Logical Synthesis Placement
Routing

Netlist, SDC,
Physical library

Clock Tree DRC/LVS/Antenna

Floor Plan Noise Fixes etc
Synthesis

GDSII, post-layout
netlist, SDF, SPEF

Power Planning Placement

& Routing Optimization

**STA is done at
all the stages
Thanks !!