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    VHDL Oral Questions

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    vk2you009
    - VHDL and Verilog are both commonly used languages for designing digital circuits, but they approach the task differently - VHDL is more exact and verbose, while Verilog is more terse and assumes the designer's intent. - VHDL is better suited for system-level modeling, while Verilog excels at gate-level simulation. There are also analog extensions for VHDL but analog synthesis is still limited. - For a VHDL design to be synthesizable, it must adhere to a small subset of the language and reflect the target technology's structure efficiently. Synthesis translates valid VHDL code into a netlist representation of the designed circuit.

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    VHDL Oral Questions

    Uploaded by

    vk2you009
    189 views1 page
    - VHDL and Verilog are both commonly used languages for designing digital circuits, but they approach the task differently - VHDL is more exact and verbose, while Verilog is more terse and assumes the designer's intent. - VHDL is better suited for system-level modeling, while Verilog excels at gate-level simulation. There are also analog extensions for VHDL but analog synthesis is still limited. - For a VHDL design to be synthesizable, it must adhere to a small subset of the language and reflect the target technology's structure efficiently. Synthesis translates valid VHDL code into a netlist representation of the designed circuit.

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    Vhdl Oral Questions

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    - VHDL and Verilog are both commonly used languages for designing digital circuits, but they approach the task differently - VHDL is more exact and verbose, while Verilog is more terse and assumes the designer's intent. - VHDL is better suited for system-level modeling, while Verilog excels at gate-level simulation. There are also analog extensions for VHDL but analog synthesis is still limited. - For a VHDL design to be synthesizable, it must adhere to a small subset of the language and reflect the target technology's structure efficiently. Synthesis translates valid VHDL code into a netlist representation of the designed circuit.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    189 views1 page

    VHDL Oral Questions

    Uploaded by

    vk2you009
    - VHDL and Verilog are both commonly used languages for designing digital circuits, but they approach the task differently - VHDL is more exact and verbose, while Verilog is more terse and assumes the designer's intent. - VHDL is better suited for system-level modeling, while Verilog excels at gate-level simulation. There are also analog extensions for VHDL but analog synthesis is still limited. - For a VHDL design to be synthesizable, it must adhere to a small subset of the language and reflect the target technology's structure efficiently. Synthesis translates valid VHDL code into a netlist representation of the designed circuit.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as DOCX, PDF, TXT or read online from Scribd
    Download as docx, pdf, or txt
    of 1

    What is the difference between VHDL and Verilog? Fundamentally speaking, not a lot.

    You can produce robust designs and comprehensive test environments with both langauges, for both ASIC and FPGA. However, the two langauges approach the task from different directions; VHDL, intended as a specification langauge, is very exact in its nature and hence very verbose. Verilog, intended as a simulation langauge, it much closer to C in style, in that it is terse and elegant to write but requires much more care to avoid nasty bugs. VHDL doesn't let you get away with much; Verilog assumes that whatever you wrote was exactly what you intended to write. If you get a VHDL architecture to compile, it's probably going to approximate to the function you wanted. For Verilog, successful compilation merely indicates that the syntax rules were met, nothing more. VHDL has some features that make it good for system-level modelling, whereas Verilog is much better than VHDL at gatelevel simulation. To confuse the situation more, see SystemVerilog... Can I use VHDL for the analog part of a design? Yes and No. Yes, there is a VHDL Analogue and Mixed Signal language (VHDL-AMS), based on VHDL 93, which allows modelling of both analogue and digital in the same language. You can see our 2 day VHDL-AMS workshop syllabus on our training page. However the idea of analogue synthesis is still in its early days, so currently you wouldn't normally be able to go on and synthesize an analogue model written in VHDL-AMS. There's a VHDL-AMS website at www.eda.org/vhdl-ams. How must I write VHDL to make it synthesisable? Because large parts of the language make no sense in a hardware context, synthesisable VHDL is a relatively small subset of VHDL. You must stick to this subset, and understand exactly how the synthesis tool you use interprets that code. For FPGA in particular you must also develop a good understanding of the structure of your chip, and know how your code must reflect the most efficient use of that structure. Fundamentally, never forget that you are designing a circuit, not writing a program. Forgetting this simply but important fact will only lead to pain later. How many versions of VHDL are there? There are four. The original release of the VHDL language occured in 1987 with the adoption of the Language Reference Manual as an IEEE standard. In 1993, the IEEE-1076 standard was modified and ratified and became known as VHDL'93. This is now widely supported. In 2000, the VHDL 1076 2000 Edition appeared - this fixed shared variables by introducing the idea of protected types. Finally, VHDL 1076-2002 appeared. This includes protected mode types, but also changes ports of mode buffer to make them more usable, along with some other small changes. In practise, VHDL 1076-1993 is the current flavour of VHDL which is widely supported by tool vendors. Are there any tools to generate VHDL test benches automatically? The basic answer is no. Writing a testbench can be a complex task, and can be more complex than the design being tested. If you mean "Can I get a code framework for a simple testbench", then a number of tools provide simple "testbench templates"; even the Emacs editor VHDL mode can do this! For more advanced ways of writing testbenches, you might want to look at the so-called "Testbench Automation" tools, such as SystemVerilog, SystemC Verification Library, Cadence Specman, and Synopys Vera. These tools involve learning another language of course. If you want to know how to write more complex testbenches (for instance to cope with data arriving in a different order from the order it entered a device), have a look at our Expert VHDL Verification course. What is Synthesis? Synthesis is the stage in the design flow which is concerned with translating your VHDL code into gates - and that's putting it very simply! First of all, the VHDL must be written in a particular way for the target technology that you are using. Of course, a synthesis tool doesn't actually produce gates - it will output a netlist of the design that you have synthesised that represents the chip which can be fabricated through an ASIC or FPGA vendor

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