LAB 0 | Introduction to Verilog + Icarus + GTKWave

Introduction
Verilog HDL is a Hardware Description Language (HDL). A Hardware Description Language is a
language used to describe a digital system, for example, a computer or a component of a computer.
One may describe a digital system at several levels. For example, an HDL might describe the layout
of the wires, resistors and transistors on an Integrated Circuit (IC) chip, i. e., the switch level. Or,
it might describe the logical gates and flip flops in a digital system, i. e., the gate level. An even
higher level describes the registers and the transfers of vectors of information between registers. This
is called the Register Transfer Level (RTL). Verilog supports all of these levels. However, this
handout focuses on only the portions of Verilog which support the RTL level.

What is Verilog?

Verilog is one of the two major Hardware Description Languages (HDL) used by hardware
designers in industry and academia. VHDL is the other one. The industry is currently split on which
is better. Many feel that Verilog is easier to learn and use than VHDL. As one hardware designer
puts it, "I hope the competition uses VHDL." VHDL was made an IEEE Standard in 1987, while
Verilog is still in the IEEE standardization process. Verilog is very C-like and liked by electrical and
computer engineers as most learn the C language in college. VHDL is very Ada-like and most
engineers have no experience with Ada.

Verilog was introduced in 1985 by Gateway Design System Corporation, now a part of Cadence
Design Systems, Inc.'s Systems Division. Until May, 1990, with the formation of Open Verilog
International (OVI), Verilog HDL was a proprietary language of Cadence. Cadence was motivated
to open the language to the Public Domain with the expectation that the market for Verilog HDL-
related software products would grow more rapidly with broader acceptance of the language.
Cadence realized that Verilog HDL users wanted other software and service companies to embrace
the language and develop Verilog-supported design tools.

Verilog HDL allows a hardware designer to describe designs at a high level of abstraction such as at
the architectural functional (behavioral) level as well as the lower implementation levels (gate and
TTL-switch levels) leading to Very Large-Scale Integration (VLSI) Integrated Circuits (IC) layouts
and chip fabrication. A primary use of HDLs is the simulation of designs before the designer must
commit to fabrication. This handout does not cover all of Verilog HDL but focuses on the use of
Verilog HDL at the architectural or behavioral levels. The handout emphasizes design at the Register
Transfer Level (RTL).

Why Use Verilog HDL?

Digital systems are highly complex. At their most detailed level, they may consist of millions of
elements, i. e., transistors or logic gates. Therefore, for large digital systems, gate-level design is
dead. For many decades, logic schematics served as the lingua franca of logic design, but not
anymore. Today, hardware complexity has grown to such a degree that a schematic with logic gates
 is almost useless as it shows only a web of connectivity and not the functionality of design. Since the
1970s, Computer engineers and electrical engineers have moved toward hardware description
languages (HDLs). The most prominent modern HDLs in industry are Verilog and VHDL. Verilog is
the top HDL used by over 10,000 designers at such hardware vendors as Sun Microsystems, Apple
Computer and Motorola. Industrial designers like Verilog. It works.

The Verilog language provides the digital designer with a means of describing a digital system at a
wide range of levels of abstraction, and, at the same time, provides access to computer-aided design
tools to aid in the design process at these levels.

Verilog allows hardware designers to express their design with behavioral constructs, deterring the
details of implementation to a later stage of design in the design. An abstract representation helps the
designer explore architectural alternatives through simulations and to detect design bottlenecks
before detailed design begins.

Though the behavioral level of Verilog is a high-level description of a digital system, it is still a
precise notation. Computer aided design tools, i. e., programs, exist which will "compile" programs
in the Verilog notation to the level of circuits consisting of logic gates and flip flops. One could then
go to the lab and wire up the logical circuits and have a functioning system. And, other tools can
"compile" programs in Verilog notation to a description of the integrated circuit masks for very
large-scale integration (VLSI). Therefore, with the proper automated tools, one can create a VLSI
description of a design in Verilog and send the VLSI description via electronic mail to a silicon
foundry in California and receive the integrated chip in a few weeks by way of snail mail. Verilog
also allows the designer to specific designs at the logical gate level using gate constructs and the
transistor level using switch constructs.

Our goal in the course is not to create VLSI chips but to use Verilog to precisely describe
the functionality of any digital system, for example, a computer. However, a VLSI chip designed by
way of Verilog's behavioral constructs will be rather slow and be wasteful of chip area. The lower
levels in Verilog allow engineers to optimize the logical circuits and VLSI layouts to maximize
speed and minimize area of the VLSI chip.

HDL logic simulator

Icarus Verilog, commonly known as iVerilog, is a Verilog HDL simulator and also a synthesis tool,
the current version of which provides full coverage of IEEE 1364-2001 and partially supports IEEE
1364-2005 standards. The tool can be utilized in two modes. One, as a simulator and second, as a
synthesis tool. When used as a simulator, the Verilog HDL code is compiled into an intermediate
form known as vvp assembly, which is then executed using the vvp command. The simulation
output is either written to a .vcd file or to the terminal depending on the directives in the testbench.
In the synthesis mode, the tool compiles the Verilog HDL code into a netlist of the preferred format.

Synthesis tools
Icarus Verilog used as synthesis tool converts the design into one of supported netlist formats
specified by the user. This can result in EDIF, XNF or VHDL among others. With its extensible
code generator, this tool can be modified to handle the synthesis of superconducting circuits.

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 The Verilog Language

We begin our study of the Verilog language by looking at a simple Verilog program. Looking at the
assignment statements, we notice that the language is very C-like. Comments have a C++ flavor, i e.,
they are shown by "//" to the end of the line. The Verilog language describes a digital system as a set
of modules, but here we have only a single module called "simple".

First Verilog Program

///////////////////// hello.v //////////////////////
// hello.v, "Hello World!" Verilog program
module hello; // define module to test run
initial #49 $finish; // program ends at cycle 50

always begin // loop

$display("Hello, World!"); // show msg
#10; // wait 10 cycles to continue loop
end
endmodule
///////////////////// end of hello.v //////////////////////

The runtime displays the following:

Hello, World!
Hello, World!
Hello, World!
Hello, World!
Hello, World!

Getting Started
Before getting started with actual examples, here are a few notes on conventions. First, command
lines and sequences take the same arguments on all supported operating environments, including
Linux, Windows and the various Unix systems. When an example command is shown in a figure,
the generic prompt character "% " takes the place of whatever prompt string is appropriate for your
system. Under Windows, the commands are invoked in a command window.
Second, when creating a file to hold Verilog code, it is common to use the ".v" or the ".vl" suffix.
This is not a requirement imposed by Icarus Verilog, but a useful convention. Some people also use
the suffixes ".ver" or even ".vlg". In this lab, will use the ".v" suffix.
So let us start. Given that you are going to use Icarus Verilog as part of your design process, the first
thing to do as a designer is learn how to compile and execute even the most trivial design. For the
purposes of simulation, we use as our example the most trivial simulation, a simple Hello,
World program above.

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 hello.v in a text editor

In the figure above, words in green are comments, blue are reserved words. Any program in Verilog
starts with reserved word 'module' <module_name>. In the above example line 4 contains module
hello. (Note: We can have compiler pre-processor statements like `include', `define' before module
declaration)

Line 5 contains the initial block: this block gets executed only once after the simulation starts, at
time=0 (0ns). This block contains two statements which are enclosed within begin, at line 7, and end,
at line 10. In Verilog, if you have multiple lines within a block, you need to use begin and end.
Module ends with 'endmodule' reserved word, in this case at line 11.

Use a text editor to place the program in a text file, hello.v, then compile this program with the
command:
% iverilog -o hello hello.v

The results of this compile are placed into the file "hello", because the "-o" flag tells the compiler
where to place the compiled result. Next, execute the compiled program like so:

% vvp hello
Hello, World
Hello, World
Hello, World
Hello, World
Hello, World

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 hello.v compiled and executed

And there it is, the program has been executed. So, what happened?
The first step, the "iverilog" command, read and interpreted the source file, then generated a
compiled result. The compiled form may be selected by command line switches, but the default is
the "vvp" format, which is actually run later, as needed. The "vvp" command of the second step
interpreted the "hello" file from the first step, causing the program to execute.

The "iverilog" and "vvp" commands are the most important commands available to users of Icarus
Verilog. The "iverilog" command is the compiler, and the "vvp" command is the simulation runtime
engine. What sort of output the compiler actually creates is controlled by command line switches,
but normally it produces output in the default vvp format, which is in turn executed by the vvp
program.

Second Verilog Program

Counter Design Block

Counter Design Specs

• 4-bit synchronous up counter.
• active high, synchronous reset.
• Active high enable.

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 //-----------------------------------------------------
// This is my second Verilog Design
// Design Name : first_counter
// File Name : first_counter.v
// Function : This is a 4 bit up-counter with
// Synchronous active high reset and
// with active high enable signal
//-----------------------------------------------------
module first_counter (
clock , // Clock input of the design
reset , // active high, synchronous Reset input
enable , // Active high enable signal for counter
counter_out // 4 bit vector output of the counter
); // End of port list
//-------------Input Ports-----------------------------
input clock ;
input reset ;
input enable ;
//-------------Output Ports----------------------------
output [3:0] counter_out ;
//-------------Input ports Data Type-------------------
// By rule all the input ports should be wires
wire clock ;
wire reset ;
wire enable ;
//-------------Output Ports Data Type------------------
// Output port can be a storage element (reg) or a wire
reg [3:0] counter_out ;

//------------Code Starts Here-------------------------

// Since this counter is a positive edge trigged one,
// We trigger the below block with respect to positive
// edge of the clock.
always @ (posedge clock)
begin : COUNTER // Block Name
// At every rising edge of clock we check if reset is active
// If active, we load the counter output with 4'b0000
if (reset == 1'b1) begin
counter_out <= #1 4'b0000;
end
// If enable is active, then we increment the counter
else if (enable == 1'b1) begin
counter_out <= #1 counter_out + 1;
end
end // End of Block COUNTER

endmodule // End of Module counter

Counter Test Bench

Any digital circuit, no matter how complex, needs to be tested. For the counter logic, we need to
provide clock and reset logic. Once the counter is out of reset, we toggle the enable input to the
counter, and check the waveform to see if the counter is counting correctly. This is done in Verilog.

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 Counter Testbench (left part)

The counter testbench consists of clock generator, reset control, enable control and monitor/checker
logic. Below is the simple code of testbench without the monitor/checker logic.

`include "first_counter.v"
module first_counter_tb();
// Declare inputs as regs and outputs as wires
reg clock, reset, enable;
wire [3:0] counter_out;

// Initialize all variables

initial begin
$display ("time\t clk reset enable counter");
$monitor ("%g\t %b %b %b %b",
$time, clock, reset, enable, counter_out);
clock = 1; // initial value of clock
reset = 0; // initial value of reset
enable = 0; // initial value of enable
#5 reset = 1; // Assert the reset
#10 reset = 0; // De-assert the reset
#10 enable = 1; // Assert enable
#100 enable = 0; // De-assert enable
#5 $finish; // Terminate simulation
end

// Clock generator
always begin
#5 clock = ~clock; // Toggle clock every 5 ticks
end

// Connect DUT to test bench

first_counter U_counter (
clock,
reset,
enable,
counter_out
);

endmodule

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 In this second Verilog program, we have seen that another Verilog file is created to test the former
Verilog file. We can compile either of this file. But the desired outputs we need to see can be found
in the later. To compile:

% iverilog first_counter_tb.v

The command above will create an a.out file which is necessary to perform the simulation of the
testbench. Simulation of the file through vvp command will out in the terminal the values in the
$display and $monitor line of the testbench code. To execute:

% vvp a.out

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 The following output will be generated in the terminal:

About GTKWave
GTKWAVE is VCD waveform viewer based on the GTK library. This viewer support VCD and
LXT formats for signal dumps.

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 Generating VCD/LXT files for GTKWAVE
Waveform dumps are written by the Icarus Verilog runtime program vvp. The user uses $dumpfile
and $dumpvars system tasks to enable waveform dumping, then the vvp runtime takes care of the
rest. The output is written into the file specified by the $dumpfile system task. If the $dumpfile call
is absent, the compiler will choose the file name dump.vcd or dump.lxt, depending on runtime
flags.The example below dumps everything in and below the test module.
Example:

// Do this in your test bench

initial
begin
$dumpfile("test.vcd");
$dumpvars(0,test);
end

By default, the vvp runtime will generate VCD dump output. This is the default because it is the
most portable. In line 9 of the testbench code, a dumpfile was set to be “file.vcd”. Hence, we can use
that file to view the waveform. This waveform can be viewed with the command:

% gtkwave file.vcd

As you can see, there aren't any waves in the Wave window. That's because the user has to choose
which signals he want to see. In order to choose the signal you want to see, you should go in the left
window with the SST name. Here you can see your hardware hierarchy. By clicking the + of every
instance (if there are any), you can see the signals that are related with that instance with the Type
and Signals columns below it.

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 Then you can drag & drop them, or copy & paste them in the Signals window. Or you can select the
signals then click Append button. Here are the waveforms.

Dragging the reset signal

Waveform with all the signals

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 In summary, here’s how you run the second example:

This activity should help you become familiar in coding Verilog files and compiling and simulating
them using Icarus Verilog and GTKWave.

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