Testplan Apb

TESTPLAN DOCUMENTATION
Version <1.0>
<02/21/2019>
2
VERSION HISTORY
Ver Implemented Revision Approved Approva Reason

sio By Date By l
n Date
#
1.0 Priya soni 01/04/2019 Priya <mm/dd/ Initial Documentation
ananthakrishnan yy> draft
3
1 INTRODUCTION
1.1 OBJECTIVE OF THE VERIFICATION PLAN DOCUMENT

The objective of the verification strategy described here in is to verify the functionality of
the APB slave. The main verification concerns for this unit are functional completeness
and correctness, data integrity, data coherency and performance. Testing will be structured
to check that all functions are using the right resources at the right time while many
complex scenarios are in progress. Numerous verification methods such as unit level
simulation, chip level simulation , designer simulation and gate level simulation can be
used.
No Formal Verification is planned for this unit
No System Simulation is planned for this unit
No Chip level Simulation planned for this unit
1.2 DESIGNER SIMULATION
1.3 UNIT SIMULATION
Unit level verification of these will be completed by the core team. System Verilog
simulation environments described below will be used for the simulation.
The primary simulation environment for the APB slave unit will be the system verilog
random constraint simulation environment at the chip level. This environment is being
developed from scratch to ensure high verification coverage and first-pass chip quality. The
scope of the testing in this environment is all mainline data flows, error detection, error
recovery
1.4 CHIP SIMULATION

1.5 FUNCTIONAL GATE LEVEL EVENT SIMULATION
Functional Gate Level event simulation will confirm correct chip integration of clock
control logic , reset and Asynchronous domain crossing. We can do it with and without
timing
1.6 VERIFICATION TOOLS
SYNOPSYS VCS - For Simulation , code coverage and functional coverage.
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2 VERIFICATION STRATEGY
2.1 ASSUMPTIONS / CONSTRAINTS / STANDARDS

1.Slave address locations will be 0 to 255
2.The testbench acts as a master and it will verify apb slave
3 TESTBENCH ARCHITECTURE
3.1 PACKET.TXT
The packet for APB protocol consists of:
rand bit [31:0] paddr;
rand bit [31:0] pwdata ;
bit [31:0] prdata;
bit pwrite;
bit psel;
bit penable;
bit prstn;
bit pclk;
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bit pready;
bit pslver;
constraint p1 { paddr < 256 }:slave address will be less than 256
3.2 TOP.SV
module top;
bit clk;
inter dut_if(clk);
slave d1 (.clk (dut_if.clk),……..) //instantiation of dut and interface
initial
begin
clk=0;
forever #5 clk=~clk; // clock generation
end
initial begin
uvm_config_db #(virtual inter)::set(null,"uvm_test_top","vif",dut_if);
run_test("apb_test"); //run base test
end
endmodule
3.3 APB_TEST
class counter_test extends uvm_test;
ùvm_component_utils (apb_test) //factory registration
apb_env env;
virtual inter vif;
APB_sequence seq;
virtual function void build_phase (uvm_phase phase);
////////////////////////////////////////////////////////////
create env instance
/////////////////////////////////////////////////////////////
endfunction
task run_phase( uvm_phase phase );
seq = counter_sequence::type_id::create("seq");
phase.raise_objection( this, "Starting sequence");
seq.start(m_top_env.cnt_agnt1.sequencer);
phase.drop_objection( this , "Finished sequence" );
endtask: run_phase
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virtual function void end_of_elaboration_phase (uvm_phase phase);

uvm_top.print_topology ();
endfunction
3.4 APB_ENV
it consists of two agents and a scoreboard
class apb_env extends uvm_env ;
ùvm_component_utils (apb_env)
apb_agent act_agnt1;
apb_agent pass_agnt2;// passive agent
apb_scoreboard m_scbd;
function void build_phase (uvm_phase phase);

super.build_phase (phase);
……………………………………………………………...
creates instance of two agents & a scoreboard
……………………………………………………………...
endfunction : build_phase
virtual function void connect_phase(uvm_phase phase);

super.connect_phase (phase);
………………………………………………………………….
monitors analysis ports are connected to scoreboard
…………………………………………………………………..
endfunction
3.3 APB_AGENT
class apb_agent extends uvm_agent;

it consists of apb driver sequencer monitor;
uvm_analysis_port #(apb_pkt) ap;

function void build_phase(uvm_phase phase);
super.build_phase(phase);
ap=new("ap",this); //creation of analysis port
if(get_is_active() == UVM_ACTIVE)
begin
//creates driver and sequencer
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end
//creates monitor
endfunction : build_phase
function void connect_phase(uvm_phase phase);

super.connect_phase(phase);
if(get_is_active() == UVM_ACTIVE) begin
…………………………………………………………………...
connect driver to sequencer
…………………………………………………………………..
endfunction : connect_phase
endclass
3.3 APB_SEQUENCER
The sequencer control the flow of request and response sequence items
between sequences and the driver.
class apb_sequencer extends uvm_sequencer#(counter_seq_item);

ùvm_sequencer_utils(apb_sequencer)
function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new
endclass : sequencer
3.3 APB_DRIVER
Three tasks
1. one for write: task write;
paddr <= addr;………...pwdata<=data……….pwrite<=1………..psel.<= '1;

@ ////next clock ……...penable<=1
@ ////next clock……….psel<=0……...penable<=0…….
endtask: drive_write
2. one for read: task read

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paddr <= addr……….pwrite<=0………..psel.<= '1;

@ ////next clock ……...penable<=1
@ ////next clock………data<=prdata………………...psel<=0……...penable<=0…….
endtask: drive_read
3. one for pready: task wait for pready

//////a wait task for pready /////////
3.4 APB_MONITOR.V
A Monitor is a functional block in a testbench, two monitors are used.
One for Captures the response at the output pins of the DUT & one Creates a packet out of
captured response information
class apb_monitor extends uvm_monitor;

ùvm_component_utils (apb_monitor)
uvm_analysis_port #(apb_pkt) mon_analysis_port;
virtual function void build_phase (uvm_phase phase);

super.build_phase (phase);
// Create an instance of the declared analysis port
endfunction
virtual task monitor_data();

/////////////////////////////////////////
endtask
virtual task run_phase (uvm_phase phase);

super.run_phase (phase);
forever begin
@(negedge vif.rst);
fork
monitor_data();
join_none
@(posedge vif.rst);
disable fork;
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end
endtask
endclass
3.5 APB_SCOREBOARD.V
 A Scoreboard is a functional block in the testbench that does the following: receives
response data from the monitor block
 Fetches expected results and compares with the response data received from the monitor
block
 Generates results and stores them for each test case. This aids in generating reports
Class apb_scoreboard extends uvm_scoreboard

ùvm_component_utils(counter_scoreboard)
//declare a queue
// Instantiate the analysis port, because afterall, its a class object
function void build_phase (uvm_phase phase);
super.build_phase(phase);
///////create instance of real and expected packet//////////
endfunction
virtual function void write_read (input counter_seq_item pkt1);
………..create expected packet…………………………………………..
exp_que.push_back(pkt);// write expected packet into a queue
…...compare real and expected packet……………………
……...generate report………………………………………….
endfunction :
3.6 ABP_SEQUENCE
A task is used to randomize the packet.txt
task body ();
abp_pkt pkt;
pkt = apb_pkt::type_id::create ("pkt");
repeat(5)
begin
start_item (pkt);
assert (pkt.randomize());
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finish_item(pkt);
end
endtask
3.6 FUNCTIONAL COVERAGE
prstn INPUT
pselx INPUT
penable INPUT
paddr INPUT
pwrite INPUT
pwdata INPUT
pclk INPUT
prdata OUTPUT
pslver OUTPUT
pready OUTPUT
3.7 CODE COVERAGE
Expecting a code coverage of 100 percent for the verification to be complete.

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TESTCASE SCENARIOS
NO Name of the testcase

1 Write with no wait Write transfer without wait
2 Write with wait Write transfer with wait
3 Read with no wait Read transfer without wait
4 Read with wait Read transfer with wait
5 Error packet Paddr >255 considered as error packet
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Appendix A: References
13
[Insert the name, version number, description, and physical location of any
documents referenced in this document. Add rows to the table as necessary.]
The following table summarizes the documents referenced in this document.
Document Description Location
Name and
Version
<Document [Provide description of the <URL or Network path where
Name and document] document is located>
Version
Number>
14
Appendix B: Key Terms

[Insert terms and definitions used in this document. Add rows to the table as
necessary.]
The following table provides definitions for terms relevant to this document.
Term Definition
[Insert Term] [Provide definition of the term used in this document.]

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TESTPLAN DOCUMENTATION

Ver Implemented Revision Approved Approva Reason

1.1 OBJECTIVE OF THE VERIFICATION PLAN DOCUMENT

1.4 CHIP SIMULATION

2.1 ASSUMPTIONS / CONSTRAINTS / STANDARDS

virtual function void end_of_elaboration_phase (uvm_phase phase);

function void build_phase (uvm_phase phase);

virtual function void connect_phase(uvm_phase phase);

class apb_agent extends uvm_agent;

uvm_analysis_port #(apb_pkt) ap;

function void connect_phase(uvm_phase phase);

class apb_sequencer extends uvm_sequencer#(counter_seq_item);

paddr <= addr;………...pwdata<=data……….pwrite<=1………..psel.<= '1;

2. one for read: task read

paddr <= addr……….pwrite<=0………..psel.<= '1;

3. one for pready: task wait for pready

class apb_monitor extends uvm_monitor;

virtual function void build_phase (uvm_phase phase);

virtual task monitor_data();

virtual task run_phase (uvm_phase phase);

Class apb_scoreboard extends uvm_scoreboard

3.7 CODE COVERAGE

Expecting a code coverage of 100 percent for the verification to be complete.

NO Name of the testcase

Appendix B: Key Terms

[Insert Term] [Provide definition of the term used in this document.]

[Insert Term] [Provide definition of the term used in this document.]

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