HDL LAb

OVERVIEW OF HDL LAB

HDL
In electronics, a hardware description language or HDL is any language from a class of

Computer languages for formal description of electronic circuits. It can describe the
circuit's operation, its design and organization, and tests to verify its operation by means of
simulation
HDLs are standard text-based expressions of the spatial, temporal structure and behavior of
electronic systems. In contrast to a software programming language, HDL syntax, semantics
include explicit notations for expressing time and concurrency, which are the attributes of
hardware. Languages whose only characteristic is to express circuit connectivity between a
hierarchies of blocks are properly classified as netlist languages.
HDLs are used to write executable specifications of some piece of hardware. A simulation
program, designed to implement the underlying semantics of the language statements,
coupled with simulating the progress of time, provides the hardware designer with the
ability to model a piece of hardware before it is created physically. It is this execute ability
that gives HDLs the illusion of being programming languages. Simulators capable of supporting
discrete-event and continuous-time (analog) modeling exist, and HDLs targeted for each are
available.
It is certainly possible to represent hardware semantics using traditional programming languages
such as C++, although to function such programs must be augmented with extensive and
unwieldy class libraries. Primarily, however, software programming languages function as a
hardware description language
Using the proper subset of virtually any language, a software program called a synthesizer
can infer hardware logic operations from the language statements and produce an equivalent
netlist of generic hardware primitives to implement the specified behavior. This typically
requires the synthesizer to ignore the expression of any timing constructs in the text.

The two most widely-used and well-supported HDL varieties used in industry are
 VHDL (VHSIC HDL)
 Verilog

Dept. of ECE_UVCE
HDL LAb
VHDL
VHDL (Very High Speed Integrated Circuit Hardware Description Language) is
commonly used as a design-entry language for field-programmable gate arrays and application-
specific integrated circuits in electronic design automation of digital circuits.
VHDL is a fairly general-purpose language, and it doesn’t require a simulator on which to run
the code. There are a lot of VHDL compilers, which build executable binaries. It can read and
write files on the host computer, so a VHDL program can be written that generates another
VHDL program to be incorporated in the design being developed. Because of this general-
purpose nature, it is possible to use VHDL to write a test bench that verifies with the user,
and compares results with those expected. This is similar to the capabilities of the Verilog
language
VHDL is not a case sensitive language. One can design hardware in a VHDL IDE (such as
Xilinx) to produce the RTL schematic of the desired circuit. After that, the generated schematic
can be verified using simulation software (such as ModelSim) which shows the waveforms of
inputs and outputs of the circuit after generating the appropriate test bench. To generate an
appropriate test bench for a particular circuit or VHDL code, the inputs have to be defined
correctly. For example, for clock input, a loop process or an iterative statement is required.
The key advantage of VHDL when used for systems design is that it allows the behavior of the
required system to be described (modeled) and verified (simulated) before synthesis tools
translate the design into real hardware (gates and wires). When a VHDL model is
translated into the "gates and wires" that are mapped onto a programmable logic device such
as a CPLD or FPGA, then it is the actual hardware being configured, rather than the
VHDL code being "executed" as if on some form of a processor chip.
Both VHDL and Verilog emerged as the dominant HDLs in the electronics industry while
older and less-capable HDLs gradually disappeared from use. But VHDL and Verilog share
many of the same limitations: neither HDL is suitable for analog/mixed-signal circuit
simulation. Neither possesses language constructs to describe recursively-generated logic
structures

Dept. of ECE_UVCE
HDL LAb
Verilog
Verilog is a hardware description language (HDL) used to model electronic systems. The
language supports the design, verification, and implementation of analog, digital, and mixed -
signal circuits at various levels of abstraction
The designers of Verilog wanted a language with syntax similar to the C programming
language so that it would be familiar to engineers and readily accepted. The language is case-
sensitive, has a preprocessor like C, and the major control flow keywords, such as "if"
and "while", are similar. The formatting mechanism in the printing routines and language
operators and their precedence are also similar
The language differs in some fundamental ways. Verilog uses Begin/End instead of curly braces
to define a block of code. The concept of time, so important to a HDL won't be found in C The
language differs from a conventional programming language in that the execution of statements
is not strictly sequential. A Verilog design consists of a hierarchy of modules are defined
with a set of input, output, and bidirectional ports. Internally, a module contains a list of wires
and registers. Concurrent and sequential statements define the behavior of the module by
defining the relationships between the ports, wires, and registers Sequential statements are
placed inside a begin/end block and executed in sequential order within the block. But all
concurrent statements and all begin/end blocks in the design are executed in parallel,
qualifying Verilog as a Dataflow language. A module can also contain one or more instances
of another module to define sub-behavior
A subset of statements in the language is synthesizable. If the modules in a design contains a
netlist that describes the basic components and connections to be implemented in hardware only
synthesizable statements, software can be used to transform or synthesize the design into the net
list may then be transformed into, for example, a form describing the standard cells of an
integrated circuit (e.g. ASIC) or a bit stream for a programmable logic device (e.g. FPGA).

Design using HDL

Dept. of ECE_UVCE
HDL LAb
The vast majority of modern digital circuit design revolves around an HDL
description of the desired circuit, device, or subsystem.
Most designs begin as a written set of requirements or a high-level architectural diagram.
The process of writing the HDL description is highly dependent on the designer's diagram.
The process of writing the HDL description is highly dependent on the designer's
background and the circuit's nature. The HDL is merely the 'capture language'–often begin
with a high-level algorithmic description such as MATLAB or a C++ mathematical model
Control and decision structures are often prototyped in flowchart applications, or entered in a
state-diagram editor. Designers even use scripting languages (such as PERL) to automatically
generate repetitive circuit structures in the HDL language. Advanced text editors (such as
PERL) to automatically generate repetitive circuit structures in the HDL language. Advanced
text editors (such as Emacs) offer editor templates for automatic indentation, syntax-
dependent coloration, and macro-based expansion of entity/architecture/signal declaration.
As the design's implementation is fleshed out, the HDL code invariably must undergo code
review, or auditing. In preparation for synthesis, the HDL description is subject to an array
of automated checkers. The checkers enforce standardized code guidelines, identifying
ambiguous code construct before they can cause misinterpretation by downstream synthesis, and
check for common logical coding errors, such as dangling ports or shorted outputs.
In industry parlance, HDL design generally ends at the synthesis stage. Once the synthesis
tool has mapped the HDL description into a gate net list, this net list is passed off to the back -
end stage. Depending on the physical technology (FPGA, ASIC gate-array, ASIC standard-
cell), HDLs may or may not play a significant role in the back-end flow. In general, as the
design flow progresses toward a physically realizable form, the design database becomes
progressively more laden with technology-specific information, which cannot be becomes
progressively more laden with technology-specific information, which cannot be stored in a
generic HDL-description. Finally, a silicon chip is manufactured.

Dept. of ECE_UVCE
HDL Programming using Xilinx ISE design suite

Xilinx ISE means Xilinx® Integrated Software Environment (ISE), i.e programmable logic
design tool in electronics industry. This Xilinx ® design software suite allows taking
design from design entry through Xilinx device programming. The ISE Project Navigator
manages and processes design through several steps in the ISE design flow. These steps are
Design Entry, Synthesis, Implementation, Simulation/Verification, and Device
Configuration. Xilinx is one of most popular software tool used to synthesize
VHDL/Verilog code.

INTRODUCTION TO FPGA (FIELD PROGRAMMABLE GATE ARRAY)

FPGA contains a two dimensional arrays of logic blocks and interconnections between
logic blocks. Both the logic blocks and interconnects are programmable. Logic blocks
are programmed to implement a desired function and the interconnects are programmed
using the switch boxes to connect the logic blocks.
To implement a complex design (CPU for instance), the design is divided into small sub
functions and each sub function is implemented using one logic block. All the sub
functions implemented in logic blocks must be connected and this is done by
programming the interconnects.

INTERNAL STRUCTURE OF AN FPGA

FPGAs, alternative to the custom ICs, can be used to implement an entire System On one
Chip (SOC). The main advantage of FPGA is ability to reprogram. User can reprogram
an FPGA to implement a design and this is done after the FPGA is manufactured. This
brings the name “Field Programmable.”
Custom ICs are expensive and takes long time to design so they are useful when
produced in bulk amounts. But FPGAs are easy to implement within a short time with
the help of Computer Aided Designing (CAD) tools.

XILINX FPGA

Xilinx logic block consists of one Look Up Table (LUT) and one Flip-flop. An LUT is
used to implement number of different functionality. The input lines to the logic block go
into the LUT and enable it. The output of the LUT gives the result of the logic function
that it implements and the output of logic block is registered or
unregistered output from the LUT.

4-INPUT LUT BASED IMPLEMENTATION OF LOGIC BLOCK.

Xilinx LUT

FPGA/ASIC DESIGN FLOW OVERVIEW

Part –A Software Experiments

Procedure :
1. Double click on Xilinx Design Suite 13.1 Icon.
2. Select new project in file menu.
3. Enter the project name and location as shown below and press Next .
4. Select the Family, Device, Package and speed as per the requirements and press Next .
5. Create a new source by using new source icon or right click on the device/project folder
to create new source.
6. Select the appropriate source type and enter the file name in New Source Wizard
window and press Next .
7. Enter the architecture name – dataflow/behavioral/structural, port name and select the
direction. This will create .v source file. Press Next and finish the initial project creation.
8. Write complete VHDL/Verilog code implementation and save.
9. Click on implementation and check for syntax using “Check syntax” option under
synthesize tab. If any error, edit and correct VHDL/Verilog code and repeat check syntax
until zero errors.
10. Double click on ISIM simulator by selecting simulation mode to complete the
functional simulation of your design.

Part –B Hardware Interfacing

Procedure :
1. Repeat the steps 1 to 10 from the procedure for software experiments .
2. Make the connection between appropriate FRC’s of the FPGA board and the DIP switch
connector of the GPIOcard-2/
3. Make the connection between appropriate FRC’s of the FPGA board and to the
connector of the GPIOcard-2.
4. Right click on the device and select “New Source”, Select the option “Implementation
constraint File” and provide the file name and click on next and then hit Finish. This
creates an .ucf file.
6. Double click on the added .ucf file and assign the pin numbers to inputs and outputs
referring to FRC sheet using the syntax as shown.Save the constraint file.
7. Connect USB programmer for FPGA between FPGA kit and USB port of your
computer.
8. Go to process window, select the VHDL or Verilog file and click on “configure target
device”.
9. Click OK for the warning below.
10. Select boundary scan to impact the target device.

11. Right click on the impact window to establish a connection between system and FPGA
by selecting “INTIALIZE CHAIN” option.
12. Both prom device and FPGA device gets identified after step 10 and bypass the
procedure to select only FPGA which of main interest.
13. Now choose device 2(FPGA XC3S400) and hit ok to complete the impact.
14. Now right click on the device to assign a new .bit file by selecting an option “ASSIGN
NEW CONFIGURATION FILE”.
15. Select the corresponding .bit file from the project folder and hit Open .
16. Press ‘No’ on the following dialog box.
17. Finally right click on the device(XC3S400) and implement the program by choosing an
option “PROGRAM”
18. Once again select the FPGA device (XC3S400) by clicking ok and now the program
will be identified and succeeded.
 PART –A
PROGRAMS

Experiment No 1
Realize all the logic gates Using Verilog code

Objective: -
To write and simulate the Verilog code to realize the basic logic gates and to check
the functionality by simulating the design .

Theory :-
Logic gates are the basic building blocks of any digital system. It is an
electronic circuit having one or more than one input and only one output. The relationship
between the input and the output is based on a certain logic. Based on this, logic gates are
named as AND gate, OR gate, NOT gate
Verilog Code:

1.a) Realizing AND gate:

module and_gate (a,b,y);
input a,b ; //defines two input port
output y; // defines one output port
and g1(y,a,b); /*gate declaration with predefined keyword or representing
logic OR, g1 is optional user defined gate identifier */
endmodule

Functional table:

Input Input Output

A B Y
0 0 0
0 1 0
1 0 0
 1 1 1

Simulation Results:-

1.b) Realizing OR gate:

Verilog Code :

//Verilog module for OR gate

module or_gate(a,b,y);
input a,b; //defines two input port
output y; // defines one output port
or g1(y,a,b); /*gate declaration with predefined keyword or representing
logic OR, g1 is optional user defined gate identifier */
endmodule

Functional table:
Input Input Output
A B Y
0 0 0
0 1 1
1 0 1
1 1 1
Simulation Results:-

1.c). Realizing XOR gate:

Verilog Code :
module xor_gate(y,a,b);
input a,b;
output y;
xor g1(y,a,b);
endmodule

Functional table:
Input Input Output
a b c
0 0 0
0 1 1
1 0 1
1 1 0

Simulation Results
1.d) NOT GATE:

architecture behavioral of not1 is

begin
c<=not a ;
end behavioral;

Verilog Code:
module not_gate(a,y);
input a;
output y;
not g1(y,a);
endmodule

Functional table:
Input Output
A c
0 1
1 0

Simulation Results
1. e) NAND GATE:

Verilog module for NAND gate

module nand_gate(a,b,y);
input a,b;
output y;
nand g1(y,a,b);
endmodule

Functional table:

Input Input Output

A B c
0 0 1
0 1 1
1 0 1
1 1 0

Simulation Results
1. f) NOR GATE :

Verilog Code :

module nor_gate(y,a,b);
input a,b;
output y;
nor g1(y,a,b);
endmodule

Functional table:

Input Input Output

A B c
0 0 0
0 1 0
1 0 0
1 1 1
Simulation Results
1.g) XNOR GATE:

Verilog Code :

module xnor_gate(y,a,b);
input a,b;
output y;
xnor g1(y,a,b);
endmodule

Functional table:
Input Input Output
A B c
0 0 1
0 1 0
1 0 0
1 1 1

Simulation Results
Verilog Code to Realize all Logic Gates :

Block Diagram
Verilog Code :
module gates(a_in, b_in,
not_op,and_op,nand_op,or_op,nor_op,xor_op,xnor_op);
input a_in,b_in;
output
not_op,and_op,nand_op,or_op,nor_op,xor_op,xnor_op;
assign not_op= ~a_in;
assign and_op=a_in&b_in;
assign nand_op=~(a_in&b_in);
assign or_op=a_in|b_in;
assign nor_op=~(a_in|b_in);
assign xor_op=a_in^b_in;
assign xnor_op=~(a_in^b_in);
endmodule

Results:-
Written and simulated the HDL model for Basic logic gates and verified the
response with the truth table and concluded that the basic logic gates design is
working fine.
Experiment No 2:

Realize the following combinational circuits using Verilog Code

(a). 2 to 4 decoder.
(b) 8to 3 encoder without priority &
(c) 8 to 3 (encoder with priority) .
(d) 8 to 1 Multipexer
(e) 4 bit binary to gray converter .
(f) Multiplexer, De-Multiplexer, Comparator
Objective: -

To write and simulate the HDL code to realize the Combinational gates and to
check the functionality by simulating the design ISE Simulator.

2 (a). 2 to 4 decoder:

Theory:

A decoder is a multiple input, multiple output logic circuit that converts coded inputs into
coded outputs where the input and output codes are different. The enable inputs must be
ON for the decoder to function, otherwise its outputs assumes a ‘disabled’ output code
word. Decoding is necessary in applications such as data multiplexing, seven segment
display and memory address decoding.

y(3)
a(0) 2:4 Decder
y(2)

y(1)
a(1)
y(0)
Verilog Code :

module decoder(a, y);

input [1:0] a;
output [3:0] y;
reg [3:0] y;
always @ (a)
case(a)
2’b00: y<= 4’b1110;
2’b01: y<= 4’b1101;
2’b10: y<= 4’b1011;
2’b11: y<= 4’b0111;
endcase
endmodule

Functional table:

Input : a Output :
(1downto 0) y(1downto 0)
00 1110
01 1101
10 1011
11 0111

Simulation Results:-
2.(b) 8 to 3 encoder without priority:

Theory: An Encoder is a combinational circuit that performs the reverse operation of

Decoder.It has maximum of 2^n input lines and 'n' output lines, hence it encodes the
information from 2^n inputs into an n-bit code. Encoders are used to translate rotary or
linear motion into a digital signal. The priority encoder is the binary representation of the
original number starting from zero of the most significant input bit. They are often used to
control interrupt requests by acting on the highest priority encoder. If two or more inputs
are given at the same time, the input having the highest priority will take precedence.

Verilog Code :

module encoder (din, dout);

input [7:0] din;
output [2:0] dout;
reg [2:0] dout;

always @(din)
begin
if (din ==8'b00000001) dout=3'b000;
else if (din==8'b00000010) dout=3'b001;
 else if (din==8'b00000100) dout=3'b010;
else if (din==8'b00001000) dout=3'b011;
else if (din==8'b00010000) dout=3'b100;
else if (din ==8'b00100000) dout=3'b101;
else if (din==8'b01000000) dout=3'b110;
else if (din==8'b10000000) dout=3'b111;
else dout=3'bX ;
end
endmodule

Functional table:

Enable din: input dout: output

(input) (7 downto 0); (2 downto 0)
0 xxxxxxxx zzz
1 00000001 000
1 00000010 001
1 00000100 010
1 00001000 011
1 00010000 100
1 00100000 101
1 01000000 110
1 Others 111
Simulation Results:-

2 (c). 8 to 3 priority encoder with priority

Verilog Code :

module encoder (din, dout);

 input [7:0] din;
output [2:0] dout;
reg [2:0] dout;

always @(din)
begin
if (din ==8'b00000001) dout=3'b000;
else if (din==8'b0000001 X) dout=3'b001;
else if (din==8'b000001 XX) dout=3'b010;
else if (din==8'b00001XXX) dout=3'b011;
else if (din==8'b0001XXXX) dout=3'b100;
else if (din ==8'b001XXXXX) dout=3'b101;
else if (din==8'b01XXXXXX) dout=3'b110;
else if (din==8'b1XXXXXXX) dout=3'b111;
else dout=3'bX;
end
endmodule

Functional table:

Enable (input) din: input (7 dout: out

downto 0); (2 downto 0)
1 xxxxxxxx zzz
0 00000001 000
0 0000001x 001
0 000001xx 010
0 00001xxx 011
0 0001xxxx 100
0 001xxxxx 101
0 01xxxxxx 110
0 Others 111

Simulation Results:-
2 (d) 8 to 1 Multiplexer

Theory : A multiplexer (or mux) is a device that selects between several analog or digital
input signals and forwards it to a single output line. A multiplexer is also called a data
selector. A multiplexer of inputs has select lines, which are used to select which input line
to send to the output.[2] Multiplexers are mainly used to increase the amount of data that
can be sent over the network within a certain amount of time and bandwidth.

Verilog Code :

module mux8_1(i_in, sel, y_out);

input [7:0] i;
input [2:0] sel;
output y_out;
reg y_out;
always@ (i_in,sel )
begin
case (sel) 3'b000:y_out=i_in[0];
3'b001: y_out=i_in[1];
3'b010: y_out=i_in[2];
3'b011: y_out=i_in[3];
3'b100: y_out=i_in[4];
 3'b101: y_out=i_in[5];
3'b110: y_out=i_in[6];
3'b111: y_out=i_in[7];
default: y_out =3'b000;
endcase
end
endmodule

Functional table:

sel y_out
000 a[0]
001 a[1]
010 a[2]
011 a[3]
100 a[4]
101 a[5]
110 a[6]
others a[7]

Simulation Results:-
2 (e). 4 bit binary to gray converter

Block Diagram

Theory :

The “Reflected binary code”, also known as Gray code after Frank Gray. In a Gray code
the adjacent numbers differ by one symbol. The original name reflected binary code is
derived from the fact that the second half of the values are equivalent to the first half in
reverse order, except for the highest bit, which is inverted.

Applications: Some sensors send information in Gray code. These must be converted to
binary in order to do arithmetic operations. Gray codes are widely used to facilitate error
correction in digital communications.

Verilog Code :

module bintogray(b_in, g_op);

input [3:0] b_in;
output [3:0] g_op;
assig_opn g_op[3]=b_in[3];
assig_opn g_op[2]=b_in[3] ^ b_in[2];
assig_opn g_op[1]=b_in[2] ^ b_in[1];
assig_opn g_op[0]=b_in[1] ^ b_in[0];
endmodule

Functional table:

Decimal Binary Gray

0 0000 0000
1 0001 0001
2 0010 0011
3 0011 0010
4 0100 0110
5 0101 0111
6 0110 0101
7 0111 0100
8 1000 1100
9 1001 1101
10 1010 1111
11 1011 1110
12 1100 1010
13 1101 1011
14 1110 1001
15 1111 1000
Simulation Results:-
2 (f). 8:1 Demultiplexer

Theory : A demultiplexer (or de mux) is a device taking a single input and selecting
signals of the output of the compatible mux, which is connected to the single input, and a
shared selection line. A multiplexer is often used with a complementary demultiplexer on
the receiving end

Demultiplexer

Verilog code :
module demux(a_in, sel, y_out);
input a_in;
input [2:0] sel;
output [7:0] y_out;
reg [7:0] y_out;
always @ (a_in or sel)
casele(sel)
2’b000: y_out(0)=a_in;
2’b001: y_out(1)=a_in;
2’b010: y_out(2)=a_in;
2’b011: y_out(3)=a_in;
2’b100: y_out(0)=a_in;
2’b101: y_out(1)=a_in;
2’b110: y_out(2)=a_in;
2’b111: y_out(3)=a_in;
endcase
endmodule

Functional Table:
a_in= 0/1
sel : (in) y_out (output)
00 y_out(0)
01 y_out(1)
 10 y_out(2)
11 y_out(3)

Simulation results:
2 (g) Comparator

Verilog Code :
module comparator(a_in, b_in, L_op,g_op,e_op);
input [3:0] a_in;
input [3:0] b_in;
output L_op;
output g_op;
output e_op;
reg L_op,g_op,e_op;
always @ (a_in,b_in)
begin
if (a_in<b_in)
L_op=1'b1;
else
L_op=1'b0;
if (a_in>b_in)
g_op=1'b1;
else
g_op=1'b0;
if (a_in==b_in)
e_op=1'b1;
else
e_op=1'b0;
end
endmodule

Functional Table:

a_in:input b_in:input e_op g_op L_op

(3downto0) (3downto0)
 1111 1100 0 1 0
1111 1111 1 0 0
0000 1111 0 0 1

Simulation Results:-
Experiment No 3:

Realize HDL and Verilog model for Full adder using three different modeling
styles.
Objective :
To write and simulate the HDL model for Full adder using three different modeling
styles

Theory :
Full adder is the basic combinational arithmetic block used in digital design the
purpose of this model is to take three inputs (input A, input B and carry in) and
provide the two outputs (sum and carryout).sum will be the arithmetic addition of
all the three inputs and the carryout will be the overflow of value in the sum.

Block Diagram :

Logical Expressions:
sum = a_in xor b_in xor c_in;
carry= (a_in.b_in) + (b_in.c_in)+(a_in.b_in);

Truth Table :
3 (a). Data Flow description

VHDL Code :

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fulladder is
port (a_in, b_in, c_in: in std_logic;
sum, carry: out std_logic);
end fulladder;
architecture dataflow of fulladder is
begin
sum <= a_in xor b_in xor c_in;
carry<= (a_in and b_in) or (b_in and c_in) or (a_in and
b_in);
end dataflow;

Verilog Code :

module fulladder(a_in, b_in, c_in, sum, carry);

input a_in, b_in,c_in;
output sum, carry;
assign sum = a_in^b_in^c_in;
assign carry = (a_in & b_in) | (b_in & c_in) | (a_in & c_in);
endmodule

3(b). Behavioral description

VHDL Code :

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity fulladder is
port (abc: in std_logic_vector(2 downto 0);
sum, carry: out std_logic);
end fulladder;
architecture behavioral of fulladder is
begin
process(abc)
begin
case (abc) is
when”000”=>sum<=’0’; carry<=’0’;
when”001”=>sum<=’1’; carry<=’0’;
when”010”=>sum<=’1’; carry<=’0’;
when”011”=>sum<=’0’; carry<=’1’;
when”100”=>sum<=’1’; carry<=’0’;
when”101”=>sum<=’0’; carry<=’1’;
when”110”=>sum<=’0’; carry<=’1’;
when”111”=>sum<=’1’; carry<=’1’;
when others=>null;
end case;

Verilog Code :

module fulladder(abc, sum, carry);

input [2:0] abc;
output sum,carry;
reg sum,carry;
always@(abc)
begin
case (abc)
3’b000:begin sum=1’b0; carry=1’b0;end
3’b001:begin sum=1’b1; carry=1’b0;end
3’b010:begin sum=1’b1; carry=1’b0;end
3’b011:begin sum=1’b0; carry=1’b1;end
3’b100:begin sum=1’b1; carry=1’b0end
3’b101:begin sum=1’b0; carry=1’b1;end
3’b110:begin sum=1’b0; carry=1’b1;end
3’b111:begin sum=1’b1; carry=1’b1;end
endcase
end
endmodule

3(c). Structural Description

Block diagram : (gate level description)

Verilog code

module fa(a_in, b_in, c_in, sum, carry);

input a_in, b_in, c_in;
output sum, carry;
wire s1, s2, s3;
xor x1 (s1, a_in, b_in);
and a1 (s2, a_in, b_in);
xor x2 (sum, s1, c_in);
and a2 (s2, s1, c_in);
or o1 (carry, s2, s3);
endmodule

Simulation Results:-

Experiment No 4:
Realize Verilog model for 32-bit ALU using the schematic diagram shown below
with input A [31:0] and B [31:0].
Objective: -
To write and simulate the 32-bit ALU considering the A [31:0] and B [31:0] as two
inputs and to check the functionality by simulating the design using Mentor
graphics Modelsim Simulator.

Theory: -
Arithmetic and Logic Unit (ALU) is the building unit in all the processor. it
performs all the arithmetic and logical operations by taking input.It can be
implemented by using some control inputs to realize all possible arithmetic and
logical operations in a single model a. This consists of the operations like

 Arithmetic operations:
 Addition
 Subtraction
 Multiplication
 Logical operations:
 AND
 OR
 NAND
 XOR
 NOT
Functional Table:

Opcode ALU Operation

0 A+B addition
1 A-B Subtraction
2 ~A A Invert
3 A*B multiplication
4 A AND B logical AND
5 A OR B logical OR
6 A NAND B logical NAND
7 A XOR B logical XOR

Verilog Code :

module alu(a, b, opcode, y);

input [31:0] a,b;
input [3:0] opcode;
output [31:0] y;
reg [31:0] y;
always @ (a or b or opcode)
begin
case (opcode )
4'b0000: y=a+b;
4'b0001: y=a-b;
4'b0010: y=~a;
4'b0011: y=a &b;
4'b0100: y=a | b;
4'b0101: y=~(a & b);
4'b0110: y=~(a | b);
4'b0111: y=a ^ b;
4'b1000: y=~(a ^ b);
4'b1001: y=a;
4'b1010: y=32'b00000000000000000000000000000000;
4'b1011: y=32'b11111111111111111111111111111111;
4'b1100: y=a+1;
4'b1101: y=a-1;
4'b1110: y=b+1;
4'b1111: y=b-1;
default: y=32'bX;
endcase
end
endmodule

Expected Response Table:

Input Opcode 0001 010 011 100 101 110 111

A=1,B=1 0000

Output Y 2 0 0 1 1 1 0 0

Simulation Results:-
Results:-
Written and simulated the HDL model for the 32-bit ALU and verified the
simulation results for functional correctness by comparing the .

Experiment No. 5:

Objective: - Develop and simulate the Verilog code for the following flip-flops SR,
JK, D,
 Theory: -
SR flip-flop: A SR flip-flop is the simplest possible memory element. The SR flip flop has
two inputs Set and Reset. The SR flip-flop is a basic building block for other flip-flops.

D flip-flop: This is a flip-flop with a delay (D) equal to exactly equal to one cycle of the
clock. The defect with SR FF is the indeterminate output when the data inputs at S and R
are 1. In order to avoid this the input to R is through an inverter from S so that the input to
R is always the complement of S and never same. The S input is redesignated as D.

JK flip-flop: The JK flip-flop is called a “universal flip flop” because the other flip flops
like D, SR, T can be derived from it. The “racing or race around condition” takes place in a
JK FF when J=1 and K=1 and clock=1.

T flip-flop: T stands for toggling. It is obtained from JK FF by tying both the inputs J and
K.

S-R flip-flop Truth table:

Block diagram :

Truth Table :

Verilog Code :
module sr_ff(sr, clk, rst, q, qb);
input [1:0]sr;
input rst, clk;
output q,qb;
reg q,qb;
always @ (posedge clk)
begin
if (rst==1)
begin
q=0;
qb=1;
end
else
case (sr)
2'b00: begin q=q; qb=qb; end
2'b01: begin q=0; qb=1; end
2'b10: begin q=1; qb=0; end
2'b11: begin q=1'bx; qb=1'bx; end
default:begin end
endcase
end
endmodule

Simulation Result of SR flip-flop:-

D Flip Flop :

Block diagram: Truth Table

Simulation Results:-

J-K flip-flop :

Block diagram : Truth table:

Verilog Code :
module jk_ff(j, k, clk, reset, q, qb);
input [1:0]jk;
input clk,rst;
output q, qb;
reg q, qb;
reg [22:0] div;
reg clkdiv;
always @ (posedge clk)
begin
div = div+1'b1;
clkdiv = div[22];
end
always @ (posedge clkdiv)
begin
if(rst==1)
begin
q=0;
qb=1;
end
else
case (jk)
2'b00: begin q=q; qb=qb; end
2'b01: begin q=0; qb=1; end
2'b10: begin q=1; qb=0; end
2'b11: begin q=~(q); qb=~(qb); end
default: begin end
endcase
end
endmodule

Simulation Result of JK flip-flop:-

T flip-flop :

Block diagram Truth Table :

Verilog Code :
module t_ff (t, clk, rst, q, qb);
input t, clk, rst;
output q, qb;
reg q,qb;
always @ (posedge clk)
begin
div = div+1'b1;
clkdiv = div[22];
end
always @ (posedge clkdiv)
begin
if (rst==1)
begin
q=0;
qb=1;
end
else
case ( t)
1’b0:begin q=q; qb=qb; end
1’b1:begin q=~(q); qb=~(qb); end
default: begin end
endcase
end
endmodule

Results:-
Developed the HDL code for flip flops SR,JK,D,T and simulated the designs and
verified the truth table of all the flip-flops with simulation Results.

Experiment No 6:

Objective: - Design and simulate the Verilog code for a 4-bit binary, BCD counters with
 Synchronous Reset
 Asynchronous Reset
 Any sequence
Theory: -
 Basically the counters are the sequential blocks where in we use to generate a
sequence of numbers with respect to the clock counts which is a control signal provided for
the design. Counter can count and store the number of time any particular event or process
have occurred, depending on a clock signal. Counters can be modeled of synchronous or
Asynchronous types based on the clock applied for the design to execute the logic,
Asynchronous counters are those whose output is free from the clock signal. Because the
flip flops in asynchronous counters are supplied with different clock signals, there may be
delay in producing output . Counters can start counting not only from the zero, In fact it can
be initiated to any random value to make a count from some non-zero number and it is also
possible to increment the counter with more than one in one clock period.

6 (a). 4-bit Binary counter with Synchronous Reset

Block diagram :

Verilog Code :
module syncnt(clk, rst, bin_out)
input clk, rst;
output [3:0] bin_out;
reg [3:0] bin_out;
always @ (posedge clk)
begin
if(rst) begin
bin_out<=4‘b0;
end
else
bin_out<=bin_out +1;
end
endmodule
Simulation Results:-
6 (b). 4 - bit Binary Counter with Asynchronous reset :

Block diagram:

Verilog Code :
module asyncnt(clk, rst, bin_out);
input clk, rst;
output [3:0] bin_out;
reg [3:0] bin_out;
always @ (posedge clk or posedge rst)
begin
if(rst) begin
bin_out<=4'b0;
end
else
bin_out<=bin_out+1;
end
endmodule

Simulation Results:-
6 (c). 4-bit BCD counter with Synchronous reset :

Block diagram :

clk
bcd_out
Synchronous reset
counter
rst

Verilog Code :

module syncnt_bcd(clk, rst, bcd_out);

input clk, rst;
output [3:0] bcd_out;
reg [3:0] temp;
assign bcd_out=temp;
always @ (posedge clk)
begin
if(rst)
begin
temp<=4'b0000;
end
else
begin
temp<=temp+1'b1;
if(temp==4'b1001)
temp<=4'b0000;
end
end
endmodule

Simulation Results

6 (d). 4-bit BCD counter with Asynchronous reset :

Block diagram :

Verilog Code :
module Asyncnt_bcd(clk, rst, bcd_out);
input clk, rst;
output [3:0] bcd_out;
reg [3:0] temp;
assign bcd_out=temp;
always @ (posedge clk or posedge rst)
begin
if(rst)
begin
temp<=4'b0000;
end
else
begin
temp<=temp+1'b1;
if(temp==4'b1001)
temp<=4'b0000;
end
end
endmodule

Simulation Results :

Result: - Designed and simulated the HDL code for a 4-bit binary, BCD counters with
Synchronous Reset, Asynchronous Reset and and verified the simulation Results for the
counting sequence and the Synchronous and Asynchronous counting.