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    Introduction To HDL: Shaikh Khaled Mostaque Assistant Professor Eee Ru

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    Introduction To HDL: Shaikh Khaled Mostaque Assistant Professor Eee Ru

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    Rubaya
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    VHDL

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    29 views12 pages

    Introduction To HDL: Shaikh Khaled Mostaque Assistant Professor Eee Ru

    Uploaded by

    Rubaya

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    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Download as pptx, pdf, or txt
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    INTRODUCTION TO

    HDL
    SHAIKH KHALED MOSTAQUE
    ASSISTANT PROFESSOR
    EEE RU
    HDL
    • Specialized computer language used to describe the structure and
    behavior of electronic circuits, more commonly digital circuits.
    • It enables a precise, formal description of an electronic circuit
    that allows for the automated analysis and simulation of an
    electronic circuit.
    • It also allows for the synthesis of a HDL description into
    a netlist (a specification of physical electronic components and
    how they are connected together), which can then be placed and
    routed to produce the set of masks used to create an integrate
    circuit.
    Source: Wiki
    EXAMPLES OF HDL

    •  Two IEEE standards in common use in industry and


    academia are :

    • Verilog®-HDL and
    • VHDL : VHSIC Hardware Description Language
    HDL MODELING CAPACITY:
    VERILOG VS VHDL
    LOW LEVEL MODELING:
    VERILOG
    • In terms of low-level hardware modeling, Verilog is better than VHDL.
    • It is reasonable because Verilog is originally created for modeling and
    simulating logic gates. In fact, Verilog has built-in primitives or low-
    level logic gates so that designers can instantiate the primitives in
    Verilog code while VHDL does not have it.
    • Verilog's gate primitives: and, nand, or, nor, xor, xnor, buf, not, bufif0,
    notif0, bufif1, notif1, pullup, pulldown.
    • Verilog's switch primitives: pmos, nmos, rpmos, rnmos, cmos, rcmos,
    tran, rtran, tranif0, rtranif0, tranif1, rtranif1.
    • More importantly, Verilog supports User-Defined Primitives (UDP) so
    that designers can define their own cell primitives. This feature is
    especially necessary and popular for ASICs designers.
    https://www.fpga4student.com/2017/08/verilog-vs-vhdl-explain-by-example.html
    CODE
    HIGH-LEVEL MODELING: VHDL

    • User-Defined Data types in VHDL


    • VHDL supports many different data types including predefined
    VHDL data types and User-Defined data types
    • users cannot define their own data types in Verilog
    • Package for Design Reuse in VHDL
    • Packages in VHDL are commonly used for data types and
    subprograms' declaration. 
    • There is no package definition in Verilog. The closest Verilog
    equivalent to VHDL package is `include Verilog compiler
    directive. Functions or definitions can be separately saved in
    another file and then use it in a module by
    using `include directive.
    HIGH-LEVEL MODELING: VHDL
    • Configuration Statement in VHDL
    • A VHDL design can obtain many design entities with different architectures
    for one entity. Configuration statements associate the exact design entity to a
    component instance in a design. When there is more than one architecture in
    an entity, configuration statements continue to specify the desired design
    architecture is assigned to the entity for synthesis or simulation. This feature is
    very helpful when VHDL designers need to manage a large high-level design. 

    • Library Management in VHDL


    • When looking at Verilog and VHDL code at the same time, the most obvious
    difference is Verilog does not have library management while VHDL does
    include design libraries on the top of the code. VHDL libraries contain
    compiled architectures, entities, packages, and configurations. This feature is
    very useful when managing large design structures.
    VERBOSENESS: VERILOG VS
    VHDL
    • VHDL is strongly typed vs Verilog is loosely typed

    Verilog Compiler will not introduce syntax errors when you assign
    4-bit signal to 8-bit signal. In Verilog, signals with different bits
    width can be assigned to each other. Verilog compiler will adapt the
    width of the source signal to the width of the destination signal.
    Unused bits will be optimized during synthesis.
    OTHER DIFFERENCES
    • VHDL: complex data types VERILOG: simple data types
    • Verilog is like C programming language, while VHDL is like Ada or Pascal
    programming language
    • Verilog is case-sensitive while VHDL is not. It means that DAta1 and Data1
    are two different signals in Verilog, but both are the same signals in VHDL.
    • In Verilog, to use a component instance in a module, you just need to
    instantiate it in the module with a correct port map. In VHDL, before
    instantiating the instance, the component generally needs to be declared the
    architecture or in a package if you use the old instantiation statement as the
    following example. In VHDL-93, you can instantiate the entity directly like
    this: "Label_name: entity work.component_name port map (port list);".

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