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    Introduction To Cmos Vlsi Design: Design For Low Power

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    Rarun Arun
    This document summarizes techniques for low power design in CMOS VLSI circuits. It discusses reducing dynamic power by lowering activity factors through clock gating and sleep modes, reducing load capacitances with smaller transistors and shorter wires, lowering supply voltages, and reducing operating frequencies. It also discusses reducing static power by selectively using ratioed circuits, low threshold voltage devices, and leakage reduction techniques like stacked transistors, body biasing, and low temperature operation.

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    Introduction To Cmos Vlsi Design: Design For Low Power

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    Rarun Arun
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    This document summarizes techniques for low power design in CMOS VLSI circuits. It discusses reducing dynamic power by lowering activity factors through clock gating and sleep modes, reducing load capacitances with smaller transistors and shorter wires, lowering supply voltages, and reducing operating frequencies. It also discusses reducing static power by selectively using ratioed circuits, low threshold voltage devices, and leakage reduction techniques like stacked transistors, body biasing, and low temperature operation.

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    This document summarizes techniques for low power design in CMOS VLSI circuits. It discusses reducing dynamic power by lowering activity factors through clock gating and sleep modes, reducing load capacitances with smaller transistors and shorter wires, lowering supply voltages, and reducing operating frequencies. It also discusses reducing static power by selectively using ratioed circuits, low threshold voltage devices, and leakage reduction techniques like stacked transistors, body biasing, and low temperature operation.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    16 views24 pages

    Introduction To Cmos Vlsi Design: Design For Low Power

    Uploaded by

    Rarun Arun
    This document summarizes techniques for low power design in CMOS VLSI circuits. It discusses reducing dynamic power by lowering activity factors through clock gating and sleep modes, reducing load capacitances with smaller transistors and shorter wires, lowering supply voltages, and reducing operating frequencies. It also discusses reducing static power by selectively using ratioed circuits, low threshold voltage devices, and leakage reduction techniques like stacked transistors, body biasing, and low temperature operation.

    Copyright:

    Attribution Non-Commercial (BY-NC)
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 24

    Introduction to

    CMOS VLSI
    Design

    Lecture 18:
    Design for Low Power
    Credits: David Harris
    Harvey Mudd College

    (Material taken/adapted from


    Harris’ lecture notes)
    Outline
     Power and Energy
     Dynamic Power
     Static Power
     Low Power Design

    18: Design for Low Power CMOS VLSI Design Slide 2


    Power and Energy
     Power is drawn from a voltage source attached to
    the VDD pin(s) of a chip.

     Instantaneous Power: P(t )  iDD (t )VDD


    T T
     Energy: E   P (t )dt   iDD (t )VDD dt
    0 0
    T
     Average Power: E 1
    Pavg    iDD (t )VDD dt
    T T 0

    18: Design for Low Power CMOS VLSI Design Slide 3


    Dynamic Power
     Dynamic power is required to charge and discharge
    load capacitances when transistors switch.

     One cycle involves a rising and falling output.


     On rising output, charge Q = CVDD is required
     On falling output, charge is dumped to GND
     This repeats Tfsw times VDD
    iDD(t)
    over an interval of T

    C
    fsw

    18: Design for Low Power CMOS VLSI Design Slide 4


    Dynamic Power Cont.

    Pdynamic 

    VDD
    iDD(t)

    C
    fsw

    18: Design for Low Power CMOS VLSI Design Slide 5


    Dynamic Power Cont.
    T
    1
    Pdynamic   iDD (t )VDD dt
    T 0
    T
    VDD

    T 0 iDD (t )dt

    VDD
      TfswCVDD  VDD
    T iDD(t)
     CVDD 2 f sw
    C
    fsw

    18: Design for Low Power CMOS VLSI Design Slide 6


    Activity Factor
     Suppose the system clock frequency = f
     Let fsw = f, where  = activity factor
    – If the signal is a clock,  = 1
    – If the signal switches once per cycle,  = ½
    – Dynamic gates:
    • Switch either 0 or 2 times per cycle,  = ½
    – Static gates:
    • Depends on design, but typically  = 0.1

     Dynamic power: Pdynamic   CVDD 2 f

    18: Design for Low Power CMOS VLSI Design Slide 7


    Short Circuit Current
     When transistors switch, both nMOS and pMOS
    networks may be momentarily ON at once
     Leads to a blip of “short circuit” current.
     < 10% of dynamic power if rise/fall times are
    comparable for input and output

    18: Design for Low Power CMOS VLSI Design Slide 8


    Example
     200 Mtransistor chip
    – 20M logic transistors
    • Average width: 12 
    – 180M memory transistors
    • Average width: 4 
    – 1.2 V 100 nm process
    – Cg = 2 fF/m

    18: Design for Low Power CMOS VLSI Design Slide 9


    Dynamic Example
     Static CMOS logic gates: activity factor = 0.1
     Memory arrays: activity factor = 0.05 (many banks!)

     Estimate dynamic power consumption per MHz.


    Neglect wire capacitance and short-circuit current.

    18: Design for Low Power CMOS VLSI Design Slide 10


    Dynamic Example
     Static CMOS logic gates: activity factor = 0.1
     Memory arrays: activity factor = 0.05 (many banks!)

     Estimate dynamic power consumption per MHz.


    Neglect wire capacitance.

    Clogic   20  106   12   0.05 m /    2 fF /  m   24nF


    Cmem   180  106   4   0.05 m /    2 fF /  m   72nF
    Pdynamic  0.1Clogic  0.05Cmem   1.2  f  8.6 mW/MHz
    2

    18: Design for Low Power CMOS VLSI Design Slide 11


    Static Power
     Static power is consumed even when chip is
    quiescent.
    – Ratioed circuits burn power in fight between ON
    transistors
    – Leakage draws power from nominally OFF
    devices
    Vgs Vt
     Vds

    I ds  I ds 0e nvT
    1  e 
    vT

     

    Vt  Vt 0  Vds    s  Vsb  s 
    18: Design for Low Power CMOS VLSI Design Slide 12
    Ratio Example
     The chip contains a 32 word x 48 bit ROM
    – Uses pseudo-nMOS decoder and bitline pullups
    – On average, one wordline and 24 bitlines are high
     Find static power drawn by the ROM
    –  = 75 A/V2
    – Vtp = -0.4V

    18: Design for Low Power CMOS VLSI Design Slide 13


    Ratio Example
     The chip contains a 32 word x 48 bit ROM
    – Uses pseudo-nMOS decoder and bitline pullups
    – On average, one wordline and 24 bitlines are high
     Find static power drawn by the ROM
    –  = 75 A/V2
    – Vtp = -0.4V
     VDD  Vtp 
    2
     Solution:
    I pull-up    24μA
    2
    Ppull-up  VDD I pull-up  29μW
    Pstatic  (31  24) Ppull-up  1.6 mW

    18: Design for Low Power CMOS VLSI Design Slide 14


    Leakage Example
     The process has two threshold voltages and two
    oxide thicknesses.
     Subthreshold leakage:
    – 20 nA/m for low Vt
    – 0.02 nA/m for high Vt
     Gate leakage:
    – 3 nA/m for thin oxide
    – 0.002 nA/m for thick oxide
     Memories use low-leakage transistors everywhere
     Gates use low-leakage transistors on 80% of logic

    18: Design for Low Power CMOS VLSI Design Slide 15


    Leakage Example Cont.
     Estimate static power:

    18: Design for Low Power CMOS VLSI Design Slide 16


    Leakage Example Cont.
     Estimate static power:
    – High leakage:  20  106   0.2   12   0.05m /    2.4  10 6  m
    – Low leakage:  20  106   0.8  12   0.05m /   
     180  106   4   0.05m /    45.6  106 m
    I static   2.4  106  m   20nA / m  / 2   3nA / m   

     45.6  10 m   0.02nA / m  / 2   0.002nA / m  


    6

     32mA
    Pstatic  I staticVDD  38mW

    18: Design for Low Power CMOS VLSI Design Slide 17


    Leakage Example Cont.
     Estimate static power:
    – High leakage:  20  106   0.2   12   0.05m /    2.4  10 6  m
    – Low leakage:  20  106   0.8  12   0.05m /   
     180  106   4   0.05m /    45.6  106 m
    I static   2.4  106  m   20nA / m  / 2   3nA / m   

     45.6  10 m   0.02nA / m  / 2   0.002nA / m  


    6

     32mA
    Pstatic  I staticVDD  38mW

     If no low leakage devices, Pstatic = 749 mW (!)

    18: Design for Low Power CMOS VLSI Design Slide 18


    Low Power Design
     Reduce dynamic power
    – :
    – C:
    – VDD:
    – f:
     Reduce static power

    18: Design for Low Power CMOS VLSI Design Slide 19


    Low Power Design
     Reduce dynamic power
    – : clock gating, sleep mode
    – C:
    – VDD:
    – f:
     Reduce static power

    18: Design for Low Power CMOS VLSI Design Slide 20


    Low Power Design
     Reduce dynamic power
    – : clock gating, sleep mode
    – C: small transistors (esp. on clock), short wires
    – VDD:
    – f:
     Reduce static power

    18: Design for Low Power CMOS VLSI Design Slide 21


    Low Power Design
     Reduce dynamic power
    – : clock gating, sleep mode
    – C: small transistors (esp. on clock), short wires
    – VDD: lowest suitable voltage
    – f:
     Reduce static power

    18: Design for Low Power CMOS VLSI Design Slide 22


    Low Power Design
     Reduce dynamic power
    – : clock gating, sleep mode
    – C: small transistors (esp. on clock), short wires
    – VDD: lowest suitable voltage
    – f: lowest suitable frequency
     Reduce static power

    18: Design for Low Power CMOS VLSI Design Slide 23


    Low Power Design
     Reduce dynamic power
    – : clock gating, sleep mode
    – C: small transistors (esp. on clock), short wires
    – VDD: lowest suitable voltage
    – f: lowest suitable frequency
     Reduce static power
    – Selectively use ratioed circuits
    – Selectively use low Vt devices
    – Leakage reduction:
    stacked devices, body bias, low temperature
    18: Design for Low Power CMOS VLSI Design Slide 24

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