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    Lec 18 Low Power

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    Rahul Panwar
    The document discusses power consumption in CMOS VLSI circuits. It describes dynamic power, which is required to charge and discharge capacitances during transistor switching, and static power, which is consumed even when the chip is idle. Dynamic power can be reduced by lowering the activity factor, capacitance, supply voltage, and frequency. Static power can be reduced by selectively using ratioed circuits, low threshold voltage devices, and techniques like stacked transistors and body biasing. Low power design aims to minimize both dynamic and static power consumption.

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    © All Rights Reserved
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    Lec 18 Low Power

    Uploaded by

    Rahul Panwar
    93 views24 pages
    The document discusses power consumption in CMOS VLSI circuits. It describes dynamic power, which is required to charge and discharge capacitances during transistor switching, and static power, which is consumed even when the chip is idle. Dynamic power can be reduced by lowering the activity factor, capacitance, supply voltage, and frequency. Static power can be reduced by selectively using ratioed circuits, low threshold voltage devices, and techniques like stacked transistors and body biasing. Low power design aims to minimize both dynamic and static power consumption.

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    low power vlsi circuits

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    The document discusses power consumption in CMOS VLSI circuits. It describes dynamic power, which is required to charge and discharge capacitances during transistor switching, and static power, which is consumed even when the chip is idle. Dynamic power can be reduced by lowering the activity factor, capacitance, supply voltage, and frequency. Static power can be reduced by selectively using ratioed circuits, low threshold voltage devices, and techniques like stacked transistors and body biasing. Low power design aims to minimize both dynamic and static power consumption.

    Copyright:

    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    93 views24 pages

    Lec 18 Low Power

    Uploaded by

    Rahul Panwar
    The document discusses power consumption in CMOS VLSI circuits. It describes dynamic power, which is required to charge and discharge capacitances during transistor switching, and static power, which is consumed even when the chip is idle. Dynamic power can be reduced by lowering the activity factor, capacitance, supply voltage, and frequency. Static power can be reduced by selectively using ratioed circuits, low threshold voltage devices, and techniques like stacked transistors and body biasing. Low power design aims to minimize both dynamic and static power consumption.

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    © All Rights Reserved
    Download as PPT, PDF, TXT or read online from Scribd
    Download as ppt, pdf, or txt
    of 24

    Introduction to

    CMOS VLSI
    Design


    Design for Low Power
    CMOS VLSI Design Design for Low Power Slide 2
    Outline
    Power and Energy
    Dynamic Power
    Static Power
    Low Power Design
    CMOS VLSI Design Design for Low Power Slide 3
    Power and Energy
    Power is drawn from a voltage source attached to
    the V
    DD
    pin(s) of a chip.

    Instantaneous Power:

    Energy:

    Average Power:

    ( ) ( )
    DD DD
    P t i t V =
    0 0
    ( ) ( )
    T T
    DD DD
    E P t dt i t V dt = =
    } }
    avg
    0
    1
    ( )
    T
    DD DD
    E
    P i t V dt
    T T
    = =
    }
    CMOS VLSI Design Design for Low Power Slide 4
    Dynamic Power
    Dynamic power is required to charge and discharge
    load capacitances when transistors switch.

    One cycle involves a rising and falling output.
    On rising output, charge Q = CV
    DD
    is required
    On falling output, charge is dumped to GND
    This repeats Tf
    sw
    times
    over an interval of T
    C
    f
    sw
    i
    DD
    (t)
    VDD
    CMOS VLSI Design Design for Low Power Slide 5
    Dynamic Power Cont.
    C
    f
    sw
    i
    DD
    (t)
    VDD
    dynamic
    P =
    CMOS VLSI Design Design for Low Power Slide 6
    Dynamic Power Cont.
    C
    f
    sw
    i
    DD
    (t)
    VDD
    | |
    dynamic
    0
    0
    sw
    2
    sw
    1
    ( )
    ( )
    T
    DD DD
    T
    DD
    DD
    DD
    DD
    DD
    P i t V dt
    T
    V
    i t dt
    T
    V
    Tf CV
    T
    CV f
    =
    =
    =
    =
    }
    }
    CMOS VLSI Design Design for Low Power Slide 7
    Activity Factor
    Suppose the system clock frequency = f
    Let f
    sw
    = of, where o = activity factor
    If the signal is a clock, o = 1
    If the signal switches once per cycle, o =
    Dynamic gates:
    Switch either 0 or 2 times per cycle, o =
    Static gates:
    Depends on design, but typically o = 0.1

    Dynamic power:
    2
    dynamic DD
    P CV f o =
    CMOS VLSI Design Design for Low Power Slide 8
    Short Circuit Current
    When transistors switch, both nMOS and pMOS
    networks may be momentarily ON at once
    Leads to a blip of short circuit current.
    < 10% of dynamic power if rise/fall times are
    comparable for input and output
    CMOS VLSI Design Design for Low Power Slide 9
    Example
    200 Mtransistor chip
    20M logic transistors
    Average width: 12
    180M memory transistors
    Average width: 4
    1.2 V 100 nm process
    C
    g
    = 2 fF/m
    CMOS VLSI Design Design for Low Power Slide 10
    Dynamic Example
    Static CMOS logic gates: activity factor = 0.1
    Memory arrays: activity factor = 0.05 (many banks!)

    Estimate dynamic power consumption per MHz.
    Neglect wire capacitance and short-circuit current.


    CMOS VLSI Design Design for Low Power Slide 11
    Dynamic Example
    Static CMOS logic gates: activity factor = 0.1
    Memory arrays: activity factor = 0.05 (many banks!)

    Estimate dynamic power consumption per MHz.
    Neglect wire capacitance.

    ( )
    ( ) ( ) ( )
    ( )
    ( ) ( ) ( )
    ( )
    6
    logic
    6
    mem
    2
    dynamic logic mem
    20 10 12 0.05 / 2 / 24
    180 10 4 0.05 / 2 / 72
    0.1 0.05 1.2 8.6 mW/MHz
    C m fF m nF
    C m fF m nF
    P C C f


    = =
    = =
    ( = + =

    CMOS VLSI Design Design for Low Power Slide 12
    Static Power
    Static power is consumed even when chip is
    quiescent.
    Ratioed circuits burn power in fight between ON
    transistors
    Leakage draws power from nominally OFF
    devices
    0
    1
    gs t
    ds
    T T
    V V
    V
    nv v
    ds ds
    I I e e


    (
    =
    (
    (

    ( )
    0 t t ds s sb s
    V V V V q | | = + +
    CMOS VLSI Design Design for Low Power Slide 13
    Ratio Example
    The chip contains a 32 word x 48 bit ROM
    Uses pseudo-nMOS decoder and bitline pullups
    On average, one wordline and 24 bitlines are high
    Find static power drawn by the ROM
    | = 75 A/V
    2
    V
    tp
    = -0.4V
    CMOS VLSI Design Design for Low Power Slide 14
    Ratio Example
    The chip contains a 32 word x 48 bit ROM
    Uses pseudo-nMOS decoder and bitline pullups
    On average, one wordline and 24 bitlines are high
    Find static power drawn by the ROM
    | = 75 A/V
    2
    V
    tp
    = -0.4V
    Solution:

    ( )
    2
    pull-up
    pull-up pull-up
    static pull-up
    24A
    2
    29W
    (31 24) 1.6 mW
    DD tp
    DD
    V V
    I
    P V I
    P P
    |

    = =
    = =
    = + =
    CMOS VLSI Design Design for Low Power Slide 15
    Leakage Example
    The process has two threshold voltages and two
    oxide thicknesses.
    Subthreshold leakage:
    20 nA/m for low V
    t
    0.02 nA/m for high V
    t
    Gate leakage:
    3 nA/m for thin oxide
    0.002 nA/m for thick oxide
    Memories use low-leakage transistors everywhere
    Gates use low-leakage transistors on 80% of logic
    CMOS VLSI Design Design for Low Power Slide 16
    Leakage Example Cont.
    Estimate static power:
    CMOS VLSI Design Design for Low Power Slide 17
    Leakage Example Cont.
    Estimate static power:
    High leakage:
    Low leakage:






    ( )
    ( )( )( )
    6 6
    20 10 0.2 12 0.05 / 2.4 10 m m =
    ( )( ) ( ) ( )
    ( )( ) ( )
    6
    6 6
    20 10 0.8 12 0.05 /
    180 10 4 0.05 / 45.6 10
    m
    m m


    +
    =
    ( )
    ( ) ( )
    ( )
    ( ) ( )
    6
    6
    2.4 10 20 / / 2 3 /
    45.6 10 0.02 / / 2 0.002 /
    32
    38
    static
    static static DD
    I m nA m nA m
    m nA m nA m
    mA
    P I V mW


    = + + (

    + (

    =
    = =
    CMOS VLSI Design Design for Low Power Slide 18
    Leakage Example Cont.
    Estimate static power:
    High leakage:
    Low leakage:






    If no low leakage devices, P
    static
    = 749 mW (!)
    ( )
    ( )( )( )
    6 6
    20 10 0.2 12 0.05 / 2.4 10 m m =
    ( )( ) ( ) ( )
    ( )( ) ( )
    6
    6 6
    20 10 0.8 12 0.05 /
    180 10 4 0.05 / 45.6 10
    m
    m m


    +
    =
    ( )
    ( ) ( )
    ( )
    ( ) ( )
    6
    6
    2.4 10 20 / / 2 3 /
    45.6 10 0.02 / / 2 0.002 /
    32
    38
    static
    static static DD
    I m nA m nA m
    m nA m nA m
    mA
    P I V mW


    = + + (

    + (

    =
    = =
    CMOS VLSI Design Design for Low Power Slide 19
    Low Power Design
    Reduce dynamic power
    o:
    C:
    V
    DD
    :
    f:
    Reduce static power
    CMOS VLSI Design Design for Low Power Slide 20
    Low Power Design
    Reduce dynamic power
    o: clock gating, sleep mode
    C:
    V
    DD
    :
    f:
    Reduce static power
    CMOS VLSI Design Design for Low Power Slide 21
    Low Power Design
    Reduce dynamic power
    o: clock gating, sleep mode
    C: small transistors (esp. on clock), short wires
    V
    DD
    :
    f:
    Reduce static power
    CMOS VLSI Design Design for Low Power Slide 22
    Low Power Design
    Reduce dynamic power
    o: clock gating, sleep mode
    C: small transistors (esp. on clock), short wires
    V
    DD
    : lowest suitable voltage
    f:
    Reduce static power
    CMOS VLSI Design Design for Low Power Slide 23
    Low Power Design
    Reduce dynamic power
    o: clock gating, sleep mode
    C: small transistors (esp. on clock), short wires
    V
    DD
    : lowest suitable voltage
    f: lowest suitable frequency
    Reduce static power
    CMOS VLSI Design Design for Low Power Slide 24
    Low Power Design
    Reduce dynamic power
    o: clock gating, sleep mode
    C: small transistors (esp. on clock), short wires
    V
    DD
    : lowest suitable voltage
    f: lowest suitable frequency
    Reduce static power
    Selectively use ratioed circuits
    Selectively use low V
    t
    devices
    Leakage reduction:
    stacked devices, body bias, low temperature

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