Introduction To Cmos Vlsi Design: Nonideal Transistors

Introduction to
CMOS VLSI
Design
Lecture 15:
Nonideal Transistors
David Harris
Harvey Mudd College

Spring 2004
Outline
Transistor I-V Review
Nonideal Transistor Behavior
Velocity Saturation
Channel Length Modulation
Body Effect
Leakage
Temperature Sensitivity
Process and Environmental Variations
Process Corners
15: Nonideal Transistors
CMOS VLSI Design
Slide 2
Ideal Transistor I-V

Shockley 1st order transistor models

V
I ds Vgs Vt ds
2
Vgs Vt
2
Vgs Vt
V V V
ds
ds
dsat
Vds Vdsat
CMOS VLSI Design
cutoff
linear
saturation
Slide 3
Ideal nMOS I-V Plot

180 nm TSMC process
Ideal Models
= 155(W/L) mA/V2
Vt = 0.4 V
VDD = 1.8 V
Ids (mA)
400
Vgs = 1.8
300
Vgs = 1.5
200
Vgs = 1.2
100
Vgs = 0.9
Vgs = 0.6
0
0.3
CMOS VLSI Design
0.6
0.9
1.2
1.5
1.8
Vds
Slide 4
Simulated nMOS I-V Plot

180 nm TSMC process
BSIM 3v3 SPICE models
I
What differs?
ds
(mA)
250
Vgs = 1.8
200
Vgs = 1.5
150
Vgs = 1.2
100
Vgs = 0.9
50
Vgs = 0.6
0
0
0.3
0.6
0.9
1.2
1.5
Vds
CMOS VLSI Design
Slide 5
Simulated nMOS I-V Plot

180 nm TSMC process
BSIM 3v3 SPICE models
I (mA)
What differs?
250
Less ON current
200
No square law
150
Current increases
100
in saturation
ds
Vgs = 1.8
Vgs = 1.5
Vgs = 1.2
Vgs = 0.9
50
Vgs = 0.6
0
0
0.3
0.6
0.9
1.2
1.5
Vds
CMOS VLSI Design
Slide 6
Velocity Saturation
We assumed carrier velocity is proportional to E-field
v = mElat = mVds/L
At high fields, this ceases to be true
Carriers scatter off atoms
n
n
Velocity reaches vsat
Electrons: 6-10 x 106 cm/s
n /2
Holes: 4-8 x 106 cm/s
Better model
slope = m
sat
sat
Elat
v
vsat Esat
Elat
1
Esat
CMOS VLSI Design
0
0
Esat
2Esat
3Esat
Elat
Slide 7
Vel Sat I-V Effects

Ideal transistor ON current increases with VDD2
2
W Vgs Vt
I ds mCox
Vgs Vt
L
2
2
2
Velocity-saturated ON current increases with VDD

I ds CoxW Vgs Vt vmax
Real transistors are partially velocity saturated

Approximate with a-power law model
Ids VDDa
1 < a < 2 determined empirically
CMOS VLSI Design
Slide 8
a-Power Model
0
I ds I dsat ds
Vdsat
I dsat
Vgs Vt
cutoff
Vds Vdsat
linear
Vds Vdsat
saturation
I dsat Pc
Vt
gs
Vdsat Pv Vgs Vt
a /2
Simulated
a-law
Shockley
Ids (mA)
400
300
Vgs = 1.8
200
Vgs = 1.5
100
Vgs = 1.2
Vgs = 0.9
Vgs = 0.6
0
0.3
0.6
0.9
1.2
1.5
CMOS VLSI Design
1.8 V
ds
Slide 9
Channel Length Modulation

Reverse-biased p-n junctions form a depletion region
Region between n and p with no carriers
Width of depletion Ld region grows with reverse bias
V
V
GND
Source
Gate
Drain
Leff = L Ld
Depletion Region
Width: L
Shorter Leff gives more current
Ids increases with Vds
L
n+
n+
L
Even in saturation
p GND bulk Si
DD
DD
eff
CMOS VLSI Design
Slide 10
Chan Length Mod I-V

I ds
Ids (mA)
gs
Vt 1 lVds
2
400
Vgs = 1.8
300
Vgs = 1.5
200
Vgs = 1.2
100
0
0
Vgs = 0.9
Vgs = 0.6
0.3
0.6
0.9
1.2
1.5
1.8 Vds
l = channel length modulation coefficient

not feature size
Empirically fit to I-V characteristics
CMOS VLSI Design
Slide 11
Body Effect
Vt: gate voltage necessary to invert channel
Increases if source voltage increases because
source is connected to the channel
Increase in Vt with Vs is called the body effect
CMOS VLSI Design
Slide 12
Body Effect Model

Vt Vt 0 g
fs Vsb fs
fs = surface potential at threshold

fs 2vT ln
NA
ni
Depends on doping level NA

And intrinsic carrier concentration ni
g = body effect coefficient
g
tox
ox
2q si N A
2q si N A
Cox
CMOS VLSI Design
Slide 13
OFF Transistor Behavior

What about current in cutoff?
I
Simulated results
1 mA
What differs?
Sub100 mA
threshold
Current doesnt go 10 mA Region
1 mA
to 0 in cutoff
100 nA
ds
10 nA
Saturation
Region
Vds = 1.8
Subthreshold
Slope
1 nA
100 pA
10 pA
Vt
0
0.3
0.6
0.9
1.2
1.5
1.8
Vgs
CMOS VLSI Design
Slide 14
Leakage Sources
Subthreshold conduction
Transistors cant abruptly turn ON or OFF
Junction leakage
Reverse-biased PN junction diode current
Gate leakage
Tunneling through ultrathin gate dielectric
Subthreshold leakage is the biggest source in
modern transistors
CMOS VLSI Design
Slide 15
Subthreshold Leakage
Subthreshold leakage exponential with Vgs
Vgs Vt
I ds I ds 0e
nvT
Vds
v
1 e T
I ds 0 vT2 e1.8
n is process dependent, typically 1.4-1.5
CMOS VLSI Design
Slide 16
DIBL
Drain-Induced Barrier Lowering
Drain voltage also affect Vt
Vt Vt hVds
ttds
VVVh
High drain voltage causes subthreshold leakage

to ________.
CMOS VLSI Design
Slide 17
DIBL
Drain-Induced Barrier Lowering
Drain voltage also affect Vt
Vt Vt hVds
ttds
VVVh
High drain voltage causes subthreshold leakage

to increase.
CMOS VLSI Design
Slide 18
Junction Leakage
Reverse-biased p-n junctions have some leakage
VvD
T
I D I S e 1
Is depends on doping levels

And area and perimeter of diffusion regions
Typically < 1 fA/mm2
p+
n+
n+
p+
p+
n+
n well
p substrate
CMOS VLSI Design
Slide 19
Gate Leakage
Carriers may tunnel thorough very thin gate oxides
Predicted tunneling current (from [Song01])
109
tox
VDD trend
0.6 nm
0.8 nm
JG (A/cm )
106
103
1.0 nm
1.2 nm
100
1.5 nm
1.9 nm
10-3
10-6
10-9
0
Negligible for older processes

May soon be critically important
CMOS VLSI Design
0.3
0.6
0.9
1.2
1.5
1.8
VDD
Slide 20
Increasing temperature
Reduces mobility
Reduces Vt
ION ___________ with temperature
IOFF ___________ with temperature
CMOS VLSI Design
Slide 21
Increasing temperature
Reduces mobility
Reduces Vt
ION decreases with temperature
IOFF increases with temperature
I ds
increasing
temperature
Vgs
CMOS VLSI Design
Slide 22
So What?
So what if transistors are not ideal?
They still behave like switches.
But these effects matter for
Supply voltage choice
Logical effort
Quiescent power consumption
Pass transistors
Temperature of operation
CMOS VLSI Design
Slide 23
Parameter Variation
fast
Transistors have uncertainty in parameters

Process: Leff, Vt, tox of nMOS and pMOS
Vary around typical (T) values
Fast (F)
Leff: ______
Vt: ______
tox: ______
Slow (S): opposite
nMOS
Not all parameters are independent
for nMOS and pMOS
FF
pMOS
SF
TT
slow
slow
CMOS VLSI Design
FS
SS
fast
Slide 24
Parameter Variation
fast
Transistors have uncertainty in parameters

Process: Leff, Vt, tox of nMOS and pMOS
Vary around typical (T) values
Fast (F)
Leff: short
Vt: low
tox: thin
Slow (S): opposite
nMOS
Not all parameters are independent
for nMOS and pMOS
FF
pMOS
SF
TT
slow
slow
CMOS VLSI Design
FS
SS
fast
Slide 25
Environmental Variation
VDD and T also vary in time and space
Fast:
VDD: ____
T: ____
Corner
Voltage
Temperature
1.8
70 C
F
T
S
CMOS VLSI Design
Slide 26
Environmental Variation
VDD and T also vary in time and space
Fast:
VDD: high
T: low
Corner
Voltage
Temperature
1.98
0C
1.8
70 C
1.62
125 C
CMOS VLSI Design
Slide 27
Process Corners
Process corners describe worst case variations
If a design works in all corners, it will probably
work for any variation.
Describe corner with four letters (T, F, S)
nMOS speed
pMOS speed
Voltage
Temperature
CMOS VLSI Design
Slide 28
Important Corners
Some critical simulation corners include
Purpose
nMOS
pMOS
VDD
Temp
Cycle time
Power
Subthrehold
leakage
Pseudo-nMOS
CMOS VLSI Design
Slide 29
Important Corners
Some critical simulation corners include
Purpose
nMOS
pMOS
VDD
Temp
Cycle time
Power
Subthrehold
leakage
Pseudo-nMOS S
CMOS VLSI Design
Slide 30

Introduction To Cmos Vlsi Design: Nonideal Transistors

Uploaded by

Copyright:

Available Formats

Introduction To Cmos Vlsi Design: Nonideal Transistors

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Introduction To Cmos Vlsi Design: Nonideal Transistors

Uploaded by

Copyright:

Available Formats

Introduction to

Harvey Mudd College

15: Nonideal Transistors

CMOS VLSI Design

Ideal Transistor I-V

CMOS VLSI Design

Ideal nMOS I-V Plot

15: Nonideal Transistors

CMOS VLSI Design

Simulated nMOS I-V Plot

15: Nonideal Transistors

CMOS VLSI Design

Simulated nMOS I-V Plot

15: Nonideal Transistors

CMOS VLSI Design

15: Nonideal Transistors

CMOS VLSI Design

Vel Sat I-V Effects

Velocity-saturated ON current increases with VDD

Real transistors are partially velocity saturated

CMOS VLSI Design

15: Nonideal Transistors

CMOS VLSI Design

Channel Length Modulation

15: Nonideal Transistors

CMOS VLSI Design

Chan Length Mod I-V

l = channel length modulation coefficient

CMOS VLSI Design

15: Nonideal Transistors

CMOS VLSI Design

Body Effect Model

fs = surface potential at threshold

Depends on doping level NA

15: Nonideal Transistors

CMOS VLSI Design

OFF Transistor Behavior

15: Nonideal Transistors

CMOS VLSI Design

15: Nonideal Transistors

CMOS VLSI Design

n is process dependent, typically 1.4-1.5

15: Nonideal Transistors

CMOS VLSI Design

High drain voltage causes subthreshold leakage

15: Nonideal Transistors

CMOS VLSI Design

High drain voltage causes subthreshold leakage

15: Nonideal Transistors

CMOS VLSI Design

Is depends on doping levels

15: Nonideal Transistors

CMOS VLSI Design

Negligible for older processes

CMOS VLSI Design

15: Nonideal Transistors

CMOS VLSI Design

15: Nonideal Transistors