Lecture 7:

Power
 Outline
 Power and Energy
 Dynamic Power
 Static Power

7: Power CMOS VLSI Design 4th Ed. 2

 Power and Energy
 Power is drawn from a voltage source attached to
the VDD pin(s) of a chip.

 Instantaneous Power: P(t )  I (t )V (t )

T
 Energy: E   P(t )dt
0
T
 Average Power: E 1
Pavg    P(t )dt
T T 0

7: Power CMOS VLSI Design 4th Ed. 3

 Power in Circuit Elements
PVDD  t   I DD  t  VDD

VR2  t 
PR  t    I R2  t  R
R

 
dV
EC   I  t V  t  dt   C V  t  dt
0 0
dt
VC

 C  V  t dV  12 CVC2
0

7: Power CMOS VLSI Design 4th Ed. 4

 Charging a Capacitor
 When the gate output rises
– Energy stored in capacitor is
EC  12 CLVDD
2

– But energy drawn from the supply is

 
dV
EVDD   I  t VDD dt   CL VDD dt
0 0
dt
VDD

 CLVDD  dV  C V
2
L DD
0

– Half the energy from VDD is dissipated in the pMOS

transistor as heat, other half stored in capacitor
 When the gate output falls
– Energy in capacitor is dumped to GND
– Dissipated as heat in the nMOS transistor

7: Power CMOS VLSI Design 4th Ed. 5

 Switching Waveforms
 Example: VDD = 1.0 V, CL = 150 fF, f = 1 GHz

7: Power CMOS VLSI Design 4th Ed. 6

 Switching Power
T
1
Pswitching   iDD (t )VDD dt
T 0
T
VDD

T 0 iDD (t )dt

VDD
 Tfsw CVDD  VDD
T iDD(t)
fsw

 CVDD 2 f sw
C

7: Power CMOS VLSI Design 4th Ed. 7

 Activity Factor
 Suppose the system clock frequency = f
 Let fsw = af, where a = activity factor
– If the signal is a clock, a = 1
– If the signal switches once per cycle, a = ½

 Dynamic power:
Pswitching  a CVDD 2 f

7: Power CMOS VLSI Design 4th Ed. 8

 Short Circuit Current
 When transistors switch, both nMOS and pMOS
networks may be momentarily ON at once
 Leads to a blip of “short circuit” current.
 < 10% of dynamic power if rise/fall times are
comparable for input and output
 We will generally ignore this component

7: Power CMOS VLSI Design 4th Ed. 9

Power Dissipation Sources
 Ptotal = Pdynamic + Pstatic
 Dynamic power: Pdynamic = Pswitching + Pshortcircuit
– Switching load capacitances
– Short-circuit current
 Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD
– Subthreshold leakage
– Gate leakage
– Junction leakage
– Contention current

7: Power CMOS VLSI Design 4th Ed. 10

 Dynamic Power
 Consists of mainly switching power, short circuit
power is neglected.
 To calculate dynamic power given VDD and f,
consider the capacitance of each node of the circuit
including gate, diffusion, and wire capacitances.
 The effective capacitance is the true capacitance
multiplied by the node activity factor.
 The switching power depends on the sum of the
effective capacitances of all nodes.
 Activity factor is task-dependent.
 Low-power  minimize the power equation terms
7: Power CMOS VLSI Design 4th Ed. 11
Dynamic Power Example
 1 billion transistor chip
– 50M logic transistors
• Average width: 12 l
• Activity factor = 0.1
– 950M memory transistors
• Average width: 4 l
• Activity factor = 0.02
– 1.0 V 65 nm process
– C = 1 fF/mm (gate) + 0.8 fF/mm (diffusion)
 Estimate dynamic power consumption @ 1 GHz.
Neglect wire capacitance and short-circuit current.

7: Power CMOS VLSI Design 4th Ed. 12

 Solution
Clogic   50 106  12l  0.025m m / l 1.8 fF / m m   27 nF
Cmem   950 106   4l  0.025m m / l 1.8 fF / m m   171 nF

Pdynamic  0.1Clogic  0.02Cmem  1.0  1.0 GHz   6.1 W

2

7: Power CMOS VLSI Design 4th Ed. 13

 Dynamic Power Reduction

P
 switching  a CV 2
DD f

 Try to minimize:
– Activity factor
– Capacitance
– Supply voltage
– Frequency

7: Power CMOS VLSI Design 4th Ed. 14

 Activity Factor Estimation
 Let Pi = Prob(node i = 1)
– Pi = 1-Pi
 ai = Pi * Pi
 Completely random data has P = 0.5 and a = 0.25
 Data is often not completely random
– e.g. upper bits of 64-bit words representing bank
account balances are usually 0
 Data propagating through ANDs and ORs has lower
activity factor
– Depends on design, but typically a ≈ 0.1

7: Power CMOS VLSI Design 4th Ed. 15

 Switching Probability

7: Power CMOS VLSI Design 4th Ed. 16

 Example
 A 4-input AND is built out of two levels of gates
 Estimate the activity factor at each node if the inputs
have P = 0.5
 Construct the truth table and calculate the
probabilities

7: Power CMOS VLSI Design 4th Ed. 17

 Clock Gating
 The best way to reduce the activity is to turn off the
clock to registers in unused blocks
– Saves clock activity (a = 1)
– Eliminates all switching activity in the block
– Requires determining if block will be used

7: Power CMOS VLSI Design 4th Ed. 18

 Glitches
 gates sometimes make
spurious transitions called
glitches when inputs do not
arrive simultaneously
 The glitches cause extra
power dissipation
 Chains of gates are
particularly prone to this
problem
 Glitching can raise the activity
factor of a gate above 1

7: Power CMOS VLSI Design 4th Ed. 19

 Capacitance
 Gate capacitance
– Fewer stages of logic
– Small gate sizes
– Large gates with higher activity factors can be
downsized to reduce power (at the expense of
increasing logical effort and delay)
 Wire capacitance
– Good floorplanning to keep communicating
blocks close to each other
– Drive long wires with inverters or buffers rather
than complex gates
7: Power CMOS VLSI Design 4th Ed. 20
 Gate Sizing Under a Delay Constraint

 To compute energy in a circuit, consider:

– a unit inverter has gate capacitance 3C,
– a gate with logical effort g, parasitic delay p, and
drive x has gx times as much gate capacitance
and px times as much diffusion capacitance.
– The energy of the entire circuit is the sum of the
energies of each gate:

7: Power CMOS VLSI Design 4th Ed. 21

 Gate Sizing Under a Delay Constraint (2)

 By normalizing the equation:

 The problem is formulated as an optimization

problem to minimize E such that the worst-case
arrival time is less than some delay D.
 The problem is still a posynomial and has a unique
solution that can be found quickly by a good
optimizer.
7: Power CMOS VLSI Design 4th Ed. 22
 Example

 Generate an energy-delay trade-off curve for the

following circuit as delay varies from the minimum
possible (Dmin = 23.44 𝜏 to 50 𝜏). Assume that the
input probabilities are 0.5.

7: Power CMOS VLSI Design 4th Ed. 23

 Solution
 The Energy of the circuit is:

 The energy-delay trade-off

curve obtained by an automatic
Solver is depicted
 The delay cannot be minimized
unless the input inverter size is
increased

7: Power CMOS VLSI Design 4th Ed. 24

 Voltage Domains
 Run each block at the lowest possible voltage and
frequency that meets performance requirements
 Voltage Domains
– Provide separate supplies to
different blocks
– Level converters required when
crossing from low to high VDD domains
– Voltage domains are associated with a large area
of the floorplan
 Clustered Voltage Scaling (CVS) is an alternative
approach to use two supply voltages in the same
block with some constraints
7: Power CMOS VLSI Design 4th Ed. 25
 Dynamic Voltage Scaling
 Dynamic Voltage Scaling (DVS)
– Adjust VDD and f according to
workload
 DVFS
– reducing the clock frequency
to the minimum per task
– reducing the supply voltage
to the minimum necessary to
operate at that frequency

7: Power CMOS VLSI Design 4th Ed. 26

 Short-Circuit Current
 While the input switches, both pullup and pulldown
networks are partially ON causing short-circuit
current.
 It increases as the input edge rates become slower
because both networks are ON for more time, and
decreases as load capacitance increases.
 short-circuit current is a small fraction (< 10%) of
current to the load and can be ignored for sharp
input edges.
 Short-circuit power is strongly sensitive to the ratio v
= Vt / VDD, for v=0.5 short circuit current is zero.

7: Power CMOS VLSI Design 4th Ed. 27

 Static Power
 Static CMOS gates have no contention current
 Static power is consumed even when chip is
quiescent.
– Leakage draws power from nominally OFF
devices
– Ratioed circuits burn power in flight between ON
transistors

7: Power CMOS VLSI Design 4th Ed. 28

 Subthreshold Leakage
 For Vds > 50 mV Typical values in 65 nm
Vgs h Vds VDD   kg Vsb Ioff = 100 nA/mm @ Vt = 0.3 V
Ioff = 10 nA/mm @ Vt = 0.4 V
I sub  I off 10 S
Ioff = 1 nA/mm @ Vt = 0.5 V
h = 0.1
 Ioff = leakage at Vgs = 0, Vds = VDD
kg = 0.1
h: the DIBL coefficient S = 100 mV/decade
Kg: The body effect coefficient
S: Subthreshold slope
 Ioff is usually specified at 25 °C and increases
exponentially with temperature

7: Power CMOS VLSI Design 4th Ed. 29

 Stack Effect
 Series OFF transistors have less leakage
– Vx small, N1 has low DIBL and small leak
– Vx > 0, so N2 has negative Vgs
h Vx VDD  Vx h  VDD Vx  VDD   kg Vx

I sub  I off 10 S
 I off 10 S

N1 N2
hVDD
Vx 
1  2h  kg
 1h  kg 
hVDD  
 1 2h  kg  hVDD
 
I sub  I off 10 S
 I off 10 S

– Leakage through 2-stack reduces ~10x

– Leakage through 3-stack reduces further

7: Power CMOS VLSI Design 4th Ed. 30

 Leakage Control
 Leakage and delay trade off
– Aim for low leakage in sleep and low delay in
active mode
 To reduce leakage:
– Increase Vt: multiple Vt
• Use low Vt only in critical circuits
– Increase Vs: stack effect
• Input vector control in sleep
– Decrease Vb
• Reverse body bias in sleep
• Or forward body bias in active mode

7: Power CMOS VLSI Design 4th Ed. 31

 Leakage Control (2)
 Other forms of leakage must be considered to
reduce Subthreshold leakage.
 Raising the doping level to raise Vt by controlling
DIBL and short-channel effects increases BTBT.
 Applying a reverse body bias to increase Vt also
causes BTBT to increase.
 Applying a negative gate voltage to turn the
transistor OFF more strongly increases GIDL.
 Silicon on Insulator (SOI) circuits are attractive for
low-leakage designs because they have a sharper
subthreshold current roll-off.

7: Power CMOS VLSI Design 4th Ed. 32

 Gate Leakage
 Extremely strong function of tox and Vgs
– Negligible for older processes
– Approaches subthreshold leakage at 65 nm and
below in some processes
 An order of magnitude less for pMOS than nMOS
 Control leakage in the process using tox > 10.5 Å
– High-k gate dielectrics help
– Some processes provide multiple tox
• e.g. thicker oxide for 3.3 V I/O transistors
 Control leakage in circuits by limiting VDD

7: Power CMOS VLSI Design 4th Ed. 33

 Gate Leakage (2)
 Gate leakage also depends on the
voltage across the gate
 For the example in the figure
– If N1 is ON and N2 is OFF, N1 has Vgs = VDD
and has full gate leakage.
– On the other hand, if N1 is OFF and N2 is on,
N2 has Vgs = Vt and
experiences negligible gate leakage
– In both cases, the OFF transistor has no gate
leakage.
– Thus, gate leakage can be alleviated by
stacking transistors such that the OFF
transistor is closer to the rail
7: Power CMOS VLSI Design 4th Ed. 34
 NAND3 Leakage Example
 100 nm process
Ign = 6.3 nA Igp = 0
Ioffn = 5.63 nA Ioffp = 9.3 nA

Data from [Lee03]

7: Power CMOS VLSI Design 4th Ed. 35

 Junction Leakage
 From reverse-biased p-n junctions
– Between diffusion and substrate or well
 Ordinary diode leakage is negligible
 Band-to-band tunneling (BTBT) can be significant
– Especially in high-Vt transistors where other
leakage is small
– Worst at Vdb = VDD
 Gate-induced drain leakage (GIDL) exacerbates
– Worst for Vgd = -VDD (or more negative)

7: Power CMOS VLSI Design 4th Ed. 36

Static Power Estimation
 Static CMOS circuits have no contention current.
 Some other families inherently draw current even
while quiescent. (e.g. pseudo nMOS logic)
 Static current is estimated by:
– Estimate total width of transistors that are leaking,
– multiplying by the leakage current per width,
– and multiplying by the fraction of transistors that
are in their leaky state (usually one half ).
– Add the contention current if applicable.
– The static power is the supply voltage times the
static current.
7: Power CMOS VLSI Design 4th Ed. 37
 Static Power Example
 Revisit power estimation for 1 billion transistor chip
 Estimate static power consumption
– Subthreshold leakage
• Normal Vt: 100 nA/mm
• High Vt: 10 nA/mm
• High Vt used in all memories and in 95% of
logic gates
– Gate leakage 5 nA/mm
– Junction leakage negligible

7: Power CMOS VLSI Design 4th Ed. 38

 Solution
Wnormal-Vt   50 106  12l  0.025m m / l  0.05   0.75 106 m m

Whigh-Vt   50 106  12l  0.95    950 106   4l    0.025m m / l   109.25 10 6 m m

I sub  Wnormal-Vt 100 nA/m m+Whigh-Vt 10 nA/m m  / 2  584 mA

 
I gate   Wnormal-Vt  Whigh-Vt  5 nA/m m  / 2  275 mA
 
Pstatic   584 mA  275 mA 1.0 V   859 mW

7: Power CMOS VLSI Design 4th Ed. 39

 Power Gating
 Turn OFF power to blocks when they are idle to
save leakage
– Use virtual VDD (VDDV)
– Gate outputs to prevent
invalid logic levels to next block
 Voltage drop across sleep transistor degrades
performance during normal operation
– Size the transistor wide enough to minimize delay
and voltage drop
– Also, it should have low leakage during sleep
 Switching wide sleep transistor costs dynamic power
– Only justified when circuit sleeps long enough
7: Power CMOS VLSI Design 4th Ed. 40
 Power Gating Design
 It can be done externally with a disable input to a
voltage regulator or internally with high-Vt header or
footer switches
 On-chip power gating can use pMOS header switch
transistors or nMOS footer switch transistors
 Fine-grained power gating can be applied to
individual logic gates, but placing a switch in every
cell has enormous area overhead
 Practical designs use coarse-grained power gating
where the switch is shared across an entire block
 The switch is commonly sized to keep this delay to
5–10%
7: Power CMOS VLSI Design 4th Ed. 41
 Multiple Threshold Voltages
 Multiple threshold voltages can keep performance
on critical paths with low-Vt transistors while
reducing leakage on others with high-Vt transistors.
 Good design practice starts with high-Vt devices
everywhere and selectively introduces low-Vt
devices where necessary.
 Using multiple thresholds requires additional implant
masks that add to the cost of a CMOS process.
 Alternatively, designers can increase the channel
length, which tends to raise the threshold voltage via
the short channel effect.

7: Power CMOS VLSI Design 4th Ed. 42

Variable Threshold Voltage
 Vsb controls the threshold voltage via the body effect
 In variable threshold CMOS (VTCMOS), a body bias
is applied to achieve high Ion and low Ioff
 For example, low-Vt devices can be used and a
reverse body bias (RBB) can be applied during sleep
mode to reduce leakage
 Alternatively, higher-Vt devices can be used, and
then a forward body bias (FBB) can be applied during
active mode to increase performance
 Improper body biasing can increase leakage via
BTBT and junction leakage

7: Power CMOS VLSI Design 4th Ed. 43