Current Mode Logic

Mode Logic (CML) latches. The variation of the latch delay is primarily caused by the finite current transition time, which in fact depends on the rise/fall times of the clock signal. In this analysis a relation is defined between the latch characteristic parameters and the signal slew rates. The presented analysis is specific for CML latches, but it still gives insight of such behavior in other latch and flipflop structures. 0.18 m CMOS technology examples are provided.

This paper presents a three-stage CML (current mode logic) ring VCO fabricated in a 0.12 µm SOI CMOS technology with a minimum stage delay of 5.4 ps at a differential voltage swing of 400 mV. The maximum oscillation frequency measured is 31 GHz. A tuning range as high as 10 % is measured. The phase noise is -95.9 dBc at an offset frequency of 10 MHz. The energy per stage is as low as 26.8 fJ at a power supply voltage of 1.5 V and a delay per stage of 5.95 ps.

This paper introduces a new reduced swing logic style called dynamic current mode logic (DyCML) that reduces both gate and interconnect power dissipation. DyCML circuits combine the advantages of MOS current mode logic (MCML) circuits with those of dynamic logic families to achieve high performance at a low-supply voltage with low-power dissipation. Unlike CML circuits, DyCML gates do not have a static current source, which makes DyCML a good candidate for portable devices and battery-powered systems. Simulation and test results show that DyCML circuits are superior to other logic styles in terms of power and delay. A 16-bit DyCML carry look-ahead adder (CLA), fabricated in 0.6-μm CMOS technology, attains a delay of 1.24 ns and dissipates 19.2 mW at 400 MHz

A comprehensive study of the MOS Current Mode Logic (MCML) is presented. Operation of a conventional MCML latch is analyzed and some modified structures are described. A novel structure is proposed for increased stability with reduced delay parameters. General problems with single-ended to differential conversion are addressed. Comparative performance measures of Master-Slave (MS) latches are presented in a 0.18-µm CMOS technology.

This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also discusses a high-speed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure with conventional static and dynamic CMOS logic circuit. The static Majority function (bridge) design style enjoys a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as lower power consumption by using bridge transistors. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of mixedmode logic designs. Dynamic CMOS circuits enjoy area, delay and testability advantages over static CMOS circuits. Simulation results illustrate the superiority of the new designed adder circuits against the reported conventional CMOS, dynamic and majority function adder circuits, in terms of power, delay, power delay product (PDP) and energy delay product (EDP). The design is implemented on UMC 0.18µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S. .

A 10Gb/s current mode logic (CML) transmitter with multi-tap finite impulse response (FIR) pre-emphasis has been implemented in 0.18µm CMOS technology. A half-rate clock retiming circuit for generating symbol-spaced data is proposed to alleviate the speed requirement of the traditional full-rate clock retiming. HSPICE simulation results of a 5-tap FIR transmitter show that the closed eye over a 34" FR4 backplane can be opened to 0.72UI at 10Gb/s. The power dissipation of the transmitter is 50mW at a 1.8V supply.

This paper presents a clock-and-data recovery (CDR) for pseudo-synchronous high-density link applications. The CDR is a first-order bang-bang (BB) topology implemented in a standard CMOS process and consists of a phase interpolator, a linear half-rate phase detector, an analog filter followed by a limiter and a digital loop filter operating at a reduced clock rate. A detailed BB CDR analysis derives the maximum tracking range, slew-rate limited jitter tolerance and maximum loop delay. The circuit is optimized for high speed as well as low area and power consumption. The CDR operates from 8-28 Gb/s at a BER of 10 12 and tracks frequency deviations between the incoming data and the reference clock of up to 122 ppm. The sinusoidal jitter tolerance is 0.35 UI pp for jitter frequencies 100 MHz and the total timing jitter of the recovered half-rate output data amounts to 0.22 UI pp at a BER = 10 12 . The core CDR circuit occupies a chip area of 0.07 mm 2 and consumes 98 mW from a 1.1-V supply.

This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also discusses a high-speed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure with conventional static and dynamic CMOS logic circuit. The static Majority function (bridge) design style enjoys a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as lower power consumption by using bridge transistors. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of mixedmode logic designs. Dynamic CMOS circuits enjoy area, delay and testability advantages over static CMOS circuits. Simulation results illustrate the superiority of the new designed adder circuits against the reported conventional CMOS, dynamic and majority function adder circuits, in terms of power, delay, power delay product (PDP) and energy delay product (EDP). The design is implemented on UMC 0.18µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S. .

This paper deals with current mode logic (CML) and, in particular, models and optimized design strategies for MUX, XOR, and D flip-flop are presented. Both simple and accurate models for propagation delay are proposed. The models represent propagation delay with a few terms, providing a better insight into the relationship between delay and its electrical parameters, which in turn are related to process parameters. The main difference between accurate and simple models is that the former need only a few SPICE simulations to properly evaluate model parameters. The simple models show errors which are always lower than 20%, while accurate models have typical errors of 2%. Design optimization is in terms of bias currents giving minimum propagation delay, and it has been demonstrated that at the cost of a 10% increase in propagation delay we can reduce power dissipation by 40%. The models and design strategies are validated using both a traditional and a high-speed bipolar process which have a transition frequency equal to 6 and 20 GHz, respectively.

A wired-AND current-mode logic (WCML) circuit technique in CMOS technology for low-voltage and high-speed VLSI circuits is proposed, and a WCML cell library is developed using standard 0.8 micron CMOS process. The proposed WCML technique applies the analog circuit design methodologies to the digital circuit design. The input and output logic signals are represented by current quantities. The supply current of the logic circuit is adjustable for the required logic speed and the switching noise level. The noise is reduced on the power supply lines and in the substrate by the current-steering technique and by the smooth swing of the reduced node potentials. Precise analog circuits and fast digital circuits can be integrated on the same silicon substrate by using the low noise property of the WCML. It is shown by the simulations that at low supply voltages, the WCML is faster and generates less switching noise when compared to the static-CMOS logic. At high speeds, the power dissipation of the WCML is less than that of the static-CMOS logic.

Abstruct -This paper describes integrated circuits (IC's) fabricated with AIInAs/GaInAs hetemjunction bipolar transistors (HBT's) lattice matched to InP substrates. A cutoff frequency f T and a maximum frequency of oscillation fmax of 90 and 70 GHz, respectively, have been achieved with a 2x5-pm2 emitter size HBT. Current-mode logic (CML) was used to demonstrate ring oscillators, flip-flop divider circuits, and dual-modulus prescalers. The ring oscillators demonstrated a 15.8-ps gate delay, the CML flip-flip divider circuits demonstrated 24.8-GHz toggle rates, and the 4/5 and 8/9 dual-modulus prescalers consisting of 106 and 124 transistors, respectively, operated up to 9-GHz clock rates. The dual-modulus prescalers are the largest circuits fabricated with HBT's on InP substrates.

In this paper, the low-voltage CML D-latch topology is analyzed and compared to the traditional implementation to evaluate its speed potential and power efficiency, which are crucial aspects in current applications. To this end, an analytical delay model is first derived and then used to optimize its speed performance and understand its power-delay interdependence. The delay model, based on the approach proposed by Alioto and Palumbo (IEEE Trans. Circuits Systems I 46(11) (1999) 1330; IEEE Trans. Circuits and Systems II 47 , leads to simple expressions that are suitable for pencil-and-paper evaluations. The accuracy of the expressions obtained is tested by comparison to SPICE simulations, by using a bipolar process whose npn transistor has a transition frequency of 20 GHz. The delay expressions derived are used to design and compare the low-voltage and the traditional D-latch both in terms of delay and power-delay tradeoff, by considering a high-performance and a low-power consumption design target. The analytical comparison carried out is general, since it does not depend on the specific bipolar process considered. Analysis shows that the low-voltage D-latch topology does not necessarily allow for a power saving or a better power efficiency, and applications where this topology exhibits some advantage over the traditional implementation are identified. r

This paper presents a detailed analysis of metastable behavior in CMOS current mode logic (CML) latches. The variation of the latch delay is primarily caused by the finite current transition time, which in fact depends on the rise/fall times of the clock signal. In this analysis a relation is defined between the latch characteristic parameters and the signal slew rates. The presented analysis is specific for CML latches, but it still gives insight of such behavior in other latch and flip-flop structures. 0.18 mum CMOS technology examples are provided

Current mode (ECL) logic has long been the option of choice in those applications requiring logic functions at multigigahertz rates. This trend continues despite the obvious very high static power consumption and small signal swing characterizing this logic. In this work we investigate a simple mechanism for Low-Voltage-Swing Logic (LVSL) to greatly reduce the power requirement of a CML logic subsystem while improving the reliability and signal integrity. For the presented circuits operating at 5 GHz, 50% power reduction is achieved while improving the signal integrity.

Abstruct -This paper describes integrated circuits (IC's) fabricated with AIInAs/GaInAs hetemjunction bipolar transistors (HBT's) lattice matched to InP substrates. A cutoff frequency f T and a maximum frequency of oscillation fmax of 90 and 70 GHz, respectively, have been achieved with a 2x5-pm2 emitter size HBT. Current-mode logic (CML) was used to demonstrate ring oscillators, flip-flop divider circuits, and dual-modulus prescalers. The ring oscillators demonstrated a 15.8-ps gate delay, the CML flip-flip divider circuits demonstrated 24.8-GHz toggle rates, and the 4/5 and 8/9 dual-modulus prescalers consisting of 106 and 124 transistors, respectively, operated up to 9-GHz clock rates. The dual-modulus prescalers are the largest circuits fabricated with HBT's on InP substrates.

MOSAIC 5SE. Motorola's scaled and enhanced double polysilicon bipolar technology, has demonstrated world class performance in digital and analogue applications. A minimum power-delay product of 5.4fJ in current mode logic (CML) ring oscillator circuits and a noise figure of 0.9dB at 1.2 GHz with 18dB of gain are the best reported results in the digital and analogue world. High-bit-rate (Gbit/s)

MOSAIC 5SE. Motorola's scaled and enhanced double polysilicon bipolar technology, has demonstrated world class performance in digital and analogue applications. A minimum power-delay product of 5.4fJ in current mode logic (CML) ring oscillator circuits and a noise figure of 0.9dB at 1.2 GHz with 18dB of gain are the best reported results in the digital and analogue world. High-bit-rate (Gbit/s)

This paper presents a new 54×54-bit multiplier using fully differential-pair circuits (DPCs). The DPC is a key component in maintaining an input signal-voltage swing of 0.2V while providing a large current-driving capability. The combination of the DPC and the multi-level current-mode linear summation makes critical-path delay and transistor counts reduced, which achieves 1.88ns latency with 74.2mW from a 1.8V supply on a 0.85mm 2 die. It is also discussed about the efficiency of the DPCs for crosstalk noise reduction.

An analytical model for calculating the propagation delay time of two-level series-gated current mode logic (CML) and emitter-coupled logic (ECL) high-speed bipolar circuits is presented. The analytical delay model accounts for all the device parasitics and the device sizes of the two levels. Moreover, high-current effects are also considered in the developed model. Exploiting these two features, the model has been successfully applied in optimizing the design of a variety of two-level seriesgated CML and ECL circuits for maximum speed (minimum delay). A comparison with the results obtained by SPICE is presented to verify the applicability of the proposed model.

A 10Gb/s current mode logic (CML) transmitter with multi-tap finite impulse response (FIR) pre-emphasis has been implemented in 0.18µm CMOS technology. A half-rate clock retiming circuit for generating symbol-spaced data is proposed to alleviate the speed requirement of the traditional full-rate clock retiming. HSPICE simulation results of a 5-tap FIR transmitter show that the closed eye over a 34" FR4 backplane can be opened to 0.72UI at 10Gb/s. The power dissipation of the transmitter is 50mW at a 1.8V supply.

Security of electronic data remains the major concern. The art of encryption to secure the data can be achieved in various levels of abstraction. The choice of the logic style in implementing the security algorithms has greater significance, and it can enhance the ability of providing better resistance to side channel attacks. The static CMOS logic style is proved to be prone to side channel power attacks. The exploration of CMOS current mode logic style for resistance against these side channel attacks is discussed in this paper. Various characteristics of the current mode logic styles, which make it suitable for making DPA resistant circuits are explored. A new methodology of biasing the sleep transistors of (MOS current mode logic) MCML families is proposed. It uses pass gate transistors for power-gating the circuits. The power variations of the proposed circuits are compared against the standard CMOS counterparts. Logic gates such as XOR, NAND and AND gate structures of MCML families and static CMOS are designed and compared for the ability of side channel resistance. A distributed arrangement of sleep transistors for reducing the static power dissipation in the logic gates is also proposed, designed and analyzed. All the logic gates in MCML and CMOS were implemented using standard 180 nm CMOS technology employing Cadence® EDA tools.

This paper presents a detailed analysis of metastable behavior in CMOS current mode logic (CML) latches. The variation of the latch delay is primarily caused by the finite current transition time, which in fact depends on the rise/fall times of the clock signal. In this analysis a relation is defined between the latch characteristic parameters and the signal slew rates. The presented analysis is specific for CML latches, but it still gives insight of such behavior in other latch and flip-flop structures. 0.18 mum CMOS technology examples are provided

A synthesis-based bandwidth enhancing technique for current-mode-logic (CML) buffers/amplifiers is presented, which achieves bandwidth-enhancement-ratio (BWER) of 4.84, close to a proven theoretical upper limit of 4.93. By employing a complete step-by-step design methodology, the proposed technique can be applied to any load condition, which is characterized by the ratio between the load capacitance and the output capacitance of the transconductor cell. Several prototype buffer/amplifier circuits are designed using lower order passive networks to save chip area. The test chip is fabricated in a 0.18µm CMOS process, and measurements show a BWER of 3.8.

This paper presents a broadband, static, 2:1 frequency divider in a bulk 90nm CMOS LP (low-power) technology with maximum operating frequency of 35.5 GHz. The divider exhibits an enhanced input sensitivity, below 0 dBm, over a broad input range of 31 GHz and consumes 24mA from a 1.2 V supply. The phase noise of the divider is-124.6 dBc/Hz at 1 MHz offset from the carrier.

This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs). The design is primarily based on a multiple-valued logic literal circuit that utilizes the folded-back I-V (also known as negative differential-resistance, NDR) characteristics of RTDs to compactly implement its gated transfer function. MOS transistors are configured in current-mode logic, where addition of two or more digits is achieved by superimposing the signals of individual wires being physically connected at the summing nodes. The proposed SDFA design uses redundant arithmetic representation and, therefore, the circuit can perform addition of two arbitrary size binary numbers in constant time without the need for either carry propagation or carry look-ahead. The SDFA cell design has been verified through simulation by an augmented SPICE simulator that includes new homotopy-based convergence routines to tackle the nonlinear device characteristics of quantum devices. From the simulation result, the SDFA cell has been found to perform addition operation in 3.5 nanoseconds, which is somewhat superior to other multivalued redundant arithmetic circuits reported in the literature. The SDFA cell requires only 13 MOS transistors and one RTD, as opposed to the state-of-the-art CMOS redundant binary adder requiring 56 transistors, and to the conventional multivalued current-mode adder consisting of 34 MOS transistors. In order to verify the simulation result, a prototype SDFA cell has been fabricated using MOSIS 2-micron CMOS process and GaAs-based RTDs connected externally to the MOSFET circuit. Index Terms-Signed-digit arithmetic, multiple-valued logic, quantum electronic resonant-tunneling circuits.xxx ----------F ----------0018-9340/98/$10.00 © 1998 IEEE ²²²²²²²²²²²²²²²² • The authors are with the

Integrated-circuit interconnect characterization is growing in importance as devices become faster and smaller. Along with this trend, interconnect geometry is becoming more complex, consisting of an increasing number of wiring levels. Accurate numerical extraction of three-dimensional (3-D) interconnect capacitance is essential for achieving design targets in the multigigahertz digital regime. Interconnectcapacitance extraction is complicated by the presence of inhomogeneous layers with differing dielectric constant. Dielectric anisotropy as well is common in many low-polymeric dielectrics used in high-performance IC's. A CAD procedure using the novel floating random-walk extractor QuickCAP is presented. Our procedure is efficient enough to extract a substantial amount of a chip's 3-D wiring. We include as well dielectric anisotropy and inhomogeneity. The procedure is not based on effective conductor geometry or on a finite-sized conductor library but rather on the entire 3-D layout, accounting for actual local variations in conductor separations and shapes. We then apply our procedure to an experimental circuit vehicle implemented in AlGaAs/GaAs heterojunction bipolar transistor current-mode logic. This vehicle is used to validate the accuracy of our CAD procedure in predicting circuit speed. Measured and predicted test-capacitor values and ring-oscillator propagation times agreed generally to within 2-4%. To verify results on a larger digital circuit, we analyzed all interconnects in an adder carry-chain oscillator using our procedure. Predicted propagation delays were generally within 3% of measurement.

This paper presents a detailed analysis of metastable behavior in CMOS Current Mode Logic (CML) latches. The variation of the latch delay is primarily caused by the finite current transition time, which in fact depends on the rise/fall times of the clock signal. In this analysis a relation is defined between the latch characteristic parameters and the signal slew rates. The presented analysis is specific for CML latches, but it still gives insight of such behavior in other latch and flipflop structures. 0.18 m CMOS technology examples are provided.

This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs). The design is primarily based on a multiple-valued logic literal circuit that utilizes the folded-back I-V (also known as negative differential-resistance, NDR) characteristics of RTDs to compactly implement its gated transfer function. MOS transistors are configured in current-mode logic, where addition of two or more digits is achieved by superimposing the signals of individual wires being physically connected at the summing nodes. The proposed SDFA design uses redundant arithmetic representation and, therefore, the circuit can perform addition of two arbitrary size binary numbers in constant time without the need for either carry propagation or carry look-ahead. The SDFA cell design has been verified through simulation by an augmented SPICE simulator that includes new homotopy-based convergence routines to tackle the nonlinear device characteristics of quantum devices. From the simulation result, the SDFA cell has been found to perform addition operation in 3.5 nanoseconds, which is somewhat superior to other multivalued redundant arithmetic circuits reported in the literature. The SDFA cell requires only 13 MOS transistors and one RTD, as opposed to the state-of-the-art CMOS redundant binary adder requiring 56 transistors, and to the conventional multivalued current-mode adder consisting of 34 MOS transistors. In order to verify the simulation result, a prototype SDFA cell has been fabricated using MOSIS 2-micron CMOS process and GaAs-based RTDs connected externally to the MOSFET circuit.

This paper describes a new signed-digit full adder (SDFA) circuit consisting of resonant-tunneling diodes (RTDs) and metal-oxide semiconductor field effect transistors (MOSFETs). The design is primarily based on a multiple-valued logic literal circuit that utilizes the folded-back I-V (also known as negative differential-resistance, NDR) characteristics of RTDs to compactly implement its gated transfer function. MOS transistors are configured in current-mode logic, where addition of two or more digits is achieved by superimposing the signals of individual wires being physically connected at the summing nodes. The proposed SDFA design uses redundant arithmetic representation and, therefore, the circuit can perform addition of two arbitrary size binary numbers in constant time without the need for either carry propagation or carry look-ahead. The SDFA cell design has been verified through simulation by an augmented SPICE simulator that includes new homotopy-based convergence routines to tackle the nonlinear device characteristics of quantum devices. From the simulation result, the SDFA cell has been found to perform addition operation in 3.5 nanoseconds, which is somewhat superior to other multivalued redundant arithmetic circuits reported in the literature. The SDFA cell requires only 13 MOS transistors and one RTD, as opposed to the state-of-the-art CMOS redundant binary adder requiring 56 transistors, and to the conventional multivalued current-mode adder consisting of 34 MOS transistors. In order to verify the simulation result, a prototype SDFA cell has been fabricated using MOSIS 2-micron CMOS process and GaAs-based RTDs connected externally to the MOSFET circuit. Index Terms-Signed-digit arithmetic, multiple-valued logic, quantum electronic resonant-tunneling circuits.xxx ----------F ----------0018-9340/98/$10.00 © 1998 IEEE ²²²²²²²²²²²²²²²² • The authors are with the

Mode Logic (CML) latches. The variation of the latch delay is primarily caused by the finite current transition time, which in fact depends on the rise/fall times of the clock signal. In this analysis a relation is defined between the latch characteristic parameters and the signal slew rates. The presented analysis is specific for CML latches, but it still gives insight of such behavior in other latch and flipflop structures. 0.18 m CMOS technology examples are provided.

IC interconnect characterization is growing in importance as devices become faster and smaller. Accurate numerical extraction of 3D interconnect capacitance is essential for achieving design targets in the multi-GHz digital regime. An AlGaAs-GaAs heterojunction-bipolar-transistor test chip was fabricated. The chip used 3-level metal with anisotropic polyimide interlevel dielectrics. Full differential current-mode logic circuit technology was employed. The chip contained a variety of interconnect capacitor structures (parallel plate, finger, crossover) and interconnect-limited ring-oscillator circuits. Capacitance and oscillator frequency measurements were performed to compare with CAD-tool predictions. Good agreement with measurements was achieved with an independently obtained 25% uniaxial polyimide dielectric anisotropy. Measured and predicted results for the capacitor test structures generally agreed to within 2%. Predicted ring-oscillator periods were within 4% of measurement

A current mode logic (CML)-type resonant tunneling diode (RTD)/heterojunction bipolar transistor (HBT) monostablebistable transition logic element (MOBILE) IC with complementary outputs is proposed, which can simplify logic designs on the basis of complementary logic operation. Using the CML-type current modulator in the MOBILE IC, both the noninverted and inverted outputs are simultaneously generated with a single input signal. The CML-type MOBILE IC with complementary outputs has been fabricated using an InP-based RTD/HBT technology, and the operation of the fabricated circuit has been confirmed up to 10 Gb/s as a MOBILE with the complementary outputs. Moreover, the operation of a non-return-to-zero (NRZ) D-flip flop circuit, integrated with a set/reset latch (SR latch) using the CML-type complementary MOBILE IC has been for the first time confirmed up to 8 Gb/s with a low power consumption of 86 mW.

A comprehensive study of the MOS Current Mode Logic (MCML) is presented. Operation of a conventional MCML latch is analyzed and some modified structures are described. A novel structure is proposed for increased stability with reduced delay parameters. General problems with single-ended to differential conversion are addressed. Comparative performance measures of Master-Slave (MS) latches are presented in a 0.18-µm CMOS technology.

In this paper, an embedded jitter measurement system is presented. The system uses the Vernier delay method to achieve high resolution. The jitter test circuit is implemented using current-mode logic, so it is fast enough for testing today's high-speed I/O signals such as PCI Express. And the differential structure also makes the circuit immune to common-mode noise. Other advanced jitter

This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also discusses a high- speed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure with conventional static and dynamic CMOS logic circuit. The static Majority function (bridge) design style enjoys a high degree of regularity and symmetric higher density than the conventional CMOS design style as well as lower power consumption by using bridge transistors. This technique helps in reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of mixedmode logic designs. Dynamic CMOS circuits enjoy area, delay and testability advantages over static CMOS circuits. Simulation results illustrate the superiority of the new designed adder circuits against the reported conventional CMOS, dynamic and majority function adder circuits, in terms of power, delay, power delay product (PDP) and energy delay product (EDP). The design is implemented on UMC 0.18µm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.