Metastability analysis OF CMOS current mode logic latches

METASTABILITY ANALYSIS OF CMOS CURRENT MODE LOGIC LATCHES Muhammad Usama Department of Electronics Carleton University, 1125 Colonel By Drive Ottawa, ON K1S 5B6 Canada email: [email protected] Tad A. Kwasniewski Department of Electronics Carleton University, 1125 Colonel By Drive Ottawa, ON K1S 5B6 Canada email: [email protected] Abstract This paper presents a detailed analysis of metastable behavior in CMOS Current Mode Logic (CML) latches. The variation of the latch delay is primarily caused by the finite current transition time, which in fact depends on the rise/fall times of the clock signal. In this analysis a relation is defined between the latch characteristic parameters and the signal slew rates. The presented analysis is specific for CML latches, but it still gives insight of such behavior in other latch and flipflop structures. 0.18Pm CMOS technology examples are provided. Keywords: Metastability analysis, CMOS Current Mode Logic, CML Latches, signal slew-rate. 1. Introduction A latch is a level-sensitive clocked storage element. It usually contains clock (CLK), data (D) as an input and an output (Q). During one phase of the clock the latch is transparent, this phase is called a transparent phase. The other clock phase is known as a latching phase, during which the output holds the previous data value and is not affected by any change at the data input. The clock edge between the transparent and the latching phase is called the isolating or triggering edge. The timing parameters for the latch are defined with respect to this triggering edge. Setup time is the minimum time the data can change before the triggering edge of the clock, such that a correct output value is produced. Hold time is the minimum time the data can change after the triggering edge of the clock. The failure of a latch due to setup and hold time violations is not an abrupt process [1]. During the transparent phase of the clock, there is a certain delay between the last change in the data and the corresponding change at the output, denoted by TDQ. This delay is not always constant; it depends on the relative position of the data with respect to the triggering edge of the clock, denoted by TDC. For smaller TDC, an increase in the TDQ can be seen before the latch fails to capture the data. Setup and hold times can be defined as the TDC time at which the latch delay TDQ increases by a certain amount (usually an arbitrary number around 5% to 10%) from its stable value [1]. 0-7803-8886-0/05/$20.00 ©2005 IEEE CCECE/CCGEI, Saskatoon, May 2005 Fig. 1. Operating regions of a latch. This variation in the delay is due to the metastable behavior of the latch. Fig. 1 illustrates the regions of stability in the latch. A similar curve can be obtained for negative TDC, showing the hold time. This delay variation directly translates into jitter when these latches are used in circuits, like frequency prescalers. The main cause of metastable behavior is the finite rise/fall time of the clock and data. At multi-gigahertz frequencies the rise/fall times of these signals are a significant fraction of the clock period. The waveform often resembles a sinusoidal wave, so the metastability is unavoidable. This paper presents a detailed analysis of the metastable behavior in the CML latches. Section-2 briefly describes the operation of the CML latch. In Section-3 metastability dependence on the rise/fall time of the clock signal is derived. Section-4 presents 0.18 Pm CMOS technology simulation results to verify the correctness of the presented analysis. 2. CML Latches A conventional current mode logic latch consists of a sample and a hold stage, as shown in the Fig. 2 [2]. The current switching between the pairs takes place by the complementary signals of the clock. The sampling pair works as a CML buffer and when it is activated by the clock signal, it keeps track of the input data and transforms it to the outputs. This is known as the sampling mode of the latch. When the clock polarity changes the hold pair becomes active. The crosscoupled transistors in the hold pair form a regenerative positive 1521 Authorized licensed use limited to: Carleton University. Downloaded on July 17, 2009 at 14:05 from IEEE Xplore. Restrictions apply. Table 1. Total output capacitance Sample Mode Hold Mode CS+ (5/3)Cox*W*L + 4Cox*W*LD + 2Cox*DW*L + 2Cj CS- 2Cox*W*L + 4Cox*W*LD + 2Cox*DW*L + 2Cj CH+ (4/3)Cox*W*L + 4Cox*W*LD + 2Cox*DW*L + 2Cj CH- 2Cox*W*L + 4Cox*W*LD + 2Cox*DW*L + 2Cj Cox = İox/Tox, LD = Lateral Diffusion, DW = 2LD, W = Width, L = Length 3. CML Latch Delay Analysis Fig. 2. A conventional CML latch. feedback structure and keep the output data at the current state. This is known as the hold mode because the output is isolated from any changes in the input data, as no current is flowing through the sampling pair. Any change in a signal with a finite slew rate will take some time for the input charging to threshold and internal device turning on, denoted by Ti, which depends on the size and biasing conditions of the device. After this delay the current flowing through the device changes immediately and charging or discharging of output capacitance starts. Ti delay is usually small as compared to the output charging time. Different transition time for the data and the clock will have different impact on the latch propagation delay. For the following analysis it is assumed that the rise/fall time of the data and clock signals are the same and denoted by Tr. A properly biased CML circuit has all the biasing current IS flowing through either one of the two branches. Due to a voltage drop across the load RL the low output voltage becomes VL = VDD – ISRL. The other output of the branch with no current remains at the high voltage VH = VDD. The output voltage swing ǻV is therefore VH – VL = ISRL. Ideally all the input and output signals have the same voltage swing ǻV with a common mode voltage VM = VDD – ǻV/2. Let I1 and I2 be the currents flowing through the two loads, and Isample and Ihold be the currents flowing through the sample and the hold pairs respectively. The total capacitance at the output of the latch is given by CO CL  C j  CHold (1) where CL is the load capacitance, Cj is the drain to bulk junction capacitance and CHold is the parasitic capacitance of the cross-coupled hold pair. It is interesting to note that both outputs see different output capacitances during the sample and the hold mode, because of the change in the operating region of active devices [3]. Let CS+, CS , CH+ and CH be the output capacitances of the positive and negative outputs during the sample and hold modes respectively. Table 1 summarizes the total capacitance at the output terminals in both modes of latch operation. These unequal output capacitances result in unequal rise and fall times. It is assumed that the CML latch is driving the same size CML latch or buffer. The load capacitance CL will also vary depending on the biasing conditions of the following stage. Fig. 3. Signal waveforms to illustrate the terminologies used. 3.1. Delay in the Stable Region If the last change in the data is during the transparent mode of the latch well before the triggering edge of the clock, the output will change accordingly after a certain delay TDQ(Stable). If the data changes from a low input voltage VL to a high input voltage VH in time Tr, consequently after Ti delay the flow of current will switch in the branches from I1 to I2 in time Tr. Still all the current is flowing through the sample pair, because 1522 Authorized licensed use limited to: Carleton University. Downloaded on July 17, 2009 at 14:05 from IEEE Xplore. Restrictions apply. there is no change in the clock signal. Once the current transition starts, the output starts charging and during the current transition it will be charged up to a final value VO Tr VO 1 VL   CS 2 ³ i dt s Tr VL  2 1 I S Tr 2 C S (2) At this point the current reaches a stable value of IS and the charging process continues. Time required to charge the output to the mid-swing voltage level VM is given by T § 1 I S Tr ¨¨VM  VL  2 C S © · C S ¸¸ ¹ IS 1 C S 1 'V  Tr 2 IS 2 (3) so the propagation delay in the stable region is given by 1 1 C S 1 'V  Tr TDQ ( Stable) Ti  Tr  2 2 IS 2 Ti  1 C S 'V 2 IS Depending on the level to which the output was previously charged, it is possible that the output will be charged up to VM during the time Tr/2. The hold pair would then regenerate it correctly. This would result in a longer delay and a longer rise time. This is known as the metastable region where the latch’s delay TDQ increases exponentially with smaller TDC. 3.4. Limit of the Metastable/Failure Region If the output fails to charge to VM during the first half of current transition the hold pair regenerates to a wrong value and the latch operation fails. The metastable region is limited by TDC(min) for which the output is charged to VM just before the current through the hold pair exceeds from that of the sample pair. Using (6), the output charging to VM during the half current transition is 3 I S Tr 1 I S Tr  8 C S 8 C S (4) and the initial charging during the data transition, from (2), is VO Note that the delay is taken as the time from 50% input to the 50% output charging. 3.2. Limit of the Stable Region Limit of the stable region is TDC(Stable), (see Fig.1), for which there is no increase in the latch delay from its stable value TDQ(Stable). It is only possible if the outputs are already charged to VM, just before the current starts to switch from the sample to the hold pair. Current transition starts 1 Tr  Ti time 2 1 C S 1 'V  Tr 2 IS 2 Output Charging = Charging (Sample) – Discharging (Hold) 1 1 C S 3 1 Ti  Tr  'V  Tr  Tr 2 2 IS 4 2 Ti  If the data changes after TDC(Stable), the output will not be charged to VM before the current switching starts. Isample will decrease gradually and Ihold will increase at the same time. The hold pair will try to regenerate the data, opposing the sampling pair. During the first half of current transition (Tr /2), the current flowing through the sampling pair is larger than the current flowing through the hold pair. Therefore, (6) (7) now the total time taken for output charging to VM, is given by (5) 3.3. Delay in the Metastable Region 1 I S Tr 2 C S 1 C S 3 'V  Tr 2 IS 4 TDQ (max) Although the total bias current will split between Isample and Ihold, still all the current will be flowing through the same branch (I1 or I2). But there will be some change in the output rise time due to the decrease in the output capacitance, CH+, as the hold pair is now in active region. It is clear from (5) that the setup time increases with Tr. VL  so the time used for charging with stable current IS , is § 1 I S Tr 1 I S Tr · C S ¸  T ¨¨VM  V L  2 C S 4 C S ¸¹ I S © earlier than the clock edge. 1 TDC ( Stable ) t TDQ ( Stable )  Tr  Ti 2 1 I S Tr 4 C S 1 C S 1 'V  Tr 2 IS 4 (8) since the current switching takes place Ti delay after the clock edge, the corresponding TDC(min) can be obtained as follows TDC (min) TDQ (max)  Ti 1 C S 1 'V  Tr 2 IS 4 (9) Any change in the data after this time will not be captured by the latch. And the hold pair will regenerate the output to its previous value. An unwanted bump at the output will appear, as shown in Fig. 4. Equations (5) and (9) define the boundaries of the metastable region, which is clearly dependent on Tr. 4. Simulation Verification The presented analysis is based on an assumption that the biasing current IS remains constant during the switching of data 1523 Authorized licensed use limited to: Carleton University. Downloaded on July 17, 2009 at 14:05 from IEEE Xplore. Restrictions apply. CLK CLKB D Metastable Stable Failure Q Fig. 6. CML latch delay with different rise/fall times. Fig. 4. Effect of late data arrival. and clock signals. However, in reality, as it could easily be observed in simulation, the current IS varies during switching. The first effect is that during the current commutation between the sampling and holding branches the instantaneous conductance of both branches can be low, causing the total current to drop. This can be prevented by careful selection of DC biasing of clock and data signals. The second effect is caused by the CDS parasitic capacitance of the current sourcing transistor. This effect is difficult to avoid especially in a lowvoltage design where the VDS voltage drop is minimized by increasing the W/L ratio of current biasing transistor. Interestingly, the resulting current peaking effect may improve the performance of the latch circuit. The results of this investigation will be reported in a separate publication. 5. Conclusion This paper addressed the issue of metastable behavior in CML latches. A detailed analysis was presented to show the dependence of characteristic latch parameters on the rise/fall time of the clock signal. In fact the latch/flip-flop timing parameters are the issue of reliability of the system. This analysis would allow the designers to find the optimum setup time for the latches/flip-flops, in order to use every fraction of the clock period. The optimum setup time lies within the metastable region [4], whose boundaries are determined by the current switching time. Hence the rise and fall times of the clock signal strongly affect the performance of a latch or flipflop. Based on this analysis, the circuit re-optimization will result in increased speed and reliability of the system. Acknowledgements The authors would like to thank NSERC for supporting this research work. References Fig. 5. Simulation test bench. A test bench is set-up as shown in Fig. 5 to simulate the effect of Tr on the latch timing parameters. TSMC 0.18Pm CMOS technology was used as an example. Series input resistors Rin are used to realize the input charging time Ti, using ideal sources. TDC is swept from the stable region to the failure region and the corresponding latch delay TDQ is plotted. Fig. 6 shows the simulation results, with different values of Tr. It can be observed that during the stable region the delay does not depend on Tr, as predicted by (4). The setup time and the width of metastable region are also proportional to the rise/fall time. The latch delay before failure TDC(max) is found to be much higher in simulation than what was predicted in (8). This is due to the drop in total bias current IS, as explained earlier in this section. [1] Vojin G. Oklobdzija, Vladimir M. Stojanovic, Dejan M. Markovic, and Nikola M. Nedovic, DIGITAL SYSTEM CLOCKING: High-Performance and Low-Power Aspects, IEEE Press: Piscataway, NJ, USA, 2003, Pages: 47-50. [2] Muhammad Usama and Tad Kwasniewski, “Design and comparison of CMOS current mode logic latches,” Proceedings of the International Symposium on Circuits and Systems, Volume: 4, May 2004 Pages: 353 - 356 [3] David A. Johns and Ken Martin, ANALOG INTEGRATED CIRCUIT DESIGN, John Wiley & Sons, Inc., 1997, Pages: 56-61. [4] N. Nedovic, W. W. Walker and V. G. Oklobdzija, “A test circuit for measurement of clocked storage element characteristics,” IEEE Journal of Solid-State Circuits, Volume: 39, Issue: 8, Aug. 2004 Pages: 1294 – 1304. 1524 Authorized licensed use limited to: Carleton University. Downloaded on July 17, 2009 at 14:05 from IEEE Xplore. Restrictions apply.