Unit-1

Architecture of 8086
microprocessors
 What is microprocessor ?
• A microprocessor is a computer processor
that incorporates the functions of a computer
's central processing unit (CPU) on a single
integrated circuit (IC).
• The microprocessor is a multipurpose,
programmabledevice that accepts digital data
as input, processes it according to
instructions stored in its memory, and
provides results as output
 Generation of Microprocessor

• 1st Generation: This was the period during

1971 to 1973 of microprocessor’s history. In
1971, INTEL created the first microprocessor
4004 that would run at a clock speed of 108
KHz.
 Cont…
• 2nd Generation: This was the period during
1973 to 1978 in which very efficient 8-bit
microprocessors -INTEL-8085.
• 3rd Generation: From 1979 to 1980, INTEL
8086/80186/80286 were developed. It is 16-
bit processor.Speeds of those processors were
four times better than the 2nd generation
processors.
 Cont….
• 4th Generation:After 1980, INTEL 80386 &
80486 were developed. It is 32-bit processor.
Terms related to Microprocessors
• Bit
A digit of the binary number or code
• Nibble
The 4-bit binary number or code
• Byte
The 8-bit binary number or code
• Word
The 16-bit binary number or code
• Double Word
The 32-bit binary number or code
 Terms related to Microprocessors
• Data
The quantity operated by an instruction of a
program is called data. The size of the data is
specified as Bit, Byte,Word……..
• Address
The address is an identification number in binary
for Memory locations. The 8086 processor uses
20-bit address for memory.
• Bus
A bus is a group of conducting lines that carries
data,address and control signals.
 Features of 8086
• Introduced in 1978 .
• Comes in Dual-In-Line Package(DIP) IC.
• 8086 1s a 16-bit microprocessor .
• Works on 5 volts power supply.
• It is built on single semiconductor chip and
packaged in an 40-pin IC.
• It has 20-bit address bus and 16-bit data bus.
• It can directly address upto 220 I.e., 1M bytes of
memory.
• The maximum internal clock for 8086 is 5MHz

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 8086 Architecture

• The architecture of 8086 is divided into two

functional parts i.e.,
i. Execution unit (EU)
ii. Bus interface unit (BIU)
• BIU and EU operate parallelly and
independently i.e., EU executes the instructions
and BIU fetches another instruction from the
memory simultaneously.
• As the whole architecture is divided into two
independent functional parts and both the
subsystem’s operations can be overlapped,
hence the architecture is PIPELINING type of
architecture.
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 8086 Architecture
EXECUTION UNIT

• The execution unit consists of the following:

 General purpose registers(AX,BX,CX,DX)
 Pointer & Index registers(SP,BP,SI,DI)
 ALU
 Flag register( FLAGS/ PSW)
 Instruction decoder
 Timing and control unit

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 8086 Architecture
Functions of EU
• Receives opcode of an instruction from the queue.
• decodes the instructions.
• Executes the instruction.
Functions of various parts of EU
• Control circuitry: Directs internal operations.
• Instruction Decoder: Translates instructions fetched from
memory into series of actions.
• ALU: Performs arithmetic and logical operations.
• FLAGS: Reflects the status of program.
• General purpose registers: Used to store Temporary data.
• Index and Pointer registers: Specifies/ informs about offset of
operand
8086
12
 8086 Architecture
BUS INTERFACE UNIT

• The BIU consists of the following:

o Segment Registers(CS,DS,ES,SS)
o Instruction pointer
o 6-Byte instruction Queue Register

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 8086 Architecture
Functions of BIU
• Handles transfer of data and address between processor
and memory / I/O devices.
• Compute physical address and send it to memory
interfaces.
• Fetches instruction codes and stores it in Queue.

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 8086 Architecture
Functions of various parts of BIU
• Segment registers : Used to hold the starting address of
the segment .
• Queue register: Used to store prefetched instructions and
inputs it to EU. which is an 6-byte FIFO register set. When
the EU is ready for its next instruction,it simply reads the
instruction byte(s) for the instruction from the queue
which is present in BIU.
• Instruction Pointer: Used to point to the next instruction
to be executed by EU.

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 Register organization of 8086
• The various registers available internal to 8086
microprocessors are :
1. Flag Register
2. General purpose registers
AX ( AH,AL)
BX (BH,BL)
CX (CH,CL)
DX (DH,DL)
3. Pointer and Index registers (IP,SP,BP & SI,DI)
4. Segment registers (ES, CS, DS,SS)

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 Register organization of 8086
Flag Register
• Flag register is part of EU.
• 8086 microprocessor has a 16-bit flag register.
• The flag register contents indicate the result of compuitation
in the ALU.It is also known as PSW ( Program Status Word).
• The flag register/psw can be divided into 2-parts:
Conditional /status flags
Machine Control flags
• 8086 microprocessor has 9- active flags
6- conditional flags
3- control flags
• Conditional flags: The lower byte of the flag register along
with overflow flag, they reflect the status of program.
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 Register organization of 8086
• Control Flags : Higher byte of the flag register , It has 3-
flags i.e., direction flag, interrupt flag and trap flag.
They control the working of machine(microprocessor)
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

X X X X O D I T S Z X AC X P X C
O  Overflow flag, D  Direction flag, I  Interrupt flag,
T  Trap flag, S  Sign flag, Z Zero flag,
AC  Auxiliary Carry flag, P  Parity flag
CY  Carry flag, X  Not used / Undefined

SET  1 & RESET  0.

8086 18
 Register organization of 8086
Flag Register
Condition flags
• Bit – 0 : CF (carry flag) — addition sets flag if carry
out of MSB generate; subtraction sets flag if
borrow needed.
• Bit –2 : PF (parity flag) — set to 1 if low-order 8
bits of result contain even number of 1’s.
• Bit – 4 : AF (auxiliary carry flag) — set if carry out
of bit 3 during addition or borrow by bit 3 during
subtraction.

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 Register organization of 8086
Flag Register
Condition flags
• Bit – 6 : ZF (zero flag) — set to 1 if result is 0; to 0
if result is nonzero
• Bit – 7 : SF (sign flag) —set to 1 if equal to MSB of
result is 1.Thus this flag indicates whether the
result is positive or negative.
• Bit – 11 : OF (overflow flag) — set if overflow
occurs (that is, the result can not be included in
the available capacity)

8086 20
 Register organization of 8086
Example – 1
• CF (carry flag) — carry out of 0011 0100 1101 1100
MSB
• PF (parity flag) — set to 1 if low- +0000 0111 0010 1110
order 8 bits (low order byte) 0011 1100 0000 1010
contain even number of 1’s CF = 0
• AF (auxiliary carry flag) —carry
out of bit 3 PF = 1
• ZF (zero flag) — set to 1 if result AF = 1
is 0; to 0 if result is nonzero
ZF = 0
• SF (sign flag) —MSB of result
• OF (overflow flag) — set if carry SF = 0
in to MSB is not equal to carry OF = 0
out from MSB)

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 Register organization of 8086
Example – 2
• CF (carry flag) — carry out of 1111 1111 1110 0101
MSB +1111 1111 1011 0001
• PF (parity flag) — set to 1 if low- 1 1111 1111 1001 0110
order 8 bits (low order byte) CF = 1
contain even number of 1’s
• AF (auxiliary carry flag) —carry PF = 1
out of bit 3 AF = 0
• ZF (zero flag) — set to 1 if result
is 0; to 0 if result is nonzero ZF = 0
• SF (sign flag) —MSB of result SF = 1
• OF (overflow flag) — set if carry OF = 0
in to MSB is not equal to carry
out from MSB)

8086 22
 Register organization of 8086
Flag Register
Control flags
• TF (trap flag) — if set, a trap is executed after
each instruction (single step execution).
• IF (interrupt enable flag) — if set, a maskable
interrupt can be recognized by the CPU;
otherwise, these interrupts are ignored.
• DF (direction flag) — used by string manipulation
instructions; if clear to 0, then process string from
low address to high; if set to 1, then process
string from high address to low.
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 Register organization of 8086
General Purpose Register
• In 8086 there are 4- general purpose registers i.e.,
AX,BX,CX,DX.
• These registers are of 16-bit size and can be used either as
a whole 16-bit register ( the letter X used in the
representation of the register indicates that the complete
16 – bit register is being used) or the upper and lower
bytes can be accessed separately ( the letters H and L
indicates the higher order and lower order bytes
respectively in the representation of the registers )
• The general purpose registers can be used to store both
operands and temporary results and each of them can be
accessed as whole or as sub-registers.

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 Register organization of 8086
General Purpose Register
• In addition to serving as general purpose registers
AX,BX,CX,DX have special uses as addressing, counting,
and I/O roles.
• The special uses of the general purpose registers is:
AX  used as accumulator
BX  used as a base register in address
calculation for some of the instructions
CX  used as an counter by certain instructions
(ex : Loop)
DX  used as a destination register in case of
multiplication and division instructions

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Register organization of 8086

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 Register organization of 8086
• Code segment register :It is used to address
the code segment of memory, where the
executable program is stored.
• Data segment register: is points to data
segment of memory, where the data is
resided.
• Extra segment register :It is another data
segment of memory. Thus extra segment also
contains data.
• Stack segment register: It is used to address
the stack segment of memory .which is used
to store stack data.
 Register organization of 8086
Pointer and index registers
•The 8086 contains 3 pointer registers(IP,SP,BP) and 2
index registers(SI,DI).All these registers are 16-bit
registers.
•The pointer registers contain the offsets with in the
particular segments as follows:
IP  Offset within the Code segment.
BP  Offset within the Data segment.
SP  Offset within the Stack segment.
•The SI register is used to store the offset of sourse data
in data segment, while DI register is used to store the
offset of destination in data in data or extra segment.
•The index registers are particularly useful for string
manipulations.

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Generation of 20-bit(physical) address

• The 8086 generates this address using contents

of segment registers & offset registers.
• For this, the contents of segment register also
called as segment address is shifted left bit-wise
by four times & to this result,contents of offset
register also called as offset address is added.
• The Bus Interface Unit(BIU) has a separate adder
to perform this procedure for obtaining physical
address.
 Generation of 20-bit(physical)
address
• For 20-bit physical address calculation the
contents of segment register is multiplied by
(10)16 or (16)10 and offset is added to it.
• 10hxsegment address+offset address
Generation of 20-bit(physical) address
Example:
Segment address- 1005H
Offset address - 5555H
Segment address-1005H- 0001 0000 0000 0101
Shifted by 4-bit positions-0001 0000 0000 0101 0000
+
Offset address - 0101 0101 0101 0101
Physical address -0001 0101 0101 1010 0101
1 5 5 A 5
 MEMORY SEGMENTATION
• As the 8086 microprocessor is an 16-bit
processor the segmentation will also use only
16-bit registers hence the whole 1 MB
memory can be divided into segments of
64KB .
 MEMORY SEGMENTATION
• Types of the segments:
The segments in the 8086 memory organization is of two
types:
Non-Overlapping segments
Overlapping segments
The classification of the types of segments is made
depending on how the base address is specified.
• Non-Overlapping Segments:
When ever the new logical segment is started only after
all the 64KB locations of present segment is completed
such type of segmentation is known as Non-Overlapping
Segments.

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 Memory segmentation
Non –overlapping segments:

Base address of Code Segment

Code Segment

Base address of Data Segment

Data Segment

Base address of Stack Segment

Stack Segment

Base address of Extra Segment

Extra Segment

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 Memory segmentation
Overlapping segments:In Overlapping
segments the next segments starts before the
present segment 64-KB are completed.
 Memory segmentation

Base address of Segment-1

Segment-1
End of Data/Code
64 KB
Starting of segment-2

Ending of segment-1

Segment-2

64 KB
Ending of segment-2

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 Advantages of memory segmentation

• It allows the placing of code,data and stack

portions of same program in different
segments for data & code protection.
• It allows programs to be relocatable.
 INTEL 8086 - Pin Diagram

RCET Microprocessor & Microcontroller 38

 Pin Definitions
Pin(s) symbol Description

1&20 GND ground

2-16 AD14-AD0 multiplexed address and data bus.it is seperated by

ALE pin.when it is high address bus is selected &
low data bus is selected.

17 NMI Non-maskable interrupt .it is not maskable by software

18 INTR interrupt request.It specifies the availability of request.

if any request is pendig processor gives
the acknowledgement by resetting IF flag(IF=0)

19 CLK It is a timing signal.which is asymetric square wave

with 33%duty cycle.

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 Pin Definitions

21 RESET It terminates the current activity

& starts execution

22 READY Indicates the trasfer of data

which
is ready
______
23 TEST when it is zero ,execution
will continues.when it is
one processor is in idle state

24-31 -- defined for minimum and maximum

mode

40
 Pin Definitions
32 RD ‘ indicates a memory or I/O read is to be
performed.

33 ___ CPU is in minimum mode when strapped to

MN / MX +5V and maximum mode when
grounded.

34 BHE’/S7 It is used to indicate the transfer of data

over higher order bus(D15-D8).

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 Pin Definitions
35-38 A19/S6 - during the first part of the bus cycle the
A16/S3
upper 4 bits of the address are output and
During the remainder of the bus cycle status
is output. S3 & S4 indicate the segment
register being used as follows:
S4 S3 Register
0 0 ES
0 1 SS
1 0 CS or none
0 0 DS
S5 gives the current setting of IF.
S6 is always 0.

39 AD15 same as AD14-AD0

40 VCC supply voltage +5V ±10%.

42
Minimum mode 8086 system

43
 Minimum mode 8086 system
• 8086 operated in minimum mode when
MN/MX’=1
• In this all the control signals are given out by
microprocessor chip itself.
• There is a single microprocessor in minimum
mode.
 Minimum mode system
___
24 INTA Indicates recognition of an interrupt request.

25 ALE outputs a pulse at the beginning of bus cycle and is to indicate an

address is available on the address pins.
____
26 DEN output during the latter portion of bus cycle and is to inform the
transceiver that CPU is ready to send or receive data.
___
26 DT / R indicates to the set of transceivers whether they are to transmit or
receive data.
__
26 M / IO distinguish memory transfer (logic 1) from an I/O transfer (logic 0).
__
26 WR when 0, it indicates a write operation is being performed.
27 HOLD Receives a bus request from bus masters.
28 HLDA outputs a bus grant to a requesting master.

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maximum mode 8086 system

46
 Maximum mode system
24,25 QS1,QS0 Reflects the status of the instruction queue.
__ __ __
26 – 28 S0,S1,S2 Indicates the type of transfer to take place during the current bus
cycle.
__ __ __
S2 S1 S0 QS1 QS0 Indication
0 0 0 Interrupt acknowledge 0 0 No operation
0 0 1 Read I/O port 0 1 First byte of op-
code
0 1 0 Write I/O port from the
queue
0 1 1 Halt 1 0 Empty Queue
1 0 0 Instruction fetch 1 1 Subsequent byte
from 1 0 1 Read memory the queue.
1 1 0 Write memory
1 1 1 Inactive – passive
_____
29 LOCK Indicates the bus will not be released to other potential bus
masters until the instruction with prefix LOCK is executed.
___ ___
30 RQ / GT1 for inputting bus requests and outputting bus grants.
___ ___ ___ ___ ___ ___ 47
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