Chapter 2

The 8086 Microcontroller Architecture

Aziza Umer

Department of Electrical and Computer Engineering

June 13, 2022

Outline I
Features of 8086 Microprocessor
Architecture of 8086
Bus Interface Unit(BIU)
Execution Unit (EU)
Register Organization
General purpose registers
Segment Register
Pointer and Index Register
Flag Registers
Bus Operation
Memory Segmentation
Physical, Offset, and Logical Addresses
Code Segment
Data Segment
Extra Segment
Stack Segment
Features of 8086 Microprocessor

I 16-bit microprocessor. (ALU, internal registers and most of

its instructions are designed to work with 16-bit binary words)
I 16-bit data bus. (can read/write data from/to memory and
ports either 16-bit or 8 bits at a time)
I 20-bit address bus. (can directly access 220 =
1,048,576=1Mb memory locations)
I Can generate 16-bit I/O address. (can access 216 =
65,536 I/O ports)
Features of 8086 Microprocessor
Cont...

I Provides fourteen 16-bit registers.

I Has multiplexed address and data bus. (reduces the number
of pins needed, but slow down the transfer of data)
I Possible to perform bit, byte, word and block operations.
I Designed to perform in two modes, namely the minimum
mode and the maximum mode:
I In the minimum mode only one processor is used and control
signals required by memory and I/O devices are issued by the
processor.
I In the maximum mode more than one processor is used and
control signals are generated with the help of external bus
controller(8288).
Features of 8086 Microprocessor
Cont...

I Supports multiprogramming. (the code for two or more

processes is in memory at the same time and is executed in a
time-multiplexed fashion)
I Supports pipelining.
I Range of clock rates:
I 5 MHZ for 8086
I 8 MHZ for 8086-2
I 10 MHZ for 8086-1
I Requires single +5v power supply.
Architecture of 8086
Architecture of 8086
Cont...

I Internally 8086 is divided into two separate functional units:

I Bus Interface Unit(BIU)
I Execution Unit(EU)
Architecture of 8086
Bus Interface Unit(BIU)

Functions of Bus Interface Unit

I Sends address of the memory or I/O
I Fetches instruction from memory
I Reads data from port/memory
I Writes data into port/memory
I Supports instruction queuing
I Provides address relocation facility
Architecture of 8086
Bus Interface Unit(BIU)

I To implement its functions the BIU contains instruction

queue, segment registers, instruction pointer, address
summer and bus control logic.
I To speed up program execution, the BIU fetches six
instruction bytes ahead of time from memory. These
pre-fetched instruction bytes are held for the execution unit in
a group of registers called Queue.
I To fetch the next instruction when current instruction is in
execution called pipeline.
I The queue operates on the principle of FIFO. EU gets the
instruction in the order they are fetched.
I The 8086’s main memory can be divided into 16 segments of
64K bytes each (16 x 64 KB = 1 MB). A segment may
contain codes or data. The 8086 uses 16-bit registers to
address segments.
Architecture of 8086
Execution Unit (EU)

I The execution unit of 8086 tells the CPU from where to fetch
instructions or data, decodes instructions and executes
instructions.
I It contains Control Circuitry, Instruction Decoder, ALU,
and Register Organization(General purpose registers,
Flag registers, Pointers and Index registers).
I The control circuitry in the EU directs and control the internal
operations.
I The decoder translates the instructions fetched from memory
into a series of actions which the EU performs.
Register Organization

General purpose registers

Register Organization
General purpose registers

I AX (A- Accumulator): used for instructions like MUL, DIV

and IN/OUT instructions.
I BX (B-Base register): used to store the EA of memory
location for data transfer between microprocessor and memory.
I CX (C- Counter register): Used as a counter for rotate, shift,
repeat and loop instructions.
I DX (D-Data register): in MUL and DIV operations if result is
of 32 bits, then register DX is used to store 16 MSBs and
register AX is used to store 16 LSBs. The 16-bit input and
output port is also stored in register DX.
Register Organization
General purpose registers

Operand/Temporary Register
I This register can not be used by the programmer. It is used
by the microprocessor to store any intermediate data or result.
ALU
I The different arithmetic operations performed in ALU are
addition, subtraction, multiplication, and division of binary
numbers, BCD numbers and ASCII code numbers.
I The logical operations performed are ANDing, ORing, and
EX-Oring, inverting, rotating data and shifting data.
Register Organization
Segment Register

I Code Segment:- The user cannot modify the content of

these registers. Only the microprocessor’s compiler can do
this.
I Data Segment:- It is used to store the data used by the
program. The user can modify the content of the data
segment.
I Stack Segment:- It handles memory to store data and
address during execution. The SS is used to store the
information about the memory segment. The operations of
the SS are mainly Push and Pop.
I Extra Segment:- It is an additional data segment used by
the string. By default, the control of the compiler remains in
the DS where the user can add and modify the instructions. If
there is less space in that segment, then ES is used. ES is also
used for copying purpose.
Register Organization
Pointer and Index Register

I Segment register is 16 bit wide

I Physical address of 8086 is 20 bit wide.
I To get 20 bit physical address one more register associated
with segment register.
Register Organization
Pointer and Index Register

The pointer and index register consists of

I Stack Pointer:- The Stack Pointer Points at the current top
value of the Stack. Like the BP, it also acts as an offset to
the Stack Segment (SS). The indexes are used with the
extra segment and they usually are used for copying the
contents of a particular block of memory to a new location.
[SP + SS] + 20 bit address
I Base Pointer:- The Base pointer stores the base address of
the memory. Also, it acts as an offset for Stack Segment
(SS). [BP + SS] + 20 bit address
I Source Index:- It stores the offset address of the source. [SI
+ DS] + 20 bit address
I Destination Index:- It stores the offset address of the
Destination. [DI + ES] + 20 bit address
Register Organization
Flag Registers
Flag Registers
I The Flag or Status register is a 16-bit register which contains
9 flags, and the remaining 7 bits are idle in this register.
These flags tell about the status of the processor after any
arithmetic or logical operation.
I If the flag value is 1, the flag is set, and if it is 0, it is said to
be reset.

I Six out of nine flags are used as status flags. Depending upon
the status of the result obtained in ALU, microprocessor will
store corresponding status bit 0/1 in this status..
Register Organization
Flag Registers
I Carry flag (CF): when there is carry out or borrow into of
MSB CF=1, otherwise CF=0.
I Auxiliary carry flag (AC): will be set to one if there is a
carry out of or a borrow into the MSB of the nibble.
I Parity flag (PF): set to 1 if result of byte operations or lower
byte of the word operation contain an even number of ones;
otherwise it is 0.
I Zero flag (ZF): set to 1 if the result of operation in ALU is
zero; otherwise it is 0.
I Sign flag (SF): if the result obtained is correct binary
number, then the sign flags bit will give correct sign of the
result. If SF=0/1, then the result is +ve/-ve respectively.
I Overflow flag (OF): when the sign binary result of the
8/16-bit is out of range then OF=1, and sign flag will be
incorrect..
I If carry/borrow into the MSB is equal to carry/borrow out of
the MSB, then the sign result is correct and OF=0.
Register Organization
Examples

I Give the contents of the flag registers after execution of the

following addition.
0110 0101 1101 0001
+ 0010 0011 0101 1001
I Trap flag (TF): used for single stepping through a program.
I Interrupt flag (IF): used to allow/prohibit the interruption of a
program.
I Direction flag (DF): if DF=0, the string is processed from its
beginning towards the high address.
Bus Operation

I The 8086 has a common address and data bus.

I The address data are time multiplexed (address and data
appear on the bus at different time intervals).
I The multiplexed address and data bus provides the most
efficient use of pins.
I The multiplexed address and data bus has to be
de-multiplexed externally with the use of latches and the ALE
signal provided by 8086.
Memory Segmentation

I Two types of memory organizations are commonly used:

linear addressing and segmented addressing.
I In linear addressing the entire memory space is available to
the processor in one linear array.
I In segmented addressing the available memory space is
divided into segments.
I In 8086 the memory is divided into 16 logical segments. Each
segment is 64kB in size and addressed by one of the segment
registers.
Memory Segmentation
Cont...

I The code segment contains the assembly language

instructions that perform the tasks that the program was
designed to accomplish.
I The data segment is used to store information (data) that
needs to be processed by the instructions in the code segment.
I The stack is used to store information temporarily.
I A segment is an area of memory that includes up to 64kB and
begins on an address evenly divisible by 16 (such an address
ends in 0H).
Memory Segmentation
Cont...
Memory Segmentation
Physical, Offset, and Logical Addresses

I Physical address is the 20-bit address that is actually put on

the address pins of the 8086 microprocessor and decoded by
the memory interfacing circuitry. It is an actual physical
location in RAM or ROM within the 1MB memory range.
I Offset address is a location within a 64kB segment range.
I Logical address consists of a segment value and an offset
address.
Memory Segmentation
Physical, Offset, and Logical Addresses

I The 16-bit contents of the segment register gives the

starting/base address of a particular segment.
I To address a specific memory location within a segment we
need an offset address.
I The offset address is also 16-bit wide and it is provided by one
of the associated pointer or index register.
Memory Segmentation
Physical, Offset, and Logical Addresses
Memory Segmentation
Code Segment

I To execute a program, the 8086 fetches the instructions

(op-codes and operands) from the code segment.
I The logical address of an instruction always consists of a CS
and an IP.
Memory Segmentation
Code Segment

Example
Memory Segmentation
Code Segment
Memory Segmentation
Data Segment

I While CS uses only the IP register as an offset, DS uses only

BX, DI, and SI to hold the offset address of the data.
Memory Segmentation
Data Segment
Memory Segmentation
Data Segment
Memory Segmentation
Data Segment
Memory Segmentation
Extra Segment

I ES is a segment used as an extra data segment.

I Although in many normal programs this segment is not used,
its use is absolutely essential for string operations.
Memory Segmentation
Stack Segment

I The stack is a section of read/write memory (RAM) used by

the CPU to store information temporarily.
I The CPU needs this storage area since there are only a limited
number of registers.
I The two main registers used to access the stack are the SS
register and the SP register. These registers must be loaded
before any instructions accessing the stack are used.
Memory Segmentation
Stack Segment

I The storing of a CPU register in the stack is called a push,

and loading the contents of the stack into the CPU register is
called a pop.
I In the 8086, the stack pointer register (SP) points at the
current memory location used for the top of the stack and as
data is pushed onto the stack it is decremented. It is
incremented as data is popped off the stack into the CPU.
I When an instruction pushes or pops a general purpose
register, it must be the entire 16-bit register. In other words,
one must code “PUSH AX”; there is no instruction such as
“PUSH AL”.
Memory Segmentation
Stack Segment

I To ensure that the code section and stack section of the

program never write over each other, they are located at
opposite ends of the RAM memory set aside for the program
and they grow toward each other but must not meet. If they
meet, the program will crash.
I As each PUSH is executed, the contents of the register are
saved on the stack and SP is decremented by 2.
I With every pop, the top 2 bytes of the stack are copied to the
register specified by the instruction and the stack pointer is
incremented twice. Although the data actually remains in
memory, it is not accessible since the stack pointer is beyond
that point.
Memory Segmentation
Stack Segment

I What values are assigned to the SP and SS, and who assigns
them?
I It is the job of the DOS to assign the values for the SP and
SS since memory management is the responsibility of the
operating system.
I The top of the stack is the last stack location occupied.
I BP is another register that can be used as an offset into the
stack, but it has very special applications and is widely used
to access parameters passed between assembly language
programs and high-level language programs.
Memory Segmentation
Stack Segment(Example)
Memory Segmentation
Stack Segment(Example)
Example
Example
Overlapping

I In calculating the physical address, it is possible that two

segments can overlap, which is desirable in some
circumstances.
Advantages of Memory Segmentation

I It allows the memory addressing capacity to be 1MB even

though the address associated with individual instruction is
only 16-bit.
I It allows instruction code, data, stack, and portion of a
program to be more than 64KB long by using more than one
code, data, stack segment, and extra segment.
I It facilitates use of separate memory areas for program, data
and stack.
I It permits a program or its data to be put in different areas of
memory, each time the program is executed which is very
useful in multiprogramming.