Unit-1 MPMC

Unit-1
8086 microprocessors
What is microprocessor ?
• A microprocessor is a computer processor that
incorporates the functions of a computer's
central processing unit (CPU) on a single
integrated circuit (IC).
• The microprocessor is a multipurpose,
programmabledevice that accepts digital data
as input, processes it according to instructions
stored in its memory, and provides results as
output
Cont…..
Generation of Microprocessor
• 1st Generation: This was the period during

1971 to 1973 of microprocessor’s history. In
1971, INTEL created the first microprocessor
4004 that would run at a clock speed of 108
KHz.
Cont…
• 2nd Generation: This was the period during
1973 to 1978 in which very efficient 8-bit
microprocessors -INTEL-8085.
• 3rd Generation: From 1979 to 1980, INTEL
8086/80186/80286 were developed. It is 16-
bit processor.Speeds of those processors were
four times better than the 2nd generation
processors.
Cont….
• 4th Generation:After 1980, INTEL 80386 &
80486 were developed. It is 32-bit processor.
Terms related to Microprocessors
• Bit
A digit of the binary number or code
• Nibble
The 4-bit binary number or code
• Byte
• Word
• Double Word
Terms related to Microprocessors
• Data
The quantity operated by an instruction of a
program is called data. The size of the data is
specified as Bit, Byte,Word……..
• Address
The address is an identification number in binary
for Memory locations. The 8086 processor uses
20-bit address for memory.
• Bus
A bus is a group of conducting lines that carries
data,address and control signals.
Features of 8086
• Introduced in 1978 .
• Comes in Dual-In-Line Package(DIP) IC.
• 8086 1s a 16-bit microprocessor .
• Works on 5 volts power supply.
• It is built on single semiconductor chip and
packaged in an 40-pin IC.
• It has 20-bit address bus and 16-bit data bus.
• It can directly address upto 220 I.e., 1M bytes of
memory.
• The maximum internal clock for 8086 is 5MHz
8086 9
8086 Architecture
• The architecture of 8086 is divided into two

functional parts i.e.,
i. Execution unit (EU)
ii. Bus interface unit (BIU)
• BIU and EU operate parallelly and independently
i.e., EU executes the instructions and BIU fetches
another instruction from the memory
simultaneously.
• As the whole architecture is divided into two
independent functional parts and both the
subsystem’s operations can be overlapped, hence
the architecture is PIPELINING type of architecture.
8086 11
8086 Architecture
EXECUTION UNIT
• The execution unit consists of the following:

 General purpose registers(AX,BX,CX,DX)
 Pointer & Index registers(SP,BP,SI,DI)
 ALU
 Flag register( FLAGS/ PSW)
 Instruction decoder
 Timing and control unit
8086 12
8086 Architecture
Functions of EU
• Receives opcode of an instruction from the queue.
• decodes the instructions.
• Executes the instruction.
Functions of various parts of EU
• Control circuitry: Directs internal operations.
• Instruction Decoder: Translates instructions fetched from
memory into series of actions.
• ALU: Performs arithmetic and logical operations.
• FLAGS: Reflects the status of program.
• General purpose registers: Used to store Temporary data.
• Index and Pointer registers: Specifies/ informs about offset of
operand
8086
13
8086 Architecture
BUS INTERFACE UNIT
• The BIU consists of the following:

o Segment Registers(CS,DS,ES,SS)
o Instruction pointer
o 6-Byte instruction Queue Register
8086 14
8086 Architecture
Functions of BIU
• Handles transfer of data and address between processor
and memory / I/O devices.
• Compute physical address and send it to memory
interfaces.
• Fetches instruction codes and stores it in Queue.
8086 15
8086 Architecture
Functions of various parts of BIU
• Segment registers : Used to hold the starting address of
the segment .
• Queue register: Used to store prefetched instructions and
inputs it to EU. which is an 6-byte FIFO register set. When
the EU is ready for its next instruction,it simply reads the
instruction byte(s) for the instruction from the queue
which is present in BIU.
• Instruction Pointer: Used to point to the next instruction
to be executed by EU.
8086 16
Register organization of 8086
• The various registers available internal to 8086
microprocessors are :
1. Flag Register
2. General purpose registers
AX ( AH,AL)
BX (BH,BL)
CX (CH,CL)
DX (DH,DL)
3. Pointer and Index registers (IP,SP,BP & SI,DI)
4. Segment registers (ES, CS, DS,SS)
8086 17
Flag Register
• Flag register is part of EU.
• 8086 microprocessor has a 16-bit flag register.
• The flag register contents indicate the result of compuitation
in the ALU.It is also known as PSW ( Program Status Word).
• The flag register/psw can be divided into 2-parts:
Conditional /status flags
Machine Control flags
• 8086 microprocessor has 9- active flags
6- conditional flags
3- control flags
• Conditional flags: The lower byte of the flag register along
with overflow flag, they reflect the status of program.
8086 18
• Control Flags : Higher byte of the flag register , It has 3-
flags i.e., direction flag, interrupt flag and trap flag.
They control the working of machine(microprocessor)
BIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X X X X O D I T S Z X AC X P X C
O  Overflow flag, D  Direction flag, I  Interrupt flag,
T  Trap flag, S  Sign flag, Z Zero flag,
AC  Auxiliary Carry flag, P  Parity flag
CY  Carry flag, X  Not used / Undefined
SET  1 & RESET  0.

8086 19
Flag Register
Condition flags
• Bit – 0 : CF (carry flag) — addition sets flag if carry
out of MSB generate; subtraction sets flag if
borrow needed.
• Bit –2 : PF (parity flag) — set to 1 if low-order 8
bits of result contain even number of 1’s.
• Bit – 4 : AF (auxiliary carry flag) — set if carry out
of bit 3 during addition or borrow by bit 3 during
subtraction.
8086 20
Flag Register
Condition flags
• Bit – 6 : ZF (zero flag) — set to 1 if result is 0; to 0
if result is nonzero
• Bit – 7 : SF (sign flag) —set to 1 if equal to MSB of
result is 1.Thus this flag indicates whether the
result is positive or negative.
• Bit – 11 : OF (overflow flag) — set if overflow
occurs (that is, the result can not be included in
the available capacity)
8086 21
Example – 1
• CF (carry flag) — carry out of 0011 0100 1101 1100
MSB
• PF (parity flag) — set to 1 if low- +0000 0111 0010 1110
order 8 bits (low order byte) 0011 1100 0000 1010
contain even number of 1’s CF = 0
• AF (auxiliary carry flag) —carry
out of bit 3 PF = 1
• ZF (zero flag) — set to 1 if result AF = 1
is 0; to 0 if result is nonzero ZF = 0
• SF (sign flag) —MSB of result
• OF (overflow flag) — set if carry SF = 0
in to MSB is not equal to carry OF = 0
out from MSB)
8086 22
Example – 2
• CF (carry flag) — carry out of 1111 1111 1110 0101
MSB +1111 1111 1011 0001
• PF (parity flag) — set to 1 if low- 1 1111 1111 1001 0110
order 8 bits (low order byte) CF = 1
contain even number of 1’s
• AF (auxiliary carry flag) —carry PF = 1
out of bit 3 AF = 0
• ZF (zero flag) — set to 1 if result ZF = 0
is 0; to 0 if result is nonzero
• SF (sign flag) —MSB of result SF = 1
• OF (overflow flag) — set if carry OF = 0
in to MSB is not equal to carry
out from MSB)
8086 23
Flag Register
Control flags
• TF (trap flag) — if set, a trap is executed after
each instruction (single step execution).
• IF (interrupt enable flag) — if set, a maskable
interrupt can be recognized by the CPU;
otherwise, these interrupts are ignored.
• DF (direction flag) — used by string manipulation
instructions; if clear to 0, then process string from
low address to high; if set to 1, then process string
from high address to low.
8086 24
General Purpose Register
• In 8086 there are 4- general purpose registers i.e.,
AX,BX,CX,DX.
• These registers are of 16-bit size and can be used either as
a whole 16-bit register ( the letter X used in the
representation of the register indicates that the complete
16 – bit register is being used) or the upper and lower
bytes can be accessed separately ( the letters H and L
indicates the higher order and lower order bytes
respectively in the representation of the registers )
• The general purpose registers can be used to store both
operands and temporary results and each of them can be
accessed as whole or as sub-registers.
8086 25
General Purpose Register
• In addition to serving as general purpose registers
AX,BX,CX,DX have special uses as addressing, counting,
and I/O roles.
• The special uses of the general purpose registers is:
AX  used as accumulator
BX  used as a base register in address
calculation for some of the instructions
CX  used as an counter by certain instructions
(ex : Loop)
DX  used as a destination register in case of
multiplication and division instructions
8086 26
•
8086 27
• Code segment register :It is used to address
the code segment of memory, where the
executable program is stored.
• Data segment register: is points to data
segment of memory, where the data is resided.
• Extra segment register :It is another data
segment of memory. Thus extra segment also
contains data.
• Stack segment register:It is used to address
the stack segment of memory .which is used to
store stack data.
Pointer and index registers
• The 8086 contains 3 pointer registers(IP,SP,BP) and 2 index
registers(SI,DI).All these registers are 16-bit registers.
• The pointer registers contain the offsets with in the
particular segments as follows:
IP  Offset within the Code segment.
BP  Offset within the Data segment.
SP  Offset within the Stack segment.
• The SI register is used to store the offset of sourse data in
data segment, while DI register is used to store the offset
of destination in data in data or extra segment.
• The index registers are particularly useful for string
manipulations.
8086 29
Memory Organization of 8086
• Memory Segmentation
Advantages of memory segmentation
Segmentation types
Non-overlapping Segmentation
Overlapping Segmentation
• Physical Address and Effective address
• Physical memory organization
Even Address
Odd Address
8086 30
• The processor provides a 20-bit address to memory which
locates the byte being referenced. The memory is logically
organized as a linear array of 1 million bytes, addressed as
00000(H) to FFFFF(H).
• In 8086 as there are 20-bit address bus it can address
directly upto 1 Mbytes of addresses but to handle this 20-
bit address internally all the registers of BIU has to be 20-
bits but this will increase the internal hardware logic as
well as the space required by the BIU,thus to avoid this
problem the concept of segmentation is introduced.
8086 31
• Segmentation:
Logically dividing the whole 1 MB memory into smaller
segments such that instead of referring to the whole 20-
bit address one can use and address with lesser bits for
accessing the memory location.
For this to happen there should be an base/ starting
address stored at some place and then address range of
addresses with reference to that base address which
requires lesser bits to be used to refer to an location.
As the 8086 microprocessor is an 16-bit processor the
segmentation will also use only 16-bit registers hence the
whole 1 MB memory can be divided into segments of
64KB (maximum)(the address spaces which can be
addressed using an 16-bit offset).
8086 32
• Thus the whole memory is logically divided into 16
segments of 64 KB locations each.
• The base address of the segment is stored in the segment
registers of 16-bit each placed in BIU.
• The offset of the location is stored in any of the pointer
registers depending on the addressing mode used.
• The default pointer register for code segment register is IP.
• The base addresses of the segment may be assigned as
0000H to F000H respectively and the offset address values
are from 0000H to FFFFH so that the physical address
ranges from 00000H to FFFFFH.
8086 33
• Advantages of memory segmentation:
 One advantage to have separate data and code
segments is that, one program can work on several
different sets of data. This is done by reloading data
segment register to point to new data.
 It allows programs to be loaded and run anywhere in
memory.
 It allows programs to be attended and recompiled
independently.
 It allows programs to be relocatable.
 It lends itself to sharing among processes.
 It lends itself to protection.
 It simplifies the handling of growing data structures.
 It reduces the number of bits required to address a
memory location.
8086 34
• Types of the segments:
The segments in the 8086 memory organization is of two
types:
Non-Overlapping segments
Overlapping segments
The classification of the types of segments is made
depending on how the base address is specified.
• Non-Overlapping Segments:
The simplest and conventional approach is to let both the
code and data reside in an contiguous area in memory and
put stack in some fixed area which always starts from a
fixed address.
8086 35
• Similar is the case with data and stack.
• When ever the new logical segment is started only after all
the 64KB locations of present segment is completed such
type of segmentation is known as Non-Overlapping
Segments.
Base address of Code Segment
Code Segment
Base address of Data Segment
Data Segment
Base address of Stack Segment

Stack Segment
Base address of Extra Segment
Extra Segment
8086 36
• Overlapping segments :
When the amount of data is not of size 64 KB then the
unused part of the memory is waste so to overcome the
problem of this memory wastage, Overlapping segments
are used.
In Overlapping segments the next segments starts before
the present segment 64-KB are completed.
Thus the unused part of the memory as in case of Non-
overlapping segmentation but, however the programmer
has to take care in selecting the starting address of the
next segment such that the starting address of the new
segment is divisible by 1610 or 1016
8086 37
.
Base address of Segment-1
Segment-1
End of Data/Code
64 KB
Starting of segment-2
Ending of segment-1
Segment-2
64 KB
Ending of segment-2
8086 38
• Physical address and effective address:
 Physical Address:
The actual 20-bit address that can be transferred on to
20-bit address bus.
 Effective Address:
The offset/ Displacement/ Distance from the starting
address of segment is known as effective address.
 Physical Address = ( Segment register contents) X 1610
+ Effective Address / Offset
8086 39
• Physical Address Generation:
EA
DS
Data Memory
2000 0H 0000H
20001H 0001H
20002H 0002H
20003H 0003H
22001H
2001H
22002H 2002H
22003H 2003H
2FFFBH FFFBH
2FFFCH FFFCH
2FFFDH FFFDH
2FFFEH FFFEH
2FFFFH FFFFH
8086 40
• Base Address:
The 20-bit starting memory location address of any
memory segment is called as base address.
• Physical Address:
Actual 20-bit address of any memory location is called as
physical address.The physical address of any memory
location is always fixed.
• Effective Address:
The displacement or offset of any memory location
measured from the base address is called as effective
address. EA (Effective Address) is stored in 16-bit registers
so maximum value of effective address will be FFFFH.
So one memory segment will consists of 216 = 64 K
locations.
8086 41
• EA ranges from 0000H to FFFFH. The combination of base
address and effective address (BA:EA) is called as logical
address.
Microprocessor will always transfer 20-bit physical address
to select any memory location. This physical address is
generated by 8086 is as given below:
BA = 16-bit 0000 20-bit
EA = + Memory Pointer 16-bit
PA = Σ 20-bit
8086 42
• Physical Memory Organization:
The 1Mbytes memory is physically organized as Odd bank
and Even bank, each of 512 Kbytes addressed in parallel
by processor.
Byte data with Even address is transferred on D7-D0, while
the byte data with Odd address is transferred on D15-D8
bus lines.
The processor provides two enable signals (BHE)’ and A0
for selection of either Even or Odd or Both the banks. The
instruction stream is fetched from memory as words and
is addressed internally by the processor as necessary.
8086 43
• If the processor fetches a word ( consecutive two bytes )
from memory, there are different possibilities likes:
 Both bytes may be Data operands.
 Both bytes may be Opcode bits.
 One of the bytes may be Opcode while the other may
be data.
In all the possibilities opcodes and operands are identified
by the internal decoder circuit which further derives the
signals those act as input to the timing and control unit.
The timing and control unit then derives all the signals
required for execution of the instruction.
8086 44
• When BIU fetches a word, the number of fetch cycles
required depends on whether the starting byte is located
at Odd address or Even address.
• For a byte starting at Even address, to fetch a word a
single memory cycle is enough.
• For a byte starting at Odd address, to fetch a word two
memory cycles are required, i.e., one for lower byte and
the next for the higher byte.
• Thus always it is preferable to keep or start our structure/
program at a even address.
• Fro structures like Stack they must be initialized at an even
address for efficient operation.
8086 45
• Certain locations in memory are reserved for specific CPU
operations such as the locations FFFF0H to FFFFFH are
reserved for operations including jump to initialization
program and I/O- Processor initialization.
• The locations 00000H to 003FFH are reserved for Interrupt
Vector Table , thus known as interrupt structure.
• The interrupt structure provides space for a total of 256
interrupt vectors.
Each interrupt vector need 4 bytes i.e., two bytes for CS
and two bytes for IP in the interrupt vector table.
Thus 256 types of interrupts require 256 X 4 = 03FFH (1 K
bytes) locations for the complete interrupt vector table.
8086 46
Generation of 20-bit(physical) address
• To access any memory location from any
segment we need 20-bit physical address.
• The 8086 generates this address using contents
of segment registers & offset registers.
• For this, the contents of segment register also
called as segment address is shifted left bit-wise
by four times & to this result,contents of offset
register also called as offset adderss is added.
• The Bus Interface Unit(BIU) has a separate
adder to perform this procedure for obtaining
physical address.
Generation of 20-bit(physical) address
Example:
Segment address- 1005H
Offset address - 5555H
Segment address-1005H- 0001 0000 0000 0101
Shifted by 4-bit positions-0001 0000 0000 0101 0000
+
Offset address - 0101 0101 0101 0101
Physical address -0001 0101 0101 1010 0101
1 5 5 A 5
Pin Diagram of 8086
RCET Microprocessor & Microcontroller 49

INTEL 8086 - Pin Diagram

INTEL 8086 - Pin Details
Power Supply
5V  10%
Ground
Reset
Terminate the
current
activity &
starts
execution
Clock
Timing signal
Address/Data Bus:
Contains address Address Latch Enable:
bits A15-A0 when ALE
is 1 & data bits D15 – When high,
multiplexed
D0 when ALE is 0.
address/data bus
contains address
information.

INTERRUPT
Non - maskable
interrupt
Interrupt
acknowledge
Interrupt request
Direct
Memory
Access
Hold
Indicates
the other
master
requesting
for bus
access
Hold
acknowledge

Address/Status Bus
Address bits A19 –
A16 & Status bits S6 –
S3

Bus High Enable/S7

Enables most
significant data bits
D15 – D8 during read
or write operation.
S7: Always 1.

Min/Max mode
Minimum Mode: +5V
Maximum Mode: 0V
Minimum Mode Pins
Maximum Mode
Pins

Minimum Mode- Pin Details
Read Signal
Write Signal
Memory or I/0
Data
Transmit/Receive
Data Bus Enable

Maximum Mode - Pin Details
S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access Status Signal
101: read memory Type of operation
110: write memory being carried out by
111: none -passive the processor.

Lock Output
Used to lock the
peripherals from gaining
the system bus, when it is DMA
Request/Grant
0.
Lock Output

QS1 QS0
00: Queue is idle
01: First byte of opcode
10: Queue is empty
11: Subsequent byte of
opcode
Queue Status
Indicates the status
of code-prefetch
queue
• TEST’: If this pin is 0,execution will continue,
else, processor is in idle state. it is a active low
signal.
• READY:it is a active high signal.it indicates
ready for data transfer,when this pin is high.
Minimum Mode 8086 System

• In a minimum mode 8086 system, the microprocessor

8086 is operated in minimum mode by strapping its
MN/MX pin to logic 1.
• In this mode, all the control signals are given out by the
microprocessor chip itself. There is a single
microprocessor in the minimum mode system.
• The remaining components in the system are latches,
transreceivers, clock generator, memory and I/O devices.
(cont..)
• Latches are generally buffered output D-type flip-
flops like 74LS373 or 8282. They are used for
separating the valid
• address from the multiplexed address/data signals
and are controlled by the ALE signal generated by
8086.
• Transreceivers are the bidirectional buffers and
some times they are called as data amplifiers. They
are required to separate the valid data from the time
multiplexed address/data signals.
• They are controlled by two signals namely, DEN and
DT/R.
‘Read’ Cycle timing Diagram for Minimum
Mode

• The read cycle begins in T1 with the assertion of
address latch enable (ALE) signal and also M / IO
signal.
• During the negative going edge of this signal, the
valid address is latched on the local bus.
• The BHE and A0 signals address low, high or both
bytes.
• From T1 to T4 , the M/IO signal indicates a memory
or I/O operation.
• • At T2, the address is removed from the local
bus and is
• sent to the output. The bus is then tristated.
The read (RD) control signal is also activated in
T2.
• The read (RD) signal causes the address
device to enable its data bus drivers.
• After RD goes low, the valid data is available
on the data bus
‘Write’ Cycle timing Diagram for Minimum
Mode

• A write cycle also begins with the assertion of
ALE and the emission of the address.
• The M/IO signal is again asserted to indicate a
memory or I/O operation.
• In T2, after sending the address in T1, the
processor sends the data to be written to the
addressed location.
• The data remains on the bus until middle of
T4 state. The
• WR becomes active at the beginning of T2
(unlike RD is somewhat delayed in T2 to
provide time for floating).
• • The BHE and A0 signals are used to select
the proper byte or bytes of memory or I/O
word to be read or write.
Maximum Mode 8086 System

Maximum Mode 8086 System
• Here, either a numeric coprocessor of the type 8087 or another
processor is interfaced with 8086.The Memory, Address Bus,
Data Buses are shared resources between the two processors.
• The control signals for Maximum mode of operation are

generated by the Bus Controller chip 8788. The three status
outputs S0’, S1’, S2’ from the processor are input to 8788.
• The outputs of the bus controller are the Control Signals,

namely DEN, DT/R’, IORC’, IOWTC’, MWTC’, MRDC’, ALE etc.

Memory Read timing in
Maximum Mode

Memory Write timing in
Maximum Mode

• Here the only difference between in timing
diagram between minimum mode and
maximum mode is the status signals used and
the available control and advanced command
signals.

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Unit-1

• 1st Generation: This was the period during

• The architecture of 8086 is divided into two

• The execution unit consists of the following:

• The BIU consists of the following:

SET  1 & RESET  0.

Base address of Data Segment

Base address of Stack Segment

Base address of Extra Segment

BA = 16-bit 0000 20-bit

EA = + Memory Pointer 16-bit

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Bus High Enable/S7

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Minimum Mode Pins

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Data Bus Enable

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• In a minimum mode 8086 system, the microprocessor

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• The control signals for Maximum mode of operation are

• The outputs of the bus controller are the Control Signals,

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