+

Chapter 3  A Top-Level View of Computer

 Function and Interconnection

William Stallings, Computer Organization and Architecture,9 th Edition

+ Objectives

 At top level, what are main components of a computer?

 How are they connected?
 After studying this chapter, you should be able to:
 Understand the basic elements of an instruction cycle and the role of
interrupts.
 Describe the concept of interconnection within a computer system.
 Understand the difference between synchronous and asynchronous bus
timing.
 Explain the need for multiple buses arranged in a hierarchy.
 Assess the relative advantages of point-to-point interconnection compared
to bus interconnection.
+
Contents
 3.1- Computer Components
 3.2- Computer Function
 3.3- Interconnection Structures
 3.4- Bus Interconnection
+
3.1- Computer Components
 Contemporary (nowaday) computer designs are based on concepts
developed by John von Neumann at the Institute for Advanced
Studies, Princeton

 Referred to as the von Neumann architecture and is based on three

key concepts:
 Data and instructions are stored in a single read-write memory
 The contents of this memory are addressable by location, without regard to
the type of data contained there
 Execution occurs in a sequential fashion (unless explicitly modified) from
one instruction to the next

 Hardwired program
 The result of the process of connecting the various components in the
desired configuration
+
Hardware
and Software
Approaches
 Software Software

●
A sequence of codes or instructions
●
Part of the hardware interprets each instruction and generates control signals
Provide a new sequence of codes for each new program instead of rewiring
I/O
●

the hardware
Components

Major components:
+

●
CPU
●
Instruction interpreter
●
Module of general-purpose arithmetic and logic functions
●
I/O Components
●
Input module
●
Contains basic components for accepting data and instructions and converting them into an internal form of signals usable by the system
●
Output module
●
Means of reporting results
 Memory address Memory buffer MEMORY
register (MAR) register (MBR)
• Specifies the address • Contains the data to
in memory for the be written into
next read or write memory or receives
the data read from
memory

MAR

I/O address I/O buffer register

register (I/OAR) (I/OBR)
• Specifies a particular • Used for the exchange
+ I/O device of data between an
I/O module and the
CPU
MBR
 Computer
Components:
Top Level
View
+
3.2- Computer Function

Basic Instruction Cycle

+
Fetch Cycle
 At the beginning of each instruction cycle the processor fetches an
instruction from memory

 The program counter (PC) holds the address of the instruction to be

fetched next

 The processor increments the PC after each instruction fetch so that

it will fetch the next instruction in sequence

 The fetched instruction is loaded into the instruction register (IR)

 The processor interprets the instruction and performs the required

action
Action Categories of actions

• Data transferred from processor to • Data transferred to or

memory or from memory to processor from a peripheral device
by transferring between
the processor and an I/O
module

Processor-
I/O
memory
Processor-

Control Data
processing

• An instruction may specify that the • The processor may

sequence of execution be altered perform some arithmetic
or logic operation on data
+ Instruction structure:

Opcode 4 bits  16 actions

Máy giả định

 + Example
of
Program
Execution
1940(h)
1(h): 0001
 Load AC from memory 940(h)

5941(h)
5(h) 0101
 Add to AC from memory 941(h)

2941(h)
2(h): 0010Store AC to memory 941

 Add 2 memory cell at addresses 940,

941. The result is stored at 941
+
Instruction Cycle State Diagram
+ Classes of Interrupts
CPU
Virtually all computers provide a
mechanism by which other modules 5V

(I/O, memory) may interrupt the

normal processing of the processor. An
interrupt can be caused by: IO Module
 Program Flow Control

Read
keyboard
+
Transfer of Control via Interrupts

- A controls B means that B must perform

all instructions from A.
- Hardware must perform actions
specified in each instruction
- Proccess controls hardware
+
Instruction Cycle With Interrupts

CPU
5V

OS decides whether CPU accepts

interrupt or not

IO Module
+

Program
Timing:
Short I/O
Wait
+

Program
Timing:
Long I/O
Wait
Instruction Cycle State Diagram
With Interrupts
 Transfer of
Control

Multiple
Interrupts

+
+ Time Sequence of Ex
Multiple Interrupts am
ple
+
I/O Function
 I/O module can exchange data directly with the processor

 Processor can read data from or write data to an I/O module

 Processor identifies a specific device that is controlled by a particular I/O
module
 I/O instructions rather than memory referencing instructions

 In some cases it is desirable to allow I/O exchanges to occur directly

with memory
 The processor grants to an I/O module the authority to read from or write
to memory so that the I/O memory transfer can occur without tying up the
processor
 The I/O module issues read or write commands to memory relieving (làm
giảm nhẹ) the processor of responsibility for the exchange
 This operation is known as direct memory access (DMA)
+ 3.3-
Interconne_
ction
Structures
The interconnection structure must support the following
types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory

An I/O
module is
allowed to
exchange
Processor Processor
Processor Processor data directly
reads an reads data
writes a unit sends data to with memory
instruction or from an I/O
of data to the I/O without going
a unit of data device via an
memory device through the
from memory I/O module
processor
using direct
memory
access
 Signals
Signals transmitted
transmitted by by any
any one
one device
device
munication
munication pathway
pathway are
are available
available for
for reception
reception byby all
all
cting
cting two
two or
or more
more devices
devices other
other devices
devices attached
attached toto the
the bus
bus

3.4-
characteristic
characteristic is
is that
that it
it is
is aa If
If two
two devices
devices transmit
transmit during
during the
the
dd transmission same
same time period their signals will
time period their signals
transmission medium
medium will
overlap and become garbled
overlap and become garbled

lly
lly consists

line
consists of
unication
unication lines
line is
of multiple
lines
is capable
multiple

capable of
of
Computer
Computer systems
number of
number
systems contain
of different
provide
contain aa
different buses
buses that
that
Bus
provide pathways
pathways between

Inter-
mitting between
mitting signals
signals components
senting components at
at various
various levels
levels of
of
senting binary
binary 11 and
and the
yy 00 the computer
computer system
system hierarchy
hierarchy

System
System bus
A
A bus
bus
bus that
that connects
connects major
major
The
The most
computer
most common
common
computer interconnection
interconnection
connec
structures
structures are
are based
based on
on the

tion
computer the
computer components
components use of one or more system
(processor, use of one or more system
(processor, memory,
memory, I/O)
I/O) buses
buses
Data Bus
 Data lines that provide a path for moving data among system
modules

 May consist of 32, 64, 128, or more separate lines

 The number of lines is referred to as the width of the data bus

 The number of lines determines how many bits can be transferred at a

time

 The width of the data bus

is a key factor in
determining overall
system performance
+ Address Bus Control Bus

 Used to designate the source or  Used to control the accessand the use of the
destination of the data on the data bus data and address lines
 If the processor wishes to read a
word of data from memory it puts  Because the data and address lines are shared
the address of the desired word on by all components there must be a means of
the address lines controlling their use

 Width determines the maximum  Control signals transmit both command and
possible memory capacity of the timing information among system modules
system
 Timing signals indicate the validity of data and
 Also used to address I/O ports address information
 The higher order bits are used to
select a particular module on the  Command signals specify operations to be
bus and the lower order bits select performed
a memory location or I/O port
within the module
Bus Interconnection Scheme
Fig. 3.17- Example Bus Configuration
Fig. 3.17- Example Bus Configuration
+ Elements of Bus Design

Dedicated: chuyên dụng, multiplex: đa thành phần

Synchronous- đồng bộ- At a time, only one device can uses the bus. The others must
wait until the bus is idle.
Arbitration: phân xử, quản lý
Asynchronous- không đồng bộ- At a time, some devices can use the bus concurrently
 Timing of
Synchronous
Bus Operations
 Timing of
Asynchronous
Bus
Operations
+
Questions
(Write answers to your notebook)

 3.1 What general categories of functions are specified by computer

instructions?

 3.2 List and briefly define the possible states that define an instruction
execution.

 3.3 List and briefly define two approaches to dealing with multiple
interrupts.

 3.4 What types of transfers must a computer’s interconnection

structure (e.g., bus) support?

 3.5 What is the benefit of using a multiple-bus architecture compared

to a single-bus architecture?
+
Building Block
Read by yourself
 3.5- Point-to-Point Interconnect

 3.6- PCI Express

+ Summary A Top-Level View of
Computer Function and
Interconnection
Chapter 3

 Computer components
 Computer function
 Instruction fetch and execute
 Interrupts
 I/O function
 Interconnection structures
 Bus interconnection
 Bus structure
 Multiple bus hierarchies
 Elements of bus design