Chapter 2
Chapter 2
Chapter 2
Chapter 2
COMPUTER
FUNCTION
Contents
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Computer Components
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What is a program
A sequence of steps
For each step, an
arithmetic or logical
operation is done
For each operation, a
different set of control
signals is needed
Also need temp storage
(memory) and way to get
input and output
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Software
A sequence of codes or instructions
Part of the hardware interprets each instruction and generates
control signals
Provide a new sequence of codes for each new program instead
of rewiring the hardware
Major components:
CPU
Instruction interpreter
Module of general-purpose arithmetic and logic functions
I/O Components
Input module : Contains basic components for accepting data and
instructions and converting them into an internal form of signals usable
by the system
Output module : Means of reporting results
Memory
Memory address Memory buffer
register (MAR) register (MBR)
• Specifies the • Contains the data
address in memory to be written into
for the next read or memory or
write receives the data
read from memory
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Computer system
At the most basic level, a computer is a device consisting of
four parts:
A processor to interpret and execute programs
A memory to store both data and programs
A mechanism for transferring data to and from the outside
world.
Bus (interconnection among parts)
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Instruction Cycle
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Fetch Cycle
Execute Cycle
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Explain
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Interrupt
Classes of Interrupts
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Software Interrupts
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Interrupt processing
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Interrupt Cycle
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Program timing
Long IO wait
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Multiple Interrupts
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Sequential interrupt
Processing
Nested interrupt
Processing
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Exception Table
code for
exception handler 0
Exception code for
Table exception handler 1
0
1 code for
2 exception handler 2
...
n-1
...
code for
Exception
exception handler n-1
numbers
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I/O Function
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I/O Module
IO systems
IO peripherals
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Questions to investigate:
How does the CPU communicate with I/O
devices?
How do I/O devices communicate with the CPU?
How to transmit data efficiently, without errors?
How to connect the I/O devices to the CPU?
IO addressing
According to address separation there are two
possibilities:
Separate I/O and Memory address space
Shared I/O and Memory address space
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Alternative implementation
The CPU has a shared bus for the I/O and the
memory
A selector signal determines the target of the
communication
More cost effective (less wires)
Example: x86
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Memory mapped IO
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I/O Space
It is important to notice that these I/O addresses are
NOT memory-mapped addresses on the 80x86
machines.
Special instructions (IN/OUT)
Memory
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Interconnection Structures
Computer modules
Computer is a network of basic modules.
There must be paths for connecting the modules.
The collection of paths connecting the various modules is called
the interconnection structure. The design of this structure will
depend on the exchanges that must be made among modules.
Computer Modules
Memory modul :
A memory module will
consist of N words of equal
length.
Each word is assigned a
unique numerical address (0,
1, …, N - 1)
A word of data can be read
from or written into the
memory.
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IO modul :
Function similar to memory.
An I/O module may send interrupt signals to the processor.
Processor
The processor reads in instructions and data, writes out data
after processing, and uses control signals to control the overall
operation of the system.
The processor also receives interrupt signals.
Types of transfers
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Bus interconnection
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System Bus
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Bus Structure
Multiple-Bus Hierachies
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Multiple-Bus Hierachies
High-performance architecture
Data Bus
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Address Bus
Control Bus
Used to control the access and the use of the data and
address lines
Because the data and address lines are shared by all
components there must be a means of controlling their
use
Control signals transmit both command and timing
information among system modules
Timing signals indicate the validity of data and address
information
Command signals specify operations to be performed
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Bus Types
Dedicated (functional)
Separate data & address lines
Multiplexed (Time multiplexing)
Shared lines
Address valid or data valid control line
Advantage - fewer lines
Disadvantages
More complex control
Performance – cannot have address and data simultaneously on
bus
Dedicated (physical)
Bus connects subset of modules
Example: all I/O devices on a slow bus
Provides high throughput, but cost and complexity increase
Bus Arbitration
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Timing
Synchronous diagram
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Asynchronous Timing
Asynchronous diagram
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Bus Width
Example of Bus
Address:
If I/O, a value between 0000H and FFFFH is issued.
If memory, it depends on the architecture:
20 -bits (8086/8088)
24 -bits (80286/80386SX)
25 -bits (80386SL/SLC/EX)
32 -bits (80386DX/80486/Pentium)
36 -bits (Pentium Pro/II/III)
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Data:
8 -bits (8088)
16 -bits (8086/80286/80386SX/SL/SLC/EX)
32 -bits (80386DX/80486/Pentium)
64 -bits (Pentium/Pro/II/III)
Control:
Most systems have at least 4 control bus connections
(active low).
MRDC (Memory ReaD Control), MWRC , IORC
(I/O Read Control), IOWC
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