+

Lec02 - Computer Function and

Interconnection
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Contents

Computer components

Computer function

Interconnection structures

Bus interconnection

PCI Express
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Computer Components

Contemporary computer designs are based on concepts

developed by John von Neumann at the Institute for
Advanced Studies, Princeton

Referred to as the von Neumann architecture and is based on

three key concepts:
Data and instructions are stored in a single read-write memory
The contents of this memory are addressable by location, without
regard to the type of data contained there
Execution occurs in a sequential fashion (unless explicitly
modified) from one instruction to the next

Hardwired program
The result of the process of connecting the various components in
the desired configuration
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Hardware
and Software
Approaches
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Software
• A sequence of codes or instructions
• Part of the hardware interprets each instruction and Software
generates control signals
• Provide a new sequence of codes for each new
program instead of rewiring the hardware
Major components:
• CPU I/O
• Instruction interpreter
Components
• Module of general-purpose arithmetic and logic
functions
• I/O Components
• Input module
+ • Contains basic components for accepting data
and instructions and converting them into an
internal form of signals usable by the system
• Output module
• Means of reporting results
• Main memory
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Main Memory

Store instructions temporarily:

Input device will bring instructions and data in sequentially
But a program is not invariably executed sequentially; it may jump
around

Store data temporarily:

Operations on data may require access to more than just one
element at a time in a predetermined sequence

Von Neumann pointed out that the same memory could be

used to store both instructions and data
 Address Buffer 7

Memory Memory buffer MEMORY

address register (MBR)
Memory

register (MAR) • Contains the data

• Specifies the to be written into
address in memory memory or
for the next read or receives the data
write read from memory

MAR

I/O address I/O buffer

register (I/OAR) register (I/OBR)
• Specifies a • Used for the
I/O

+ particular I/O exchange of data

device between an I/O
module and the
CPU MBR
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Computer
Components:
Top Level
View
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Computer Function

The basic function is execution of a program, which

consistsof a set of instructions stored in memory.

In simplest form, instruction processing consists of two steps:

Fetch - The processor reads instructions from memory one at a
time.
Execute – The processor executes each instruction.
Program execution consists of repeating the process of instruction
fetch and instruction execution.

The processing required for a single instruction is called an

instruction cycle.
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Basic Instruction Cycle

In simplest form, instruction processing consists of two steps:

fetch and execute.
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Registers for Instruction Execution

Memory buffer • Is used to receive a word from memory

register (MBR) or from the I/O unit

Memory address • Specifies the address in memory of the

register (MAR) word to be read into the MBR

Instruction register • Contains the instruction being

(IR) executed

• Contains the address of the next

Program counter (PC) instruction pair to be fetched from
memory
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Fetch Cycle
At the beginning of each instruction cycle the processor
fetches an instruction from memory

The program counter (PC) holds the address of the

instruction to be fetched next

The processor increments the PC after each instruction

fetch so that it will fetch the next instruction in sequence

The fetched instruction is loaded into the instruction

register (IR)

The processor interprets the instruction and performs the

required action
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Instruction’s Action Categories

• Data transferred from • Data transferred to or

processor to memory or from a peripheral
from memory to device by transferring
processor between the
processor and an I/O
module
Processor- Processor-
memory I/O

Data
Control
processing

• An instruction may • The processor may

specify that the perform some
sequence of execution arithmetic or logic
be altered operation on data
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Simple
Example
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Example
of
Program
Execution
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Instruction Cycle State Diagram

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Instruction Cycle State Diagram (2)

Instruction address calculation (iac): Determine the address of the next

instruction to be executed. Usually, this involves adding a fixed number to
the address of the previous instruction. For example, if each instruction is 16
bits long and memory is organized into 16-bit words, then add 1 to the
previous address. If, instead, memory is organized as individually
addressable 8-bit bytes, then add 2 to the previous address.

Instruction fetch (if): Read instruction from its memory location into the
processor.

Instruction operation decoding (iod): Analyze instruction to determine

type of operation to be performed and operand(s) to be used.

Operand address calculation (oac): If the operation involves reference to

an operand in memory or available via I/O, then determine the address of
the operand.

Operand fetch (of): Fetch the operand from memory or read it in from I/O.

Data operation (do): Perform the operation indicated in the instruction.

Operand store (os): Write the result into memory or out to I/O.
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Classes of Interrupts
Virtually all computers provide a mechanism by which
other modules (I/O, memory) may interrupt the normal
processing of the processor.
Program Flow Control 19

1, 2, 3 – code segments
4 – I/O preparation
5 – code to complete I/O
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Transfer of Control via Interrupts

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Instruction Cycle With Interrupts

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Program
Timing:
Short I/O
Wait
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Program
Timing:
Long I/O
Wait
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Instruction Cycle State Diagram
With Interrupts
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Transfer of
Control

Multiple
Interrupts

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Multiple Interrupts

Two approaches:
1. Disable other interrupts
Processor can and will ignore other interrupt request
signal while completing the current interrupt
If an interrupt occurs during this time, it generally
remains pending and will be checked by the processor
after the processor has enabled interrupts.
Nice and simple
2. Define priorities
Allow an interrupt of higher priority to cause a lower-
priority interrupt handler to be itself interrupted
+ Time Sequence of 27
E me
x p
Multiple Interrupts a l
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I/O Function
I/O module can exchange data directly with the processor

Processor can read data from or write data to an I/O module

Processor identifies a specific device that is controlled by a
particular I/O module
I/O instructions rather than memory referencing instructions

In some cases it is desirable to allow I/O exchanges to occur

directly with memory
The processor grants to an I/O module the authority to read from
or write to memory so that the I/O memory transfer can occur
without tying up the processor
The I/O module issues read or write commands to memory
relieving the processor of responsibility for the exchange
This operation is known as direct memory access (DMA)
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29

Computer
Modules
The interconnection structure must support the 30

following types of transfers:

Memory Processor I/O to or

I/O to Processor
to to from
processor to I/O
processor memory memory

An I/O
module is
allowed to
exchange
data
Processor Processor
directly
reads an Processor reads data Processor
with
instruction writes a from an I/O sends data
memory
or a unit of unit of data device via to the I/O
without
data from to memory an I/O device
going
memory module
through the
processor
using direct
memory
access
 31
A communication pathway Signals transmitted by any one
connecting two or more device are available for
devices reception by all other devices
attached to the bus
• Key characteristic is that it is a
shared transmission medium • If two devices transmit during the I
same time period their signals will
overlap and become garbled n
n
e
Typically consists of multiple t
communication lines
• Each line is capable of transmitting
Computer systems contain a
number of different buses that
B c
signals representing binary 1 and
binary 0
provide pathways between e
components at various levels of
the computer system hierarchy u t
r
s i
c
System bus
• A bus that connects major o
computer components (processor,
memory, I/O)
The most common computer
interconnection structures are o
based on the use of one or
more system buses n
n
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Data Bus
Data lines that provide a path for moving data among system
modules

May consist of 32, 64, 128, or more separate lines

The number of lines is referred to as the width of the data bus

The number of lines determines how many bits can be

transferred at a time

The width of the data bus

is a key factor in
determining overall
system performance
+ Address Bus Control Bus
33

Used to designate the source or Used to control the access and the
destination of the data on the use of the data and address lines
data bus
If the processor wishes to Because the data and address lines
read a word of data from are shared by all components there
memory it puts the address of must be a means of controlling their
the desired word on the use
address lines
Control signals transmit both
Width determines the maximum command and timing information
possible memory capacity of the among system modules
system
Timing signals indicate the validity
Also used to address I/O ports of data and address information
The higher order bits are
used to select a particular Command signals specify operations
module on the bus and the to be performed
lower order bits select a
memory location or I/O port
within the module
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Bus Interconnection Scheme

If one module wishes to send/request data to/from

another:
1. obtain the use of the bus
2. transfer data/request via the bus
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C
o a
n t
B
f i
u
i o
s
g n
u s
r
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Elements of Bus Design

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Peripheral Component
Interconnect (PCI)
A popular high bandwidth, processor independent bus that can
function as a peripheral bus

Delivers better system performance for high speed I/O

subsystems

PCI Special Interest Group (SIG)

Created to develop further and maintain the compatibility of the PCI
specifications

PCI Express (PCIe)

Point-to-point interconnect scheme intended to replace bus-based
schemes such as PCI
Key requirement is high capacity to support the needs of higher data rate
I/O devices, such as Gigabit Ethernet
Another requirement deals with the need to support time dependent data
streams
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PCIe
Configuration
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PCIe Multilane Distribution

+ Summary
40

Computer Function
and Interconnection
Lec02
PCI express
Computer components
PCI physical and logical
Computer function
architecture
Instruction fetch and
execute
Interrupts
I/O function
Interconnection structures
Bus interconnection
Bus structure
Multiple bus hierarchies
Elements of bus design